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DEPARTMENT OF Electronics and Communication Engineering

COURSE PLAN

Department : Electronics and Communication Engg.

Subject : VLSI Design (ECE 305)

Semester & branch : V Sem ECE

Name of the faculty : Dr. D. V. Kamath, Mr Shailendra K. Tiwari

and Mr. Om Prakash

No of contact hours/week : 4

Assignment portion

Assignment no. Topics

1 L1 L13

2 L14 L26

3 L27 L50

Test portion

Test no. Topics

1 L1 L20

2 L21 - 41

Submitted by: Prof. D. V. Kamath

(Signature of the faculty)Date: 6-8-2013

Approved by:

(Signature of HOD)Date: 6-8-2013

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MANIPAL INSTITUTE OF TECHNOLOGY(A constituent college of Manipal University, Manipal)

Manipal Karnataka 576 104

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Course Objectives

At the end of this course, the student will be able to:

CO1: Describe Moors Law and its significance in VLSI.CO2: List and discuss the key performance parameters related to ICs.

CO3: Explain the operation of MOS devices and derive the expressions for the draincurrent.

CO4: Analyze NMOS & CMOS inverter circuits and estimate the key parameters.

CO5: Design combinational circuits using switch logic and gate logic and compare them.

CO6: Discuss the design of sequential circuits in VLSI.

CO7: Discuss the design issues related to memory circuits.CO8: Describe the process of fabrication of MOS and CMOS devices using suitable

sketches and compare different types of processes.

CO9: Draw layouts for VLSI circuits as per the design specifications and estimate theparasitic values.

CO10: Estimate the delay and power dissipation in CMOS.

CO11: Describe scaling in CMOS and compare different types of scaling

CO12: List and Describe various issues involved in subsystem design.

Course Plan

L/TSl No.

Topics

L1 Introduction to VLSI Design, Performance measures and issues.

L2 Discussion of Moores law and VLSI technology trendsL3 Discussion of MOSFET and types, operation and concept of threshold

voltage

L4 Tutorial

L5 Study of depletion and enhancement mode MOSFET with VI

characteristics

L6 Derivation of equation for drain current and discussion of their

significance.

L7 Discussion of second-order effects

L8 TutorialL9 Pass transistors and transmission gates.

L 10 Analysis of NMOS inverters

L11 Analysis of CMOS inverters

L12 Tutorial

L 13 Discussion of the impact of device ratios on the performance of inverter

L 14 Implementation of Boolean functions and combinational circuits using

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switch logic and gate logic.

L 15 Designing of arbitrary logic using CMOS

L16 Tutorial

L 17 NMOS fabrication

L18 CMOS fabrication: Discussion of P-well & N-well process

L19 Discussion of Twin-tub process, Latch up in CMOS and its prevention.L 20 Tutorial.

L 21 SOI process of CMOS fabrication, VLSI yield and economics

L 22 Stick diagrams.

L23 Design rules and Layouts

L 24 Tutorial.

L25 Representation of logic circuits in stick notation and drawing layouts.

L 26 Concept of sheet resistance, standard unit of capacitance, delay unit,

resistance and area capacitance calculation

L27 Estimation of NMOS inverter pair delay, CMOS inverter delay.

L 28 Tutorial.L29 Driving of large capacitive loads.

L 30 Super buffers, Discussion of power dissipation.

L31 Pseudo NMOS

L32 Tutorial.

L33 Dynamic and clocked CMOS logic.

L 34 Clocking strategies: single and two phase clocking

L 35 Flip flops, shift registers and clocked sequential circuits

L 36 Tutorial.

L 37 Memory systems like, ROM, EPROMs and PLAs

L38 Static and dynamic memory cells

L 39 Scaling of MOS devices

L40 Tutorial.

L41 Design description domains and design strategies

L42 Issues in subsystem design.

L43 Design examples such as ALUs, Bus arbitration logic, Parity generation

L44 Tutorial

L45 Design of Shifters

L46 Trends in VLSI technology: GaAs, BiCMOS

L47 Introduction to GaAs technology: basic properties, merits, demerits and

applications

L48 Introduction to BiCMOS design: circuits and application areasL49 Tutorial

L50 Introduction to Low power VLSI, Analog and mixed signal design

EVALAUTION SCHEME:

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IN SEMESTER TESTS: - 40 %

ASSIGNMENTS: - 10%

END SEMESTER EXAM: - 50%

Total: - 100%

References:

1. Pucknell D. A and Eshraghian K, Basic VLSI Design,PHI Publication, 2009.

2. West N and Eshraghian K, Principles of CMOS VLSI Design, Addison Wesley

Publication, 2nd Edition.3. Amar Mukherjee, Introduction to NMOS & CMOS VLSI systems Design,

Prentice Hall, 1986.

4. Jan M Rabaey, Digital Integrated Circuits,Prentice Hall India, 2003

5. Sung Mo Kang and Yusuf leblebici, CMOS digital Integrated circuits design andanalysis, Tata Mcgraw Hill, 3rd edition.

6. Allen, CMOS Analog Circuit Design, Oxford University Press.,2nd Edition

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