course topics - outline - biu · 7 event-based timing control event is a change in value on...
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Course Topics - Outline
Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 – Behavioral modeling B Lecture 7 – Behavioral modeling C Lecture 8 – Data flow modeling Lecture 9 – Gate Level modeling Lecture 10 – Tasks and Functions Lecture 11 – Advanced Modeling Techniques Lecture 12 - Coding Styles and Test Benches Lecture 13 -Switch Level modeling
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Lecture 6 - Behavioral modeling B
Timing Control mechanism Delay-based - # Inter-Statement Delay Intra-Statement Delay
Event-based - @ Regular event control – posedge, negedge Named event control - event Event OR control – (a or b or ..) Level-sensitive timing control - wait
Conditional Statements - If, else Multi-way Branching - case, casex, casez Exercise 6
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Timing Control
Various behavioral timing control constructs are available in Verilog.
If there are no timing control statements, simulation time, does not advance.
Timing controls provide a way to specify simulation time at which procedural statements will execute.
There are three methods of timing control:
Delay-based Timing Control
Event-based Timing Control
Level-sensitive Time Control - Wait Statement
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Delay-based Timing Control
Delay Control (#) - Expression specifies the time duration between initially encounter a statement and when statement actually executes.
- Delay in Procedural Assignments
• Inter-Statement Delay // Regular Delay
• Intra-Statement Delay
For example:
• Inter-Statement Delay
#10 A = A + 1 ;
• Intra-Statement Delay
A = #10 A + 1 ;
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Examples – Regular (inter) Delay Control
// Define parameters parameter latency = 20 ; parameter delta = 2 ; reg x, y, z, p, q ; // define register variables initial begin x = 0 ; // No delay control #10 y = 1 ; // Delay control with number #latency z = 0 ; // Delay control with identifier #(latency + delta) p = 1 ; // Delay control with expression #y x = x + 1 ; // Delay control with identifier #(4:5:6) q = 0 ; // min., typ. and max. delay values end
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Examples – Intra-assignment Delay Control
Unlike inter-assignment in intra-assignment delay is assign to the right of the assignment operator.
Such delay alters the flow of activity in a different manner. Example: The contrast between intra and inter assignments reg x, y, z ; initial // intra-assignment begin x = 0 ; z = 0 ; y = #5 x + z ; /* takes value of x and z @ time=0, evaluate x + z and end then wait 5 time units to assign value to y */ initial // inter-assignment method with temporary variables begin x = 0 ; z = 0 ; temp_xz = x + z ; /*stores x and z values @ current time in temp variable. x and z might change between 0 and 5 but the value assigned to y @ time 5 is unaffected */ #5 y = temp_xz ; end
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Event-based Timing Control
Event is a change in value on register or a net
There are 4 types of event-based timing control: - Regular event control - Named event control - Event OR control - Level-sensitive timing control
The symbol @ is used to specify an event control
Statements can be executed on changes in signal value or at a positive or negative transition of the signal value
The keyword posedge is used for a positive transition
The keyword negedge is used for a negative transition
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Event-based Timing Control – cont.
Regular event control
@(clock) q = d ; /* q = d is executed whenever clock
changes value */
@(posedge clock) q = d ; /* q = d is executed whenever
clock does a positive transition ( 0 to 1, x or z) */
@(negedge clock) q = d ; /* q = d is executed whenever
clock does a negative transition
( 1 to 0, x or z, x to 1, z to 1) */
q = @(negedge clock) d ; /* d is evaluated immediately
and assigned to q at the positive edge of clock */
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Named event control
Verilog provides the capability to declare an event and then trigger and recognize the occurrence of that event.
Event does not hold any data.
A named event is declared by the keyword event. An event is triggered by the symbol ->.
Triggering of the event is recognized by the symbol @.
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Example - Named event control
// A data buffer stores data after the last data packet has arrived event received_data ; // define an event called received_data
always @(posedge clock) // check at each positive clock edge begin if (last_data_packet) // If this is the last data packet ->received_data ; // trigger the event received_data
end always @(received_data) /* Await triggering of event received_data When the event is triggered, store all 4 packets of received data in data buffer Use concatenation operator { } */
data_buf = {data_pkt[0], data_pkt[1], data_pkt[2], data_pkt[3]} ;
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Event OR and Edge-sensitive Control
Transition of any one of multiple signals or events can trigger execution of a statement or a block of statements
The list of events or signals is also known as a sensitivity list The keyword or (or “,”) is used to specify multiple triggers always @(reset or en or d) ; // D latch with reset begin // wait for reset or en or d to change if (reset) // if reset signal is high, set q to 0 q <= 1’b0 ; else if (en) // data latch enabled q <= d ; end always @(posedge clk, negedge nrst) /* D-FF with asynchronous reset. Executed whenever clk swings to 1 or nrst to 0 */ begin if (!rst) q <= 1’b0 ; else q <= d ; end
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Level-sensitive Time Control - Wait Statement
Wait statement waits for its conditional expression to become true before a statement or a block of statements is executed
Level sensitive Primary used for synchronizing two concurrent processes. The keyword wait is used for level-sensitive constructs Example: always wait (count_enable) #20 count = count + 1 ; // The value of count_enable is monitored continuously.
If count_enable = 0, the statement is not entered. If it is logical 1, the statement is executed after 20 time units. If count_enable stays at 1, count will be incremented every 20 time units.
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Conditional Statements
Used to make decisions based upon certain conditions.
Keywords if and else are used for conditional statements.
Syntax: - if <expression> true statement ; - if <expression> true statement ; else false statement ; - if <expression1> true statement1 ; // many alternatives
else if <expression2> true statement2 ; else if <expression3> true statement3 ; ………… else default statement ;
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Conditional Statement example – 2 to 1 Mux
//Behavioral model of 32-bitwide 2-to-1 multiplexor.
module mux32 (in0, in1, select, out) ;
input [31:0] in0, in1 ;
input select ;
output reg [31:0] out ; // implicit register
always @ (in0 or in1 or select) // Event OR control
if (select) out = in1 ; // if-else condition
else out = in0 ;
endmodule
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Conditional Statement example - 4 to 1 Mux
module multiplexor4_1 (out, in1, in2, in3 ,in4, cntrl1, cntrl2) ; input in1, in2, in3, in4, cntrl1, cntrl2 ; output reg out ; always @(in1 or in2 or in3 or in4 or cntrl1 or cntrl2)
begin // A block is grouped between begin and end if (cntrl1==1) if (cntrl2==1) out = in4 ; else out = in3 ; else if (cntrl2==1) out = in2 ; else out = in1 ; end endmodule
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Conditional Statement example - BCD Adder
module BCDadder (sum, cout, a, b, cin) ; input [3:0] a, b ; Input cin ; output reg [3:0] sum ; output reg cout ; reg [4:0] z ; always @(a or b or cin) begin z = a + b + cin ; if (z > 9) {cout, sum} = z + 6 ; // 1011 + 0110 = 1_0001 = 11d else {cout, sum} = z ; end endmodule
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Multi-way Branching
Having many alternatives, using nested if-else-if is not practical. An easier way is to use the case statement
The keywords case, endcase and default are used. Comparisons in a case statement are made bit by bit. No break statement needed - first match executes and then case
is exited.
If not all cases are enumerated, make sure to use default case.
Multi way branching - case statement case <expression> alternative1: statement1 ; alternative2: statement2 ; ……………………………………. ; default: default_statement ; // missing alternative - avoid latch endcase
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case statement example - 4to1 mux
module mux4to1 (in0, in1, in2, in3, select, out) ;
input in0, in1, in2, in3 ;
input [1:0] select ;
output reg out ; // note: out must be a register
always @(in0 ,in1, in2, in3, select)
case (select)
2’b00: out = in0 ;
2’b01: out = in1 ;
2’b10: out = in2 ;
2’b11: out = in3 ;
endcase // No need for default case
endmodule
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case statement example - 2 to 4 Decoder
module dec2to4 (y, w, en) ; input [1:0] w ; input en ; output reg [3:0] y ; always @(w or en) case ({en, w}) // concatenation of enable & w 3’b100: y = 4’b0001 ; 3’b101: y = 4’b0010 ; 3’b110: y = 4’b0100 ; 3’b111: y = 4’b1000 ; default: y = 4’b0000 ; // disabled module case endcase endmodule
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4 to 2 Binary Encoder
module encoder (y, w) ; input [3:0] w ; // input is one hot output reg [1:0] y ; always @(w) case (w) 3’b1000: y = 2’b11 ; 3’b0100: y = 2’b10 ; 3’b0010: y = 2’b01 ; 3’b0001: y = 2’b00 ; default: y = 2’bx ; // don’t care case endcase endmodule
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Case, Casez, Casex
case treats each value 0, 1, X, and Z literally
4’b01XZ only matches 4’b01XZ
Example: 4’b0110 does not match 4’b01XX in a case
casez treats 0, 1, and X literally
casez treats Z as a don’t care
Example: 4’b0110 matches 4’b01ZZ, but not 4’b01XZ
casex treats 0 and 1 literally
casex treats both X and Z as don’t cares
Example: 4’b0110 matches 4’b01XX and also 4’b01XZ
No match here
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casex example – 4 to 2 Priority Encoder
module priority (y, z , w) ; input [3:0] w ; output reg [1:0] y ; output reg z ; always @(w) begin z = 1'b1 ; // assume valid output casex (w) // casex treats both x and z as don’t cares 4'b1XXX: y = 2'b11 ; 4'b01XX: y = 2'b10 ; 4'b001X: y = 2'b01 ; 4'b0001: y = 2'b00 ; default: begin z = 1'b0 ; // non-valid output y = 2'bX ; // don't care case end endcase end endmodule
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casez example
module casez_example () ;
reg [3:0] opcode ;
reg [1:0] a, b, c, out ;
always @ (opcode or a or b or c) casez(opcode)
4'b1ZZX : out = a ; /* Don't care about bits 2:1, bit 0 match with X */ 4'b01?? : out = b ; // bits 1:0 are don't care 4'b001? : out = c ; // bit 0 is don't care default : out = 2’b0 ;
endcase
endmodule
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Exercise 6
Priority Encoders have vast application in different client-server systems. Decision is made to grant a service based on a predefined priority rule of any specific client.
Design Priority Encoder 8 to 3. LSB – highest priority. Use if-else. Add output indicator for valid data in, using "reduction or" operator.
Design Priority Encoder 8 to 3. MSB – highest priority. Use casex. Add output indicator for valid data in (default case state)