cpe 626 advanced vlsi design lecture 8: power and...

1

CPE 626 Advanced VLSI Design

Lecture 8: Power and Designing for Low Power

Aleksandar Milenkovic

http://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenka/cpe626-04F/

[email protected]

Assistant ProfessorElectrical and Computer Engineering Dept.

University of Alabama in Huntsville

A. Milenkovic 2

Advanced VLSI Design

Why Power Matters

Packaging costsPower supply rail design

Chip and system cooling costsNoise immunity and system reliability

Battery life (in portable systems)Environmental concerns

Office equipment accounted for 5% of total US commercial energy usage in 1993Energy Star compliant systems

A. Milenkovic 3

Advanced VLSI DesignWhy worry about power? –Power Dissipation

P6Pentium ®

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Lead microprocessors power continues to increaseLead microprocessors power continues to increase

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitiveSource: Borkar, De Intel

2

A. Milenkovic 4


Problem Illustration

A. Milenkovic 5

Advanced VLSI DesignWhy worry about power ? –Battery Size/Weight

Expected battery lifetime increase over the next 5 years: 30 to 40%

From From RabaeyRabaey, 1995, 1995

65 70 75 80 85 90 95

0

10

20

30

40

50

Rechargable Lithium

Year

Nickel-Cadmium

Ni-Metal Hydride

Nom

inal

Cap

acity

(W-h

r/lb

)

Battery(40+ lbs)

A. Milenkovic 6

Advanced VLSI DesignWhy worry about power? –Standby Power

§ Drain leakage will increase as V T decreases to maintain noise margins and meet frequency demands, leading to excessive battery draining standby power consumption.

•8KW

•1.7KW

•400W

• 88W •12W

•0%

•10%

•20%

•30%

•40%

•50%

•2000 •2002 •2004 •2006 •2008

•S

tand

by P

ower

Source: Borkar, De Intel

0.250.30.350.40.4Threshold VT (V )

0.60.70.91.21.5Power supply Vdd (V)

20142011200820052002Year

…and phones leaky!

3

A. Milenkovic 7


Power and Energy Figures of Merit

Power consumption in Wattsdetermines battery life in hours

Peak powerdetermines power ground wiring designssets packaging limitsimpacts signal noise margin and reliability analysis

Energy efficiency in Joulesrate at which power is consumed over time

Energy = power * delayJoules = Watts * secondslower energy number means less power to perform a computation at the same frequency

A. Milenkovic 8


Power versus Energy

Watts

time

Power is height of curve

Watts

time

Approach 1

Approach 2

Approach 2

Approach 1

Energy is area under curve

Lower power design could simply be slower

Two approaches require the same energy

A. Milenkovic 9


PDP and EDPPower-delay product (PDP) = Pav * tp= (CLVDD

2)/2PDP is the average energyconsumed per switching event (Watts * sec = Joule)lower power design could simply be a slower design

• allows one to understand tradeoffs better0

5

10

15

0.5 1 1.5 2 2.5

Vdd (V)

En

erg

y-D

ela

y (

no

rm

alized

)

energy-delay

energy

delay

• Energy-delay product (EDP) = PDP * tp = Pav * tp2

• EDP is the average energyconsumed multiplied by the computation time required

• takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption)

4

A. Milenkovic 10


Understanding Tradeoffs

Ene

rgy

1/Delay

a

b

c

d

Which design is the “best” (fastest, coolest, both) ?

bette

r

better

A. Milenkovic 11


Understanding Tradeoffs

Ene

rgy

1/Delay

a

b

c

d

Lower EDP

Which design is the “best” (fastest, coolest, both) ?

bette

r

better

A. Milenkovic 12


CMOS Energy & Power Equations

E = CL VDD2 P0→1 + tsc VDD Ipeak P0→1 + VDD Ileakage

P = CL VDD2 f0→1 + tscVDD Ipeak f0→1 + VDD Ileakage

Dynamic power

Short-circuit power

Leakage power

f0→1 = P0→1 * fclock

5

A. Milenkovic 13


Dynamic Power Consumption

Energy/transition = CL * VDD2 * P0→1

Pdyn = Energy/transition * f = CL * VDD2 * P0→1 * f

Pdyn = CEFF * VDD2 * f where CEFF = P0→1 CL

Not a function of transistor sizes!Data dependent - a function of switching activity!

Vin Vout

CL

Vdd

f0→1

A. Milenkovic 14


Pop Quiz

Consider a 0.25 micron chip, 500 MHz clock, average load cap of 15fF/gate (fanout of 4), 2.5V supply.

Dynamic Power consumption per gate is ??

With 1 million gates (assuming each transitions every clock)

Dynamic Power of entire chip = ??.

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Lowering Dynamic Power

Pdyn = CL VDD2 P0→1 f

Capacitance:Function of fan-out, wire length, transistor sizes

Supply Voltage:Has been dropping with successive generations

Clock frequency:Increasing…

Activity factor:How often, on average, do wires switch?

6

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Short Circuit Power Consumption

Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting.

Vin Vout

CL

Isc

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Short Circuit Currents Determinates

Duration and slope of the input signal, tsc

Ipeak determined by the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc.strong function of the ratio between input and output slopes

• a function of CL

Esc = tsc VDD Ipeak P0→1

Psc = tsc VDD Ipeak f0→1

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Impact of CL on Psc

Vin Vout

CL

Isc ≈ 0

Vin Vout

CL

Isc ≈ Imax

Large capacitive load

Output fall time significantly larger than input rise time.

Small capacitive load

Output fall time substantially smaller than the input rise time.

7

A. Milenkovic 19


Ipeak as a Function of CL

-0.5

0

0.5

1

1.5

2

2.5

0 2 4 6

I pe

ak

(A)

time (sec)

x 10-10

x 10-4

CL = 20 fF

CL = 100 fF

CL = 500 fF

500 psec input slope

Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.

When load capacitance is small, Ipeak is large.

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Psc as a Function of Rise/Fall Times

0

1

2

3

4

5

6

7

8

0 2 4

P n

orm

aliz

ed

tsin/tsout

VDD= 3.3 V

VDD = 2.5 V

VDD = 1.5V

normalized wrt zero input rise-time dissipation

When load capacitance is small (tsin/tsout > 2 for VDD > 2V) the power is dominated by Psc

If VDD < VTn + |VTp| then Psc is eliminated since both devices are never on at the same time.

W/Lp = 1.125 µ m/0.25 µ mW/Ln = 0.375 µ m/0.25 µ mCL = 30 fF

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Leakage (Static) Power Consumption

Sub-threshold current is the dominant factor.

All increase exponentially with temperature!

VDD Ileakage

Vout

Drain junction leakage

Sub-threshold currentGate leakage

8

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Leakage as a Function of VT

0 0.2 0.4 0.6 0.8 1

VGS (V)

ID (

A)

VT=0.4VVT=0.1V

10-2

10-12

10-7

q Continued scaling of supply voltage and the subsequent scaling of threshold voltage will make subthresholdconduction a dominate component of power dissipation.

q An 90mV/decade VTroll -off - so each 255mV increase in VT gives 3 orders of magnitude reduction in leakage (but adversely affects performance)

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TSMC Processes Leakage and VT

80

0.25 V

13,000

920/400

0.08 µ m

24 Å

1.2 V

CL013 HS

52

0.29 V

1,800

860/370

0.11 µ m

29 Å

1.5 V

CL015 HS

42 Å42 Å42 Å42 ÅTox (effective)

43142230FET Perf. (GHz)

0.40 V0.73 V0.63 V0.42 VVTn

3000.151.6020Ioff (leakage) (ρA/µ m)

780/360320/130500/180600/260IDSat(n/p) (µ A/µ m)

0.13 µ m 0.18 µ m 0.16 µ m 0.16 µ m Lgate

2 V1.8 V1.8 V1.8 VVdd

CL018 HS

CL018 ULP

CL018 LP

CL018 G

From MPR, 2000

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Exponential Increase in Leakage Currents

1

10

100

1000

10000

30 40 50 60 70 80 90 100 110

0.250.180.130.1

Temp(C)

I leak

age(

nA/µ

m)

From De,1999

9

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Review: Energy & Power EquationsE = CL VDD

2 P0→1 + tsc VDD Ipeak P0→1 + VDD Ileakage

P = CL VDD2 f0→1 + tscVDD Ipeak f0→1 + VDD Ileakage

Dynamic power(~90% today and

decreasing relatively)

Short-circuit power

(~8% today and decreasing absolutely)

Leakage power(~2% today and

increasing)

f0→1 = P0→1 * fclock

A. Milenkovic 26


Power and Energy Design Space

+ Variable VT

Sleep TransistorsMulti-Vdd

Variable VT

+ Multi-VTLeakage

DFS, DVS(Dynamic

Freq, Voltage Scaling)

Clock Gating

Logic DesignReduced Vdd

SizingMulti-Vdd

Active

Run TimeNon-active ModulesDesign TimeEnergy

Variable Throughput/Latency

Constant Throughput/Latency

A. Milenkovic 27

Advanced VLSI DesignDynamic Power as a Function of Device Size

Device sizing affects dynamic energy consumptiongain is largest for networks with large overall effective fan-outs (F = CL/Cg,1)

The optimal gate sizing factor (f) for dynamic energy is smaller than the one for performance, especially for large F’s

e.g., for F=20, fopt(energy) = 3.53 while fopt(performance) = 4.47

If energy is a concern avoid oversizing beyond the optimal

1 2 3 4 5 6 70

0.5

1

1.5

f

norm

aliz

ed en

ergy

F=1

F=2

F=5

F=10

F=20

From Nikolic, UCB

10

A. Milenkovic 28

Advanced VLSI DesignDynamic Power Consumption is Data Dependent

011

001

010

100

OutBA

2-input NOR Gate

With input signal probabilitiesPA=1 = 1/2PB=1 = 1/2

Static transition probabilityP0→1 = Pout=0 x Pout=1

= P0 x (1-P0)

Switching activity, P0→1, has two componentsA static component – function of the logic topologyA dynamic component – function of the timing behavior ( glitching )

NOR static transition probability= 3/4 x 1/4 = 3/16

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NOR Gate Transition Probabilities

CL

A

B

BA

P0→1 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)

PA

PB

0

1 0 1

Switching activity is a strong function of the input signal statistics

PA and P B are the probabilities that inputs A and B are one

A. Milenkovic 30

Advanced VLSI DesignTransition Probabilities for Some Basic Gates

(1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))OR

(1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)XOR(1 - PAPB) x PAPBANDPAPB x (1 - PAPB)NAND

(1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)NORP0→1 = Pout=0 x Pout=1

B

AZ

X0.5

0.5

For Z: P0→1 =

For X: P0→1 =

11

A. Milenkovic 31

Advanced VLSI DesignTransition Probabilities for Some Basic Gates

(1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))OR

(1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)XOR(1 - PAPB) x PAPBANDPAPB x (1 - PAPB)NAND

(1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)NORP0→1 = Pout=0 x Pout=1

B

AZ

X0.5

0.5

For Z: P0→1 = P0 x P1 = (1-PXPB) PXPB

For X: P0→1 = P0 x P1 = (1-PA) PA= 0.5 x 0.5 = 0.25

= (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16

A. Milenkovic 32


Inter-signal CorrelationsDetermining switching activity is complicated by the fact that signals exhibit correlation in space and time

reconvergent fan- out

B

A

Z

X

P(Z=1) = P(B=1) & P(A=1 | B=1)

Reconvergent fan-out

0.5

0.5

Have to use conditional probabilities

A. Milenkovic 33


Inter-signal Correlations

B

A

Z

X

P(Z=1) = P(B=1) & P(A=1 | B=1)

0.5

0.5

(1-0.5)(1-0.5)x(1-(1-0.5)(1- 0.5)) = 3/16

P(Z=1) = P(B=1) * P(X=1 | B=1)= 0.5 * 1 = 0.5P(Z=0) = 1 – P(B=1)*P(X=1 | B=1) = 0.5P(0->1) = 0.5*0.5 = 0.25

Reconvergent

Determining switching activity is complicated by the fact that signals exhibit correlation in space and time

reconvergent fan- out

Have to use conditional probabilities

12

A. Milenkovic 34


Logic Restructuring

Chain implementation has a lower overall switching activity than the tree implementation for random inputs

Ignores glitching effects

Logic restructuring: changing the topology of a logic network toreduce transitions

AB

CD F

AB

CD Z

FW

X

Y0.5

0.5

(1-0.25)*0.25 = 3/16

0.50.5

0.5

0.50.5

0.5

7/6415/256

3/16

3/16

15/256

AND: P0→1 = P0 x P1 = (1 - PAPB) x PAPB

A. Milenkovic 35


Input Ordering

AB

C

X

F

0.5

0.20.1

B

CA

X

F

0.2

0.10.5

Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5)

A. Milenkovic 36


Input Ordering

Beneficial to postpone the introduction of signals with a high transition rate (signals with signal probability close to 0.5)

AB

C

X

F

0.5

0.20.1

B

CA

X

F

0.2

0.10.5

(1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196

13

A. Milenkovic 37

Advanced VLSI DesignGlitching in Static CMOS Networks

ABC

X

Z

101 000

Unit Delay

AB

X

ZC

Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards)

glitch: node exhibits multiple transitions in a single cycle be fore settling to the correct logic value

A. Milenkovic 38


Glitching in Static CMOS Networks

ABC

X

Z

101 000

Unit Delay

AB

X

ZC

Gates have a nonzero propagation delay resulting in spurious transitions or glitches (dynamic hazards)

glitch: node exhibits multiple transitions in a single cycle be fore settling to the correct logic value

A. Milenkovic 39


Glitching in an RCA

S0S1S2S14S15

Cin

0

1

2

3

0 2 4 6 8 10 12

Time (ps)

S O

utpu

t Vol

tage

(V)

Cin

S0

S1

S2

S3

S4

S5S10

S15

14

A. Milenkovic 40


Balanced Delay Paths to Reduce Glitching

So equalize the lengths of timing paths through logic

F1

F2

F3

00

0

0

12

F1

F2

F3

00

00

1

1

Glitching is due to a mismatch in the path lengths in the logic network; if all input signals of a gate change simultaneously, no glitching occurs

A. Milenkovic 41



+ Variable VT


Variable VT

+ Multi-VTLeakage

DFS, DVS(Dynamic


Clock Gating


SizingMulti-Vdd

Active

Run TimeNon-active ModulesDesign TimeEnergy



A. Milenkovic 42


Dynamic Power as a Function of VDDDecreasing the VDD decreases dynamic energy consumption (quadratically)But, increases gate delay (decreases performance)

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4

VDD (V)

t p(n

orm

aliz

ed)

Determine the critical path(s) at design time and use high VDD for the transistors on those paths for speed. Use a lower VDD on the other gates, especially those that drive large capacitances (as this yields the largest energy benefits).

15

A. Milenkovic 43


Multiple VDD ConsiderationsHow many VDD? – Two is becoming common

Many chips already have two supplies (one for core and one for I/O)

When combining multiple supplies, level converters are required whenever a module at the lower supply drives a gate at the higher supply (step-up)

If a gate supplied with VDDL drives a gate at VDDH, the PMOS never turns off

• The cross-coupled PMOS transistorsdo the level conversion

• The NMOS transistor operate on a reduced supply

Level converters are not needed for a step-down change in voltageOverhead of level converters can be mitigated by doing conversions at register boundaries and embedding the level conversion inside the flipflop (see Figure 11.47)

VDDH

Vin

VoutVDDL

A. Milenkovic 44


Dual-Supply Inside a Logic BlockMinimum energy consumption is achieved if all logic paths are critical (have the same delay)Clustered voltage-scaling

Each path starts with VDDH and switches to VDDL (gray logic gates) when delay slackis availableLevel conversion is done in the flipflops at the end of the paths

A. Milenkovic 45



+ Variable VT


Variable V T

+ Multi-VTLeakage

DFS, DVS(Dynamic


Clock Gating


SizingMulti-Vdd

Active

Run TimeNon- active ModulesDesign TimeEnergy



16

A. Milenkovic 46


Stack EffectLeakage is a function of the circuit topology and the value of the inputs

VT = VT0 + γ(√|-2φF + VSB| - √|-2φF|)where VT0 is the threshold voltage at V SB = 0 ; VSB is the source- bulk

(substrate) voltage; γ is the body-effect coefficient

A B

B

A

Out

VX VSG=VSB=0011

VGS=VBS=0VDD-VT01

VGS=VBS=0010

VGS=VBS= -V XVT ln(1+n)00

ISUBVXBA

Leakage is least when A = B = 0Leakage reduction due to stacked transistors is called the stack effect

A. Milenkovic 47


Short Channel Factors and Stack EffectIn short-channel devices, the subthreshold leakage current depends on VGS,VBS and VDS. The VT of a short-channel device decreases with increasing VDSdue to DIBL (drain-induced barrier loading).

Typical values for DIBL are 20 to 150mV change in VT per voltage change in VD S so the stack effect is even more significant for short-channel devices.VX reduces the drain-source voltage of the top nfet, increasing its V T and lowering its leakage

For our 0.25 micron technology, VX settles to ~100mV in steady state so VBS = -100mV and VDS = VDD -100mV which is 20 times smaller than the leakage of a device with VBS = 0mV and VDS = VDD

A. Milenkovic 48


Leakage as a Function of Design Time VTReducing the VT increasesthe sub-threshold leakage current (exponentially)

90mV reduction in VTincreases leakage by an order of magnitude

But, reducing VT decreasesgate delay (increases performance)

0 0 . 2 0.4 0.6 0.8 1

VGS (V)

ID (

A)

VT=0.4VVT=0.1V

Determine the critical path(s) at design time and use low VT devices on the transistors on those paths for speed. Use a high V T on the other logic for leakage control.

A careful assignment of VT’s can reduce the leakage by as much as 80%

17

A. Milenkovic 49


Dual-Thresholds Inside a Logic Block

Minimum energy consumption is achieved if all logic paths are critical (have the same delay)Use lower threshold on timing-critical paths

Assignment can be done on a per gate or transistor basis; no clustering of the logic is neededNo level converters are needed

A. Milenkovic 50


Variable VT (ABB) at Run Time

VT = VT0 + γ(√ |-2φF + VSB| - √ |-2φF |)

0.4

0.450.5

0.55

0.60.650.7

0.750.8

0.850.9

-2.5 - 2 -1.5 - 1 -0.5 0VSB (V)

V T(V

)

• A negative bias on VSBcauses VT to increase

• Adjusting the substrate bias at run time is called adaptive body-biasing(ABB)

• Requires a dual well fabprocess

• For an n-channel device, the substrate is normally tied to ground (VSB = 0)

cpe 626 advanced vlsi design lecture 8: power and...

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