cplds

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EET 3350 Digital Systems Design

Textbook: John Wakerly Chapter 9: 9-5

CPLDs

CPLDs• Overview of FPLDs

– History

– Tradeoffs

• CPLDs– General Description

– Basic Architecture

• Specific Vendor Devices– Xilinx

– Altera

• Xilinx XC9500 Series• CPLD Problems

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Hierarchy of Logic Implementations

AcronymsSPLD = Simple Programmable Logic Device PAL = Programmable Array LogicCPLD = Complex PLDFPGA = Field Programmable Gate ArrayASIC = Application Specific IC

Common ResourcesConfigurable Logic Blocks (CLB)

– Memory Look-Up Table (LUT)– AND-OR planes– Simple gates

Input / Output Blocks (IOB)– Bidirectional, latches, inverters, pullup/pulldowns

Interconnect or Routing– Local, internal feedback, and global

Logic

StandardLogic

ASIC

ProgrammableLogic Devices

(FPLDs)

GateArrays

Cell-BasedICs

Full CustomICs

CPLDsSPLDs(e.g., PALs) FPGAs

today’s focustoday’s focus

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Field-Programmable Logic Devices• Component function is defined by user under program

control• Logic Cells are interconnected by programming• Advantages:

– Flexible design that changes by reprogramming, ease of design changes

– Reduce prototype-product time– Large scale integration (over

100,000 gates)– Reliability increased, low financial

risk– Smaller device, low start-up cost

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FPLD Capacities

• “Equivalent gates” refers loosely to the number of two-input NAND gates.

• The chart serves as a guide for selecting a device for an application according to the logic capacity needed.

• Each type of FPLD is inherently better suited for some applications than for others.

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Digital Technology Tradeoffs

S

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Which Implementation Technology?• Economic versus technical factors

– The next few slides off a comparison of economic and technical factors associated with these technologies

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SPLDSSI/MSI

semicustom semicustom technologiestechnologies

standardstandardcomponentscomponents

CPLDFPGA

GateArray

Std.Cell

FullCustom

Comparison of Implementations• The table below offers a comparison of the major

implementation technologies over four key factors

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SSI/MSI SPLD FPGA Gate ArrayStandard

CellFull

Custom

Gates/Component 5 - 100 50 - 5K 100 - 10K 500 - 100K 10K - 500K 100K - 10M

Cost/Gate High

Low

NRE Cost ($) - 1-2K 2-10K 5-50K 10-100K 50K-5M

Development time (weeks)

- 1-2 1-2 2-20 5-50 20-200

Comparison of Implementations

Circuit Cost As A Function Of Volume

Discrete

Full custom

Volume

Cost

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Evolution of Implementations• CPLDs and FPGAs continue to evolve in parallel

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1960

1970

1980

1990

2000

Today

SSI

MSI

LSI

VLSI

‘standard components’

‘semicustom components’

Gate Array

Standard CellsSimple PLD

CPLD FPGA

parallel development

Three FPLD Types• Simple Programmable Logic Device (SPLD)

– LSI device

– Less than 1000 logic gates

• Complex Programmable Logic Device (CPLD)– VLSI device

– Higher logic capacity than SPLDs

• Field Programmable Gate Array (FPGA)– VLSI device

– Higher logic capacity than CPLDs

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(FPLDs)


Three FPLD Types• Simple Programmable Logic Device (SPLD)

– PLA or PAL

– Fixed internal routing, deterministic propagation delays

• Complex Programmable Logic Device (CPLD)– Multiple SPLDs onto a single chip

– Programmable interconnect

• Field Programmable Gate Array (FPGA)– An array of logic blocks

– Large number of gates, user selectable interconnection, delays depending on design and routing

– A high ratio of flip-flops to logic resources

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(FPLDs)


SPLDs

• SPLDs = Simple PLDs• Popular SPLD Architecture Types

– Programmable Logic Array, PLA– Programmable Array Logic, PAL (Vantis)– General Array Logic, GAL (Lattice)– others

• Architecture Differences– AND versus OR implementation– Programmability (e.g., EE)– Fundamental logic block

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(FPLDs)


SPLDs• We have already taken a close

look at SPLDs• A PLA-like SPLD is illustrated

at left– PAL and GAL devices offered

a somewhat better solution

• SPLDs are good alternative to using SSI and MSI devices– Especially if re-programmable

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Logic Functions

Product Terms

Sums


(FPLDs)


SPLDs• Conventional programmable logic

– PALs, PLAs, GALs– standard parts like GAL22V10 and PAL16R4 are available from

multiple vendors

• Includes programmable logic cells to a limited degree (programming options in I/O cells, may have fixed AND/OR gates for logic), limited routing network

• Lowest density of all programmable devices, however, can offer very high performance

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(FPLDs)


• SPLDs have nearly replaced TTL logic which was the dominate approach to logic implementation

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How to Expand SPLD Architecture?• Increase number of inputs and outputs in a

conventional PLD?– e.g., 16V8 → 20V8 → 22V10

– Why not → 32V16 → 128V64 ?

• Problems: – n times the number of inputs and outputs requires n2 as

much chip area – too costly

– logic gets slower as number of inputs to AND array increases


(FPLDs)


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How to Expand SPLD Architecture?• Solution:

– Multiple SPLDs with a relatively small programmable interconnect

– Less general than a single large PLD

– Can use software “fitter” to partition into smaller PLD blocks


(FPLDs)


CPLD Architecture

CPLDs• PALs and GALs are available only in small sizes

– equivalent to a few hundred logic gates

• For bigger logic circuits, complex PLDs or CPLDs can be used.

• CPLDs contain the equivalent of several PALs/GALs – linked by programmable interconnections– all in one integrated circuit (IC)

• CPLDs can replace thousands, or even hundreds of thousands, of individual logic gates – increased integration density

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(FPLDs)


Complex PLDs• Some CPLDs are programmed using a PAL

programmer, but this method becomes inconvenient for devices with hundreds of pins.

• A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal computer.

• The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function.

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(FPLDs)


Complex PLDs• Each manufacturer has a proprietary name for its

CPLD programming system • For example, Lattice calls it "in-system programming" • However, these proprietary systems are beginning to

give way to a standard from the Joint Test Action Group (JTAG)

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(FPLDs)


• Xilinx, for example:• Xilinx CPLD devices that are cheaper and have fewer

gates than Xilinx FPGAs• Meant for interfacing rather than heavy computation• Built-in flash memory

– Compare to FPGA which needs external configuration memory

• Xess board has XC9572XL part– Approximately $2-$7 in quantities of one – vs. ~$15-20 for the Spartan2 FPGA on the board– Larger quantities much lower– 1600 gates, 72 registers

Complex PLDs versus FPGAs

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(FPLDs)


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CPLD Architecture• Simplified CPLD

architecture• Small number of largish

PLDs (e.g., “36V18”) on a single chip

• Programmable interconnect between PLDs

• Large number of I/O blocks

• Large number of pins

CPLD Architecture• Generalized

architecture for a complex PLD

• Programmable Interconnect Array – Capable of

connecting any LAB input or output to any other LAB

• Logic Array Blocks – Complex SPLD-like

structure

• Input/Output Blocks

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(FPLDs)


CPLD Architecture• Each of the SPLD-like blocks in

a CPLD can be programmed as with a PAL or GAL

• Many SPLD-like blocks (e.g., LABs) are included in one CPLD

• LABs can be interconnected to build larger logic systems

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CPLD Architecture

Feedback Outputs


(FPLDs)


CPLDs• Composition of Complex PLDs

– typically composed of 2-64 SPLDs

– interconnected using sophisticated logic

– includes macrocells (more about these later)

– includes input/output blocks

• Economical for designing large systems• Fast – switching speed

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(FPLDs)


CPLDs

• Complex PLD's have arrays of PLD's on one chip, with an interconnection matrix connecting them.

• Timing performance can be more predictable than FPGAs because of simpler interconnect structure.

• Density is normally less than most FPGAs (although high end CPLDs will have about the same density as low-end FPGAs).


(FPLDs)


• Performance of CPLDs is usually better than FPGAs, but depends on vendor, number of cells in CPLD, and compared FPGA.

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