cpu: software architectureece.uprm.edu/~ahchinaei/courses/2014jun/inel4206/...instruction is cpu...

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CPU: SOFTWARE ARCHITECTURE

INSTRUCTION SET (PART 1) General Introduction

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General Introduction (1/5): On Instructions

• Instruction operate with data or with the flow of the program

• The following information is absolutely needed to define an instruction:

– OpCode: What is the operation to be done

– Operands: What operands are involved

– Addressing mode: Where is data to be found

• Additional information may include size of operands or other modifiers.

General Introduction (2/5): On instructions

• The number and type of instructions, i.e., what they do, depend on the MCU or MPU family and model.

• Several types of instructions are found in almost any MCU or MPU

– Syntax may be different

• An instruction set is not necessarily independent – It may happen that the operation of one instruction may

be realized with other with proper operands.

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General Introduction (3/5): On operands

• The maximum number of operands of instructions depends on MCU or MPU model

– Most small microcontrollers work with two operands.

– Some specific families work with three operands

• In many instances, one or more operands may be

implicit

• Two operands (data) are considered: destination and source

General Introduction (4/5): Destination

• The result of an instruction, except for some cases, is stored either as a

– CPU register content

– memory cell (or cells, depending on data size) contents

– contents of register of an IO device.

• The place where the result is stored is called destination (dest)

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General Introduction (5/5): Source

• The source is the other datum involved in the operation

• It may be a

– Constant data or a

– CPU Register, memory cell(s) or IO register contents

• Abusing of language, source is referred to as – The source itself alone

– An expression that involves the source and destination (as in source + destination)

– An expression that includes the source and other information

Register Transfer Notation (RTN)

• The register transfer notation (RTN) is a symbolic, MCU independent notation to indicate CPU transactions, operations in programs, etc. Arrow points to destination:

– dest src

• In an expression such as dest dest + source, the destination data in “dest + source” is the one previous to the transaction, and “dest” on the left is the data after transaction

– PC NewAddress is mentioned as “Jump to NewAddress” or “ GOTO Newaddress”

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Hybrid RTN and convention (1/3)

• Convention: When RTN is too complicated, a simple sentence is preferred

– Jump to address, instead a PC address

• Operands are denoted as follows:

• For a CPU register, the register name is given . – In MSP430: R4, R5, etc.

– INTEL 8086: AX, AH, BL, etc.

– In general, simply register Reg X, or RX

• A constant data by the number or #number

– Example R6 34h, or R6 #34h means R6 is stored with number 34h

Hybrid RTN and convention (2/3)

• When data is to be stored in memory, or IO device register, the address at memory is provided in parenthesis or preceded by &.

– (2030h) denotes data at address 2030h

– (Hello) denotes data at address defined by a label named Hello .

– (R5) denotes data at address given by contents of register R5

– (R5 + X) denotes data at address given by the result of adding X to the contents of register

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RTN Conventions (3/3)

• Data to register pertaining an I/O subsystem device: same notation as in memory, except that address belong to the Device register, and it must be indicated. Usually, use the name of the register

– (P1OUT) denotes the address of Output Register of Port 1

– (WDTCTL) denotes the address of the Watchdog Timer Control Register

• Addresses are also denoted with & (loan from C)

– (2030h) same as &2030h

– (P1OUT) same as &P1OUT

Machine Language

• Machine language instruction is the set of n-bit words that define an instruction

• If there are more than one word, the first in the set is called instruction word

• The instruction word contains:

– OpCode: field of bits that define the operation

– Destination and Source bit fields

– Addressing Mode field: That define how and where to read data, destination and source fields.

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Example: MSP430 instructions

From machine to assembly (1/2)

• Assembly language is make programming “in machine language” much easier and direct

• Each machine language instruction is associated to one and only one assembly language instruction

• Converting an assembly language to its machine language version is “to assemble” .

– The software tools to assemble are • assembler : works all instructions before assembling

• Interpreter or line interpreter : works with an isolated instruction

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From machine to assembly (2/2)

• An assembly language instruction consists of – A mnemonics: Name given to the opcode,

– Operands written in a specific syntax for addressing mode

• The specific syntax for mnemonics, operands and order in the instruction is CPU family dependent.

• The three examples below all express an instruction of the form dest (0204h), dest is a CPU register and the data size is a byte – MSP430 mov.b 0204h, R6 (CPU register is R6)

– Intel 8086 mov AH, [0204h] (CPU register is AH)

– M68CH11 LDAA $0204 (CPU register is accumulator A)

INSTRUCTION SET (PART 2) Instruction Types

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Instruction Types (1/2)

• Data transfer instructions (dest src)

– For reading and writing to and from memory and IO registers, Storing with data, copy from registers.

– These instructions in general do not affect flags

• Arithmetic and logic operations

– Of the type dest dest * src (* means an operation), with flags being or not affected

– Of the type (dest*src), affecting only flags

Instruction Types (2/2)

• Register operations: manipulates bit order

– Shift, roll and rotation

• Flow program operations: On execution, they modify the content of the PC register

– Jump instructions (PC New Address)

– Subroutine instructions:

• Call and Return

– Interrupt instructions:

• Return from Interrupt.

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Transfer operations (1/2)

• Move instructions: copy source data onto destination data (dest src)

– MSP430 mnemonics mov, mov.w, mov.b

– Also called “load”, “store” instructions

• Input and output transfer instructions

– For those MCU with IO mapped IO systems

– Input*: dest (Input Port)

– Output*: (Output port) Source

Common Data Transfer Instructions

• Stack transfer operations, managed by SP register (explained later)

– Push: (TOS) src

– Pop or Pull: dest (TOS)

– TOS means Top Of Stack

• Swap: dest source (exchange of contents; both operands are erased and reloaded)

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Arithmetic instructions (1/2) Addition and Subtraction

• Addition Operations:

– Addition: dest dest + src

– Addition with carry: dest dest + src + CFlag

• Subtraction Operations: Usually with two’s complement addition

– Subtraction: dest dest – src

– Subtraction with borrow : • dest dest – src – BF for dual Carry/Borrow cases

• dest dest + NOT(src) + CF, when CF=0 denotes borrow

– Compare operation: dest – src; only flags affected

Arithmetic instructions (2/2) Multiplication and division

• Not all microcontrollers’ ALU’s implement these operations.

• Operands and destination sizes are of outmost importance.

• When not supported, these operations are done by software

• Special cases are dedicated peripherals.

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Logic Instructions General introduction

• Bitwise and not bitwise

– Most microcontrollers support only bitwise logic operations

• Non bitwise logic operation principles:

– Yield a boolean result (usually in a flag)

– In source, “1” means operand is not zero; “0” means operand is zero

– Used mainly in high performance systems or as part of “high level” instructions

Bitwise Logic Operations (1)

• dest dest*source means dest(j)dest(j)*source(j)

• Bitwise operations permit individual bit manipulations

• The source is usually called “mask”

– “1”s in mask indicate which bits are to be affected

• AND: dest dest .AND. src

• OR: dest dest .OR. src

• XOR: dest dest .XOR. Src

• NOT: dest NOT(dest)

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Bit manipulation : CLEAR

0.AND.X=0;

1.AND.X=X To clear specific bits in destination, the binary expression

of the source

has 0 at the bit positions to clear and 1 elsewhere

Bit manipulation : SET

0.OR.X=X;

1.OR.X=1

To set specific bits in destination, the binary expression

of the source

has 1 at the bit positions to set and 0 elsewhere

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Bit manipulation : TOGGLE

0.XOR.X=X;

1.XOR.X=X’

To toggle specific bits in destination, the binary

expression of the source

has 1 at the bit positions to invert and 0 elsewhere

Register operations: Shifts, rolls and rotates

• Shift (or roll) right logically:

– 0 dest(N-1)dest(N-2) …. dest(1) dest(0) CF

• Shift left:

– C dest(N-1) dest(N-2) …. dest(1) dest(0) 0

• Shift (or roll) right arithmetically:

– Dest(N-1) dest(N-1)dest(N-2) …. dest(1) dest(0) CF

• Rotate right through:

– CFold dest(N-1)dest(N-2) …. dest(1) dest(0) CF

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Shift and rotate examples

Carry Old Carry

X 1 0 1 1 0 1 0 1 Original

X 0 1 0 1 1 0 1 0 1 Shift right logically

X 1 1 0 1 1 0 1 0 1 Shift right arithmetically

X 0 1 1 0 1 0 1 0 1 Shift left

A 0 1 1 0 1 0 1 A 1 Shift left with carry

1 0 1 1 0 1 0 1 Original

A A 1 0 1 1 0 1 0 1 rotate right through carry

Program Flow Instructions (1) Jumps or Branch --

• ACTION: PC NewAddress

• Unconditional jumps: (jmp)

– GOTO!!!!!!!!!!! Ohhhhhhh!!!!!!

• Conditional jumps: test a flag condition

– Basic tools for decisions

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Conditional jumps (simple flags)

Conditional jump Condition Jump if zero (jz) Z=1 Jump if not zero (jnz) Z=0 Jump if carry (jc) C=1 Jump if not carry (jnc) C=0 Jump if negative (jn) N=1 Jump if not negative (jp) N=0 Jump if overflow (jv) V=1 Jump if not overflow (jnv) V=0

Other names and otherConditional jumps

Conditional jump Condition Note

Jump if equal (je) (= Jump if zero) Z=1 Jump if not equal (jne) (= Jump if not zero) Z=0

Jump if larger or equal (= Jump if carry) C=1 Unsigned numbers

Jump if lower (= Jump if not carry) C=0 Unsigned numbers

Jump if greater or equal (jge) N=V Signed numbers

Jump if less N~=V Signed numbers

Other combinations available …..

To be used after a compare operation A-B, for numeric decisions)

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Remarks on jumps

• A jump is also called a “branch instruction”

• Unconditional jumps are present in almost any CPU

• Not all conditional jumps are necessarily present in the CPU architecture

• The use of jumps is indispensable to devise non sequencial programs.

Subroutines and Procedures

• Subroutines (also called functions or procedures) are pieces of executable code written and stored apart from the main code

• They are to be executed when invoked from main code or other subroutine, but flow must return to original “normal” flow

• The Address of first instruction is called Entry Address

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Subroutine Instructions:

• Call instruction: Saves the present value of the PC register and then loads the PC with the entry address of the subroutine

– a) (TOS) PC

– PC Sub. Entry Address

• Return instruction: Retrieves the address following the call in the main code [PC (TOS)]

• Important note: Subroutine programming must ensure that return is well done

Subroutine process

1. Just before CALL execution

PC points to next memory

location after CALL.

2. Upon execution, the content

of PC is pushed onto stack,

and PC loaded with address

of subroutine entry line

3. Subroutine is executed until

instruction RET (return) is

found.

4. Execution of RET pops PC,

restoring the address of the

instruction just after CALL

--- This happens every time

CALL is executed

Important remark: Subroutine must be

designed so that when RET is encountered

SP is pointing to the right location

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Call and Return

CALL SUB

Next Instr.

Inst Bla bla

Entry line

- - - - - - - -

Return --- -

E400

E402

E420

F248

F24A

Before Fetch of call:

PC = F248

After decode of call, and

before execute phase:

PC = F24A

First step of execution:

PC = F24A, (TOS) = F24A

Second Step of Execution

PC = E400 (TOS) = F24A

After return:

PC = F24A

Entry

Addr

Example 1: Delay loop

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Example 2: Repeat process N times

Counter N

Label: Do process

counter counter -1

Jump if not zero to Label

Examples of composed Conditional Structures using basic structure

• Single Flag(s) condition

Instruction affecting flags

FLAG? Yes No

• Multiple Flags:

FLAG_A AND FLAG_B


FLAG_A?

Yes

No

FLAG_B? Yes No

• Multiple Flags:

FLAG_A OR FLAG_B


FLAG_A? Yes

No

FLAG_B? Yes No

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STACK AND STACK POINTER

Stack Definition and Characteristics • Stack is a specialized memory segment which works in LIFO

(Last In-First Out) mode. Managed by the Stack Pointer Register (SP) – Hardwired stack: physically defined, cannot change

– Software defined: First address in stack defined by initialization of SP (by user or by compiler)

• Stack Operations: – PUSH: storing a new data at the next available location

– POP or PULL: retrieving last data available from the sequence (to be stored in some destination)

– Important Note: A retrieved data is not deleted, but cannot be retrieved again with a stack operation

• Top of Stack (TOS): memory address used in the stack operation (different for push or pop)

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Basics of stack operation

Empty at start

(Only garbagge)

Pu

sh

TO

S

X x x x x x x x x x


PUSH

(garbage not shown)

Pu

sh

TO

S

Po

p T

OS

D0

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PUSH

Pu

sh

TO

S

Po

p T

OS

D0 D1


PUSH

Pu

sh

TO

S

Po

p T

OS

D0 D1 D2

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POP

Pu

sh

TO

S

Po

p T

OS

D0 D1 D2


PUSH

Pu

sh

TO

S

Po

p T

OS

D0 D1 D3

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POP

Pu

sh

TO

S

Po

p T

OS

D0 D1 D3


POP

Pu

sh

TO

S

Po

p T

OS

D0 D1 D3

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Software Defined Stack Grows Downwards

xxxx

xxxx-N

xxxx-2N

xxxx-3N

xxxx-4N

Push TOS xxxx

xxxx-N

xxxx-2N

xxxx-3N

xxxx-4N

D0

Push TOS

PopTOS

Empty After a push

xxxx

xxxx-N

xxxx-2N

xxxx-3N

xxxx-4N

D0

Push TOS

PopTOS D1

After a push

xxxx

xxxx-N

xxxx-2N

xxxx-3N

xxxx-4N

D0

Push TOS

PopTOS

D1

D2

After a push

xxxx

xxxx-N

xxxx-2N

xxxx-3N

xxxx-4N

D0

Push TOS

PopTOS D1

D2

After a pop

xxxx

xxxx-N

xxxx-2N

xxxx-3N

xxxx-4N

D0

Push TOS

PopTOS

D1

D3

After a push

Stack and Stack Pointer

• The Stack Pointer contents is an address associated to the stack operation

– The contents of SP is sometimes called Top-of-Stack

• Since contents is unique, and two addresses are associated to the TOS, there are 2 possibilities:

– SP contains the PUSH-TOS (Example: Freescale)

– SP contains the POP TOS (Example: MSP430)

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SP points to PUSH TOS

• To do a PUSH:

– 1. Store (SP) Data

– 2. Update SP SP - N

• To do a POP:

– 1. Update SPSP+N

– 2. Retrieve Dest(SP)

• These steps are done automatically by CPU.

D0

Push TOS

PopTOS

D1

D2

(SP)

(SP+N)

SP points to POP TOS

• To do a PUSH:

– 1. Update SP SP -N

– 2. Store (SP) Data

• To do a POP:

– 1. Retrieve Dest(SP)

– 2. Update SPSP+N

• These steps are done automatically by CPU.

D0

Push TOS

PopTOS

D1

D2

(SP-N)

(SP)

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Stack Pointer in MSP430

• SP is register R1

– It is always even, since the least significant bit is hardwired to 0

– There is an error if user tries to load an odd number onto SP

• It points to the ‘last pushed item’ (first to pop)

• N=2: That is, update is always +- 2.

– If pushing a byte, the msb of the word becomes 00h

Important Remarks

• Without any reference to the actual meaning of SP contents, and the fact that the address for pushing and pulling are different, the following conventions are generally adopted:

– Contents of SP is called TOP-OF-STACK (TOS)

– PUSH operation is denoted as (TOS) source

– POP or PULL operation is denoted as dest (TOS)

• You should be aware of differences!!

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ADDRESSING MODES

General introduction(1/2)

• Addressing mode is the way to denote where to find (or store) the datum used in an operation

• A datum or result to store can be referred to

– explicitely (immediate mode)

– as contents of a CPU register (register mode)

– By the address of the memory or IO register(s) where it is to be found

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General introduction (2/2)

• Actual addressing modes and mode names in a family or model should be consulted in data sheet or user guide

– Cases presented here are common, names may differ

• Syntax depends on family system – Note: we use msp430 syntax for examples.

• Specific restrictions for use is also family dependent

• Orthogonal system: it accepts all registers and addressing modes in both source and destination

– Except immediate mode, not valid for destination

Immediate and register modes (1/2)

• Immediate mode is when datum is explicitly given

– It is valid only for source

– Syntax in MSP430 #Datum (#N)

• Register mode is when datum is the contents of a CPU register

– Syntax in MSP430 (and almost all MCU): Register Name Rn.

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Immediate and Register Modes (2/2) Examples

• MSP430 examples:

– Explanation: mov src, dest stands for destsrc

• Examples: (Register contents in hex notation)

– If R5=245A, then after execution of instruction mov #0x2AC, R5 R5 = 02AC

– If R5=245A, then after execution of instruction mov #-20285, R5 R5 = B0C3

– If R5 = 245A and R6 = ABCD, then after execution of instruction mov R5, R6 R5 = 245A, R6=245A

• Instruction does not modify source

– mov R5,#435 is not valid!

Memory related addressing modes:

• Direct mode (or absolute mode): address is explicitely given

– MSP430 notation: Address_value (X)

• Register indirect (or indirect): address is given as contents of a CPU register

– MSP430 notation: @Rn

• Indexed ( register relative; or base indexed): Address is given as the addition of a number X and contents of a CPU register

– MSP430 notation: X(Rn)

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Examples (1/2)

• Word size data address and content before each example (all hex notation): [0308]= 23FE, [030A]=012D

• Direct mode:

– mov 0308h, R6 R6 = 23FE

– If R6 = 9ABC , then mov R6, 0308h [0308] = 9ABC

• Register indirect:

– If R5 = 0308, then • mov @R5, R6 R6=23FE, R5=0308

• mov @R5, 0x030A [030A]= 23FE

Examples (2/2)

• Word size data address and content before each example (all hex notation): [0308]= 23FE, [030A]=012D

• Indexed Mode:

– If R5 = 0308, and R6= 3FEC before each instruction then • mov 2(R5), R6 R6=012D, R5=0308

• mov 0(R5), 0x030A [030A]= 23FE

• mov R6, 2(R5) [030A] = 3FEC, R5= 0308, R6 = 3FEC

• mov # 128, 0(R5) [0308] = 8000

– Comments: Indexed mode is very handy for arrays.

cpu: software architectureece.uprm.edu/~ahchinaei/courses/2014jun/inel4206/...instruction is cpu...

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