cpu3-3ba57162ab

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Alcatel OmniPCX 4400

SECTION xx

CPU3 (step2-step3) board

Ed.02

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Section xx - CPU3 (step2-step3) board


SUMMARY

CPU3 board (step2 - step3)Operation ....................................................................................................... xx. 3

1. Presentation.......................................................................................... xx. 32. Environment.......................................................................................... xx. 33. General operating principles ............................................................... xx. 44. Functional blocks .................................................................................. xx. 5

Configuration.................................................................................................. xx.111. CPU3 step 2 board ................................................................................ xx.112. CPU3 step 3 board ................................................................................ xx.133. Meaning of the LED............................................................................... xx.15

Connection...................................................................................................... xx.171. Connection ............................................................................................ xx.172. Output pins ........................................................................................... xx.18

OBCA boardOperation ....................................................................................................... xx.23

1. Presentation.......................................................................................... xx.232. Environment.......................................................................................... xx.243. General principle of operation............................................................. xx.254. Functional blocks .................................................................................. xx.26

VMU-OBCA boardOperation ....................................................................................................... xx.29

1. Presentation.......................................................................................... xx.292. Environment.......................................................................................... xx.303. General principe of operation.............................................................. xx.314. Functional blocks .................................................................................. xx.32

Ed.02 Ref.3BA19919ENAA xx.1

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xx.2 Ref.3BA19919ENAA Ed.02

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Section xx - CPU3 (step2-step3) board CPU3 board (step2 - step3)Operation

44A03222123A100AAEN

CPU3 board (step2 - step3)OperationEdition: 02

1. Presentation

The CPU3 board (step 2 or step 3) is the heart of the system. It generates the clock signals and pro-cesses the system applications (atelephone, telematics, messaging applications, etc.). It is used todownload the flash EPROMs of each of the systems boards. It permits connection of an external musicon-hold and a voice service and provides four V24 channels, an SCSI bus (step 2 only), an on-boardbackplane Ethernet access and a direct 10base T access.

A second CPU3 board (optional) (same step) can be installed to back up the first board. A backplanesignal (depending on the position) specifies, on system power up, the master or slave function of eachCPU3 (step 2 or 3) board. Switch-over takes place in the event of faulty clock signals.

The following daughter boards (optionnal) can be installed on the CPU3 board (step 2 or 3):

- OBCA: 64kbit/s access (seemodule VMU-OBCA board - Operation ),

- VMU-OBCA: voice mail + 64kbit/s access (seemodule VMU-OBCA board - Operation ).

The CPU3 board (step 2 or 3) configuration is described in module CPU3 board (step2 - step3) -Configuration .

The CPU3 board (step 2 or 3) connection is described in module CPU3 board (step2 - step3) - Connec-tion .

2. Environment

2.1. Position in the rack

The CPU3 (step 2 or 3) is connected to the other system boards via the I/O controller which integratesa C1 to establish the type 1 links wityh the 27 other system boards.

The CPU3 board (step 2 or 3) can be connected to the following, on the front side :

- the IO2 board, via ATB2 connection interface board,

- the IO2N board, via ISAB2 connection interface board.

The CPU3 (step 2 or 3) has a predefined position according to the type of ACT.


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CPU3 board (step2 - step3) Section xx - CPU3 (step2-step3) boardOperation

2.2. Inputs/outputs

Figure 1 : CPU3 (step2-step3) board inputs/outputs diagram

DEM1 to 5-48V0V48

TYPE 1 links T1 to T28

Master/slave

Rectifier alarm

16MHz system clocks

256kHz convertersynchronisation

512kHz externalreference clock

AlarmNetwork line forwarding

4 V24 links

8kHz frame synchronisation

External music on holdVoice service

TYPE 1 linksR1 to R28

On/OffPower supply

Systemclocks

I/O controller

10 base T port, AUI

CPU

Ethernet interface

B bus

Embedded Ethernet link

Remote resetSCSI bus (step 2)Floppy

3. General operating principles

In case of failure of the main (master) CPU3 (Step 2 or 3) board, a backup (slave) CPU3 (same step)board will take over. The backplane master/slave signal specifies to each CPU (according to its posi-tion) the master (-48V) or slave (0V48) function on initialisation. During normal operation, the masterCPU considers the slave CPU as an interface board. The CPUs communicate via the 256 kbit/s chan-nel of the type 1 link. The CPU in stand-by monitors the backplane generated clocks of the active CPU.In case of master CPU reset (resulting in loss of clocks) or clock failure, switch over will take place andthe slave CPU will become master CPU.


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4. Functional blocks

4.1. LIST

The CPU3 (step 2 or 3) is made up of the following blocks:

- control unit,

- I/O controller integrating clock and tone generation,

- Ethernet, SCSI (step 2 only) and V24 interfaces,

- power supply block.


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Figure 2 : CPU3 (step2 or step3) board functional summary diagram

DRAM

2xV24interfaces

+5V+12V

-48V

8 kHz

T1/ R1to

T28/R28

Music onhold

ASICVIVALDI

C 1

Voice mailinterface

CM2 converter

Processor

512 kHz

16 MHZ

PCM E

PCM R

Externalmusic

on hold

2 asynchronousV24 (C/D)

HB, SYNC

256 kHz

ProcessorLED

ETHERNETinterface

802.3 ports(10 base T)

Bus interface

SharedRAM

256 kHz

80386EX

Harddisk

NAR6

Bus interface

EPROM flash

Protection key

BackplaneFrontpanel

Disk drivecontroller

IO2

B bu

s

On/Off

SharedFLASH

JTAG JTAG

Bus interface

SCSI SCSI bus

Disk drive

EmbeddedEthernet link

2 asynchronousV24 (A/B)

Daughterboard

Bus interface

ISA

Ethernet LED

EPROM

(step 2 only)

IO2N

B bu

s

ATB2

ISAB

2


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4.2. Blocks description

4.2.1. Control unit

This is a PC-AT platform organized around an 80386 EX-33 microprocessor. It comprises the followingelements:

- microprocessor,

- dynamic memory,

- ASIC NAR6.

Microprocessor

The microprocessor is a 32-bit 80386 EX-33 de 32bits integrating a parallel bus controller, clockcontroller, watchdog, serial asynchronous I/O unit (2 V24, COM A and COM B).

DRAM

The DRAM has a maximum capacity of 64 MB (memory modules).

ASIC NAR6

The NAR6 works directly on the picroprocessor bus. It supports the following system functions:

- DRAM controller,

- bus interface management (ISA, IDE, I/O),

- real time clock (calendar),

- JTAG functionality.

4.2.2. I/O controller

The I/O controller is made up of the following parts:

- C1 circuit,

- processor,

- clock and tone module,

- shared memory,

- voice service interface,

- external music interface.

C1 circuit

This component handles the I/Os for the CPU3 (Step 2 or 3) board. It is connected to the other systemboards via type 1 backplane links and carries out the following functions:

- distribution of music on hold and multi-frequencies to the interface boards,

- extraction of the four signalling TSs from each type 1 link and transmission to the control unit,


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- exchange on type 1 links of voice channels with the other couplers,

- injection of the signalling from the CPU3 (Step 2 or 3) on the four type 1 link TSs destined foran interface board.

Processor

This 80C188 type processor controls the C1 circuit, FLASH memory programming and activation of thecommon part processor LED. In case of system failure (PSAL rectifier alarm or watch dog), it generatestwo signals:

- the network line forwarding signal controls the forwarding relays installed on the MDF. Thisforwards the network lines directly to the back-up telephone stations,

- the alarm signal informs the exterior that the system is no longer operational.

Clocks and tones module

Most peripherals are integrated in a VIVALDI ASIC. This carries out:

- clock generator.

Clock signals are generated for the whole system:

16 MHz system clocks (16M1 and 16M2),

8 KHz frame sync (8K1 and 8K2),

converter synchronisation (256 KHz).

Clocks 16M2 and 8K2 only service the lower shelf in the 28 position backplane.

This module can be synchronised by a 512 KHz reference clock signal from the public network viaa T2, PCM or T0 interface board or a DECT board.

The clocks sent on the system are generated from the external clock or else by a local oscillator(16.384 MHz not slaved). VIVALDI ensures the selection.

- tone generator.

The frequencies are generated from samples stored in a FLASH EPROM, which is programmed viathe VIVALDI component. The tones and multi-frequencies used by the system interface boards areMFQ23 type (16 frequencies), ringing frequency (50 Hz), TL frequency (50 Hz), modem frequency(2100 Hz) as well as the tones specific to each country (Dial tone, send tone, etc.).

- watchdog function.

Voice mail interface (optional)

This module is an optional daughter board (MICROPAC interface). It interfaces with the Alcatel 4630voice messaging system.

Shared memory

This 256 kB memory can be accessed for read/write by the 80C188 processor and 80386 EX platformvia the ISA bus. Memory access is controlled by an arbitrator.

Music on hold interface


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This module interfaces with an external music on hold . This music is then distributed to the systemboards via type 1 links.

4.2.3. Interfaces

Ethernet interface

This interface is used for connection to an Ethernet network (connection to a server, etc.) via a connec-tion box. The accesses available are:

- 802.3 link implemented in the circuit (on-board Ethernet link) which distributes to the ECX1 board,

- 10 Base T AUI type interface. When this interface is in service, the 10 Base T LED on the frontpanel is on.

SCSI controller (step 2 only)

This interfaces with the ISA bus and offers an SCSI port for data transfer to the circuits on a parallelI/O bus (SCSI peripheral installed on an MMS board, for example).

Floppy interface

The floppy controller is 82078 (step 2) or PC 8477B (step 3) type. The connection to the floppy is bycable via the backplane.

V24 interfaces

Two V24 channels (COMC and COMD) are handled by a DUART (Dual Universal Asynchronous Re-ceiver/Transmitter).

Hard disk

The IDE standard hard disk with integrated controller has a minimum capacity of 350 MB.

Protection key

A key, protecting the software is plugged into a support.

4.2.4. Power supply

This is controlled by a power switch. The CM2 converter supplies the +5V/5A and +12V/60mA vol-tages required for board operation. An alarm signal (rectifier alarm) informs the control unit of rectifierfailure, thus allowing hard disk update before cut-off.

The "On/Off" signal is used to simultaneously start-up/cut-off the power supply to the CPU board andthe other boards connected on the CPU bus so that the bus interface circuits are not damaged.


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Section xx - CPU3 (step2-step3) board CPU3 board (step2 - step3)Configuration

44A03222123A020AAEN

CPU3 board (step2 - step3)ConfigurationEdition: 02

1. CPU3 step 2 board

1.1. Reference

CPU3 step 2 board: 3BA 57162 AB / 3BA 57162 BB (USA).

1.2. Presentation

The diagram below gives the position and number for each strap present on the CPU3 step 2 board.


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CPU3 board (step2 - step3) Section xx - CPU3 (step2-step3) boardConfiguration

Figure 3 : View of the CPU3 step 2 board

H1H2

X24

X25

X54X55X26

connecteurmicropac

1.3. Strappings

Ex-factory strappings are shown on a grey background.


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Alarm relay

Loop closed Loop open

X55 X55X54 X54

X26 X26

X24 X24

33 KOhms short-circuited33 KOhms in the loop

X25 X25Alarm loop

2. CPU3 step 3 board

2.1. Reference

CPU3 step 3 board: 3BA 57162 NA / 3BA 57162 MA (USA).

2.2. Presentation

The diagram below gives the position and number for each strap present on the CPU3 step 3 board.


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Figure 4 : View of the CPU3 step 3 board

H1H2

X24

X25

connecteurMicropac

X26

2.3. Strappings

Ex-factory strappings are shown on a grey background.


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Alarm relay

Loop closed Loop open

X25

X24

33 KOhms short-circuited33 KOhms in loop

X24

X25

Alarm loop

X26 X26

X26X26

Music on holdA law law

Board: 3BA 57162 NA

Board: 3BA 57162 MA (USA)

3. Meaning of the LED

3.1. Display

The CPU3 (step 2 or step 3) board has 2 LED located on the front panel.


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Figure 5 : CPU3 (step 2 or step 3) board front panel

CPU3

CPUETH

3.2. Meaning

Table 1 : Summary

LED Meaning

CPU (Green LED) CPU activity indicator

ETH (Orange LED) Ethernet link activity indicator

3.3. Cadencing

Table 2 : CPU LED

Cadencing Meaning

ON fixed Initialization in progress

100 ms (ON)/ 1s (OFF) Loading in progress

10 ms (ON)/ 10 ms (OFF) Re-flashing boot

300 ms (ON)/ 300 ms (OFF) CPU wait

8 x (900 ms (ON)/ 600 ms (OFF))/1 s (OFF) RAM Test error

8 x (300 ms (ON)/ 600 ms (OFF))/1 s (OFF) Checksum error


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Section xx - CPU3 (step2-step3) board CPU3 board (step2 - step3)Connection

44A03222123A030AAEN

CPU3 board (step2 - step3)ConnectionEdition: 02

1. Connection

The CPU3 (step 2 or 3) board must be installed in a CPU slot of the main ACT.

The CPU positions depend on the type of ACT (see the related cabinet installation documentation).

Daughter boards connection to CPU3 step 2-3

Figure 6 : Connection diagram

CPU3 board

Hard kee

Hard disk

Memory modules

VMU-OBCA board(option)

OBCA board(option)

The CPU3 connection to external components depends on the type of ACT:

- M2 or M3 cabinet, see module M2/M3 cabinet - Internal connections ,

- VH rack, see module VH rack - Internal connections ,

- WM1 rack, see module WM1 Rack - Internal connections .


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CPU3 board (step2 - step3) Section xx - CPU3 (step2-step3) boardConnection

2. Output pins

2.1. CPU3 step 2 board

The output pins of the CPU3 board step 2 are shown below:

C B A REMARKS

1 RXDA RIA TXDA

2 CTSA GND RTSA

TXDi, RXDi, RTSi,CTSi, DTRi, DSRi,DCDi, RIi = outputwires for the V24 Aand B

3 DSRA DCDA DTRA

4 RIB DCDB GND TR1, TR2 = wires forthe external musicon hold

5 RXDB DSRB GND

6 CTSB DTRB RTSB

7 TXDB GND GND

RESEXT1 = used toreset by applying12 V for 10 ms

8 GND GND (*) (*)see CPU5

9 TR2 GND TR1 CTSC, RTSC, RXDC,TXDC = port C(PIOC board)

10 CTSC RESEXT1 RTSC

11 RXDC RL1 TXDC

12 MICRN RL2 MICRP

MICEN, MICRN,MICEP, MICRP,SYNCN, SYNCP,CLKN, CLKP =wires for the 4630voice service

13 MICEN AL1 MICEP

14 SYNCP AL2 SYNCN RL1, RL2 =command forexternal lineforwarding

15 CLKP GND CLKN

16 SCSI_DPPN GND SCSI_D0N AL1, AL2 = alarmwires


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C B A REMARKS

17 TPI_RXP SCSI_D7N SCSI_D1N

18 TPI_RXN SCSI_D6N SCSI_D2N SCSI_xxx, TERMPWR= for the SCSIinterface

19 SCSI_SELN TPI_TXP SCSI_D3N

20 GND (*) TPI_TXN SCSI_D4N

21 SCSI_ACKN GND SCSI_D5N

TPI_RXP, TPI_RXN,TPI_TXP, TPI_TXN =for Ethernet in 10baseT

22 CTSD RESEXT2 RTSD

23 RXDD GND TXDD RESEXT2 = Notconnected

24 SCSI_BSYN GND SCSI_ATNN

25 INDX GND ME0 CTSD, RTSD, RXDD,TXDD = port D(PIOC board)

26 ME1 SCSI_RSTN DS0

27 DS1 SCSI_CDN DIR

28 STEP SCSI_ION WRDATA

29 WE 5V TRK0

30 WP GND RDDATA

INDX, ME0, ME1,DS0, DS1, DIR,STEP WRDATA,WE, 5V, TRK0, WP,RDDATA, HDSEL,DSKCHG = wiresfor the disk drive

31 HDSEL GND DSKCHG

32 SCSI_REQN GND TERMPWR

2.2. CPU3 step 3 board

The output pins of the CPU3 board step 3 are shown below:

C B A REMARQUES

1 RXDA RIA TXDA

2 CTSA GND RTSA

TXDi, RXDi, RTSi, CTSi, DTRi,DSRi, DCDi, RIi = outputwires for the V24 A and B

3 DSRA DCDA DTRA


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C B A REMARQUES

4 RIB DCDB GND TR1, TR2 =wires for theexternal music on hold

5 RXDB DSRB GND

6 CTSB DTRB RTSB

7 TXDB GND GND

RESEXT1 = used to reset byapplying 12 V current for 10ms

8 GND GND (*) (*) see CPU5

9 TR2 GND TR1 CTSC, RTSC, RXDC, TXDC =port C (PIOC board)

10 CTSC RESEXT1 RTSC

11 RXDC RL1 TXDC

12 MICRN RL2 MICRP

MICEN, MICRN, MICEP,MICRP, SYNCN, SYNCP,CLKN, CLKP = wires for theAlcatel 4630 voice services

13 MICEN AL1 MICEP

14 SYNCP AL2 SYNCN RL1, RL2 = command forexternal line forwarding

15 CLKP GND CLKN

16 GND AL1, AL2 = alarm wires

17 TPI_RXP

18 TPI_RXN

19 TPI_TXP

TPI_RXP, TPI_RXN, TPI_TXP,TPI_TXN = for Ethernet in 10baseT

20 GND (*) TPI_TXN

21 GND

22 CTSD RESEXT2 RTSD

23 RXDD GND TXDD RESEXT2 = Not connected

24 GND

25 INDX GND ME0 CTSD, RTSD, RXDD, TXDD =port D (PIOC board)

26 ME1 DS0

27 DS1 DIR


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C B A REMARQUES

28 STEP WRDATA

29 WE 5V TRK0

30 WP GND RDDATA

INDX, ME0, ME1, DS0, DS1,DIR, STEP WRDATA, WE, 5V,TRK0, WP, RDDATA, HDSEL,DSKCHG = wires for the diskdrive

31 HDSEL GND DSKCHG

32 GND


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Section xx - CPU3 (step2-step3) board OBCA boardOperation

44A03222503A100AAEN

OBCA boardOperationEdition: 01a

1. Presentation

The OBCA (Optimised B-channel CPU Access) board is a daughter board supporting 3 B channels at64 kbit/s.

It offers:

- remote access to the system (management, download),

- access to terminals for internal applications.

OBCA board reference : 3BA 23099 AA .

The OBCA board is a board not requiring configuration.

It is installed on a CPU3 (step 2 or 3) board (see module CPU3 board (step2 - step3) - Connection ) orCPU5 board (see module CPU5 step2 board - Connection or module CPU5 step3 board - Connection).


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OBCA board Section xx - CPU3 (step2-step3) boardOperation

2. Environment

2.1. Functional environment

Figure 7 : Integration of the OBCA board in the ACT architecture.

CPU

TA

V24

Terminal adapterwith protocol V120

OBCA

ApplicationsISA bus

Network

Applicationterminal

UA

BPRA

CPU board

T0/T2Remote access

C1

IPCM2


The OBCA board, installed on a CPU motherboard, is connected to the IPCM2 of the board C1 com-ponent.

The exchanges between the two boards are carried out via the ISA (Industry Standard Architecture) bus.


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2.3. Inputs/outputs

Figure 8 : OBCA board inputs/outputs diagram

+ 5 V

IPCM2 outputIPCM2 input

Synchros

ISA bus

Power supply

ISA interface

Physical interface

CPU

Communicationcontrol

3. General principle of operation

The OBCA board is a daughter board for CPU3 and CPU5 boards. It offers connection oriented fullduplex links between the CPU and the external entities. These links allow dialogs with character orpacket mode applications. This board can handle up to three channels B in HDLC mode. The OBCAboard can handle the following proocols: Q922, LAPD, LAPB, V120 synchronous and asynchronous.

The OBCA board only provides Frame Relay operation (D overflow into B) on the end nodes.

The OBCA board can handle several data links multiplexed on one physical channel. It can thereforeprocess up to 30 concurrent data links. It is not equipped with any circuit C1,thus it cannot handlepacket switching nor frame relay.

OBCA and IO2 boards can be fitted together on the same CPU. In this way, the amount of channelsB which can be operated concurrently is 33. However, the max. amount of channels B which can beoperated in packet or character mode remains at 30.


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4.1. List

The OBCA daughter board is made up of different blocks:

- CPU,

- physical interface,

- communication control,

- ISA interface,

- power supply.


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Figure 9 : OBCA board functional summary diagram

BACKPLANEFRONTPANEL

+5V Converter -48V

256 kHz

Physicalinterface

TSallocation

CPU

Memory

OBCA board+5V

CPU motherboard

IPCM2

ISAinterface

Synchros

ISA bus

Arbitrator

Register

Sharedmemory


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4.2.1. CPU

The CPU part, with its architecture organised around a 68302 microcontroller, handles the followingfunctions:

- management of the OBCA board,

- management of the physical interface with the motherboard,

- management of communications control.

There is no manual reset on the OBCA board (this function is carried out by the CPU motherboard).

4.2.2. Physical interface

The physical interface is connected to the Internal 2 PCM of the mother CPU board. The synchronisa-tions (4 MHz clock signal and 8 kHz frame sync signal) from the C1 component drive the OBCA board.

4.2.3. Communication control

The communications are carried out on 3 independent serial controllers. The 3 PCM channels of theIPCM2 are assigned as follows: TS1 = channel 1, TS2 = channel 2 and TS3 = channel 3.

4.2.4. ISA interface

The ISA interface handles the exchanges between the OBCA board and the mother CPU board via theISA bus. It allows the motherboard to access the shared memory, board register and CPU memory(download, maintenance functions).

The OBCA board is considered as an ISA bus peripheral.

4.2.5. Power supply

The board power supply is delivered from the converter located on the motherboard. Only the +5V isrequired.


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Section xx - CPU3 (step2-step3) board VMU-OBCA boardOperation

44A03222513A100AAEN

VMU-OBCA boardOperationEdition: 01a

1. Presentation

The VMU-OBCA board is a daughter board which is composed of 2 parts:

- a VMU (Voice Mail Unit) voice mail part which has 4 accesses (Alcatel 4615 voice mail),

- an OBCA (Optimized B-channel CPU Access) part which supports 3 64 kbit/s B channels.

The VMU-OBCA is a board not requiring configuration.

VMU-OBCA board reference: 3BA 53176 AA .

It must be installed only on a CPU3 step 2 or 3 motherboard (see module CPU3 board (step2 - step3)- Connection ).


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VMU-OBCA board Section xx - CPU3 (step2-step3) boardOperation

2. Environment

2.1. Functional environment

TA

V24

ISA bus

Network

Voice mailmanagement

terminal

UA

BPRA

T0/T2Remote access

C1

Mother board

VMU/OBCA

Z

UA

Set with voicemail system

CPU


The VMU-OBCA board, installed on a CPU motherboard, is connected to the IPCM2 of the board C1component.

The exchanges between the CPU3 and VMU-OBCA boards are conducted via the ISA bus.


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2.3. Inputs/outputs

Figure 10 : VMU-OBCA board environment

+ 5 V

PCM2

Synchros

Power supply

Physical interfaceand ISA interface

OBCA

Communicationcontrol

VMU

VMU-OBCA

PCM2

Systeminterface

Systeminterface

PCM0

CLK4MFSY28

PCM0

ISA bus

The system interface is composed of PCM links and synchronisation signals.

3. General principe of operation

The 2 VMU and OBCA parts integrate the following functions:

- ISA Bus Interface,

- shared FPGA (Field Programmable Gate Array) for the ISA (Industry Standard Architecture) Businterface command.

The VMU part has the following features:

- 2x64 Kwords DSP data memory,

- 512 Kwords of code memory,


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- 128 Mbits of FLASH NAND storage.

The OBCA part has the following features:

- MC68302 processor,

- 64 Kwords of code memory,

- 64 Kwords of shared memory.


4.1. List

The VMU-OBCA daughter board is constitued of the following parts:

- OBCA module,

- VMU module,

- power supply.


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Figure 11 : VMU-OBCA board functional summary diagram

EPROMNand

Slave DSP

Main DSP

CPLD

SRAM

SRAM

LogicReset

BACKPLANEFRONTPANEL

+5V

Convertor -48V

256 kHz

Arbitrator

Physicalinterface

TS assignment

CPU

Memory

OBCA part

CPU mother board

MICI2

ISAinterface

Synchros

Bus ISA

Register

Sharedmemory

+5V

VMU part

VMU/OBCA daughterboard


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4.2.1. OBCA moduleSee OBCA board (voir module OBCA board - Operation ).

4.2.2. VMU moduleThe Voice mail module (VMU) has 4 voice accesses, up to 128 voice mailboxes and 340 minutes ofspeech storage (maximum 4 minutes per message).VMU interfaceThe host interface of the slave DSP is used for all the exchanges with the CPU, including the start-up ofeach DSP. All the signalling messages are transferred from the slave DSP to the main DSP via the SSI0 interface.The host interface of the slave DSP is accessed via a logic applied to the CPLD (Complex ProgrammableLogic Device).The logic provides functional accesses, including the time conditions between the ISA-BUS interfaceand the host interface of the slave DSP.The quick interrupt of the slave DSP is used for both transfer directions between the CPU and the slaveDSP. The interrupt vector of the Host Receiver and the Host Emitter may be written as a move instructioninstead of a hop instruction. The DSP will insert this instruction in the normal execution of a waitingqueue without deleting this queue.The slave DSP must never inhibit the interrrupts for a duration greater than a word read access cycleor 2 bytes of the Host interface.Reset circuitAfter a CPU hardware reset, the VMU part must be reset. The reset may be removed from the VMUpart of the CPU software. The VMU part may be reset during a shutdown. The reset function appliesto the CPLDs OBCA part.DSP LLP programmingThe DSPs are controlled by the 4 MHz clock of the C1 link. The start-up program must have program-ming which is suitable for the PLL.Features of the main DSP

- Start-up by SSI 0 synchronous serial interface,

- Reset and interrupt of the EPROM NAND,

- Communication interrupt,

- Access time request,

- Configuration of the B port bits to control the external hardware,

- Configuration of the C port bits as SSI 0 synchronous serial interface,

- Interface of the signals to the CPLD,

- Data bus connection,


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- Exchange of speech data on TSs 1,2,3 and 4 of PCMI 0 and PCMO 0,

- Use of the SSI 0 synchronous serial interface to transfer the boot codes to the main DSP andexchange messages with the CPU.

Features of the slave DSP

- Communication interrupt to the main DSP,

- Access time request,

- Configuration of the B port bits to act as a host interface,

- Configuration of the C port bits as SSI 0 synchronous serial interface,

- Exchange of speech data on TSs 1,2,3 and 4 of PCMI 0 and PCMO 0,

- Use of the SSI 0 synchronous serial interface to transfer the boot codes to the main DSP andexchange messages with the CPU.

4.2.3. Power supply

The converter located on the mother board supplies the board with power. Only +5V will be used.


tocPresentationEnvironmentPosition in the rackInputs/outputsFigure 1 : CPU3 (step2-step3) board inputs/outputs diagram

General operating principlesFunctional blocksLISTFigure 2 : CPU3 (step2 or step3) board functional summary diagrBlocks descriptionControl unitI/O controllerInterfacesPower supply

CPU3 step 2 boardReferencePresentationFigure 3 : View of the CPU3 step 2 boardStrappings

CPU3 step 3 boardReferencePresentationFigure 4 : View of the CPU3 step 3 boardStrappings

Meaning of the LEDDisplayFigure 5 : CPU3 (step 2 or step 3) board front panel MeaningCadencing

ConnectionFigure 6 : Connection diagramOutput pinsCPU3 step 2 boardCPU3 step 3 board

PresentationEnvironmentFunctional environmentFigure 7 : Integration of the OBCA board in the ACT architecturePosition in the rackInputs/outputsFigure 8 : OBCA board inputs/outputs diagram

General principle of operationFunctional blocksListFigure 9 : OBCA board functional summary diagram Blocks descriptionCPUPhysical interfaceCommunication controlISA interfacePower supply

PresentationEnvironmentFunctional environmentPosition in the rackInputs/outputsFigure 10 : VMU-OBCA board environment

General principe of operationFunctional blocksListFigure 11 : VMU-OBCA board functional summary diagram Blocks descriptionOBCA moduleVMU modulePower supply

tablesTable 1 : SummaryTable 2 : CPU LED

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Documents

cpu3 step2step3 boardsection

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section xxcpu3 step2step3

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