CS 3204Operating SystemsGodmar BackLecture 15

*CS 3204 Fall 2008*AnnouncementsProject 2 due Oct 20, 11:59pmSee forum for additional office hoursReminder: need to pass 90% of tests of project 2 by the end of the semester to pass the classThats all tests (except for possibly multi-doom)P2 score will depend on what you pass by the deadline.P2 is a prerequisite for projects 3 and 4 if you cant get all tests to pass by submission deadline, fix them quickly

CS 3204 Fall 2008

Virtual Memory

*CS 3204 Fall 2008*Virtual MemoryIs not a kind of memoryIs a technique that combines one or more of the following concepts:Address translation (always)Paging (not always)Protection (not always, but usually)Can make storage that isnt physical random access memory appear as though it were

CS 3204 Fall 2008

*CS 3204 Fall 2008*Goals for Virtual MemoryVirtualizationMaintain illusion that each process has entire memory to itselfAllow processes access to more memory than is really in the machine (or: sum of all memory used by all processes > physical memory)Protection make sure theres no way for one process to access another processs data

CS 3204 Fall 2008

*CS 3204 Fall 2008*Context SwitchingProcess 1Process 2KernelP1 startsP2 startsP1 exitsP2 exits

CS 3204 Fall 2008

*CS 3204 Fall 2008*ustack (1)Process 1 Activein user modekernelkernelkernelkernelucode (1)kcodekdatakbsskheap0C0000000C0400000FFFFFFFF3 GB1 GBusedfreeuser (1)user (1)udata (1)user (1)user (2)user (2)user (2)access possible in user modeP1

CS 3204 Fall 2008

*CS 3204 Fall 2008*ustack (1)Process 1 Active in kernel modekernelkernelkernelkernelucode (1)kcodekdatakbsskheap0C0000000C0400000FFFFFFFF3 GB1 GBusedfreeuser (1)user (1)udata (1)user (1)user (2)user (2)user (2)access possible in user modeaccess requires kernel modeP1

CS 3204 Fall 2008

*CS 3204 Fall 2008*ustack (2)Process 2 Activein kernel modekernelkernelkernelkerneluser (1)user (1)user (1)ucode (2)kcodekdatakbsskheap0C0000000C0400000FFFFFFFF3 GB1 GBusedfreeuser (2)user (2)udata (2)user (2)access possible in user modeaccess requires kernel modeP2

CS 3204 Fall 2008

*CS 3204 Fall 2008*ustack (2)Process 2 Activein user modekernelkernelkernelkerneluser (1)user (1)user (1)ucode (2)kcodekdatakbsskheap0C0000000C0400000FFFFFFFF3 GB1 GBusedfreeuser (2)user (2)udata (2)user (2)access possible in user modeP2

CS 3204 Fall 2008

*CS 3204 Fall 2008*Page TablesHow are the arrows in previous pictures represented?Page Table: mathematical function Trans

Typically (though not on all architectures) haveTrans(pi, va, user, *) = Trans(pi, va, kernel, *) OR Trans(pi, va, user, *) = INVALIDE.g., user virtual addresses can be accessed in kernel modeTrans: { Process Ids } { Virtual Addresses } { user, kernel } ({ read, write, execute }) { Physical Addresses } { INVALID }

CS 3204 Fall 2008

*CS 3204 Fall 2008*Sharing VariationsWe get user-level sharing between processes p1 and p2 ifTrans(p1, va, user, *) = Trans(p2, va, user, *)Shared physical address doesnt need to be mapped at same virtual address, could be mapped at va in p1 and vb in p2:Trans(p1, va, user, *) = Trans(p2, vb, user, *)Can also map with different permissions: say p1 can read & write, p2 can only readTrans(p1, va, user, {read, write}) = Trans(p2, vb, user, {read})In Pintos (and many OS) the kernel virtual address space is shared among all processes & mapped at the same address:Trans(pi, va, kernel, *) = Trans(pk, va, kernel, *) for all processes pi and pk and va in [0xC0000000, 0xFFFFFFFF]

CS 3204 Fall 2008

Per-Process Page TablesCan either keep track of all mappings in a single table, or can split information between tablesone for each processmathematically: a projection onto a single processFor each process pi define a function PTransi as PTransi (va, *, *) = Trans(pi, va, user, *)Implementation: associate representation of this function with PCB, e.g., per-process hash tableEntries are called page table entries or PTEsNice side-effect: reduced need for synchronization if every process only adds/removes entries to its own page table*CS 3204 Fall 2008*

CS 3204 Fall 2008

*CS 3204 Fall 2008*Per-Process Page Tables (2)Common misconceptionUser processes use user page table and kernel uses kernel page table as if those were two tablesNot so (on x86): mode switch (interrupt, system call) does not change the page table that is usedIt only activates those entries that require kernel mode within the current processs page tableConsequence: kernel code also cannot access user addresses that arent mapped

CS 3204 Fall 2008

*CS 3204 Fall 2008*Non-Resident PagesWhen implementing virtual memory, some of a processs pages may be swapped outOr may not yet have been faulted inNeed to record that in page table:Trans (with paging): { Process Ids } { Virtual Addresses } { user, kernel } ({ read, write, execute }) { Physical Addresses } { INVALID } { Some Location On Disk }

CS 3204 Fall 2008

*CS 3204 Fall 2008*Implementing Page TablesMany, many variations possibleDone in combination of hardware & softwareHardware part: dictated by architectureSoftware part: up to OS designerMachine-dependent layer that implements architectural constraints (what hardware expects)Machine-independent layer that manages page tablesMust understand how TLB works first

CS 3204 Fall 2008

*CS 3204 Fall 2008*Page Tables Function & TLBFor each combination (process id, virtual_addr, mode, type of access) must decideIf access is permittedIf permitted:if page is resident, use physical addressif page is non-resident, page table has information on how to get the page in memoryCPU uses TLB for actual translation page table feeds the TLB on a TLB missTrans (with paging): { Process Ids } { Virtual Addresses } { user, kernel } { read, write, execute } { Physical Addresses } { INVALID } { Some Location On Disk }

CS 3204 Fall 2008

*CS 3204 Fall 2008*TLB

CS 3204 Fall 2008

*CS 3204 Fall 2008*TLB: Translation Look-Aside BufferVirtual-to-physical translation is part of every instruction (why not only load/store instructions?)Thus must execute at CPU pipeline speedTLB caches a number of translations in fast, fully-associative memorytypical: 95% hit rate (locality of reference principle)0xC00023450x00002345TLBVPN: Virtual Page NumberPPN: Physical Page NumberOffset

PermVPNPPNRWX K0xC00000x00000RWX K0xC00010x00001R-X K0xC00020x00002R-- K0xC00030x00003

CS 3204 Fall 2008

*CS 3204 Fall 2008*TLB ManagementNote: on previous slide example, TLB entries did not have a process idAs is true for x86Then: if process changes, some or all TLB entries may become invalidX86: flush entire TLB on process switch (refilling adds to cost!)Some architectures store process id in TLB entry (MIPS)Flushing (some) entries only necessary when process id reused

CS 3204 Fall 2008

*CS 3204 Fall 2008*Address Translation & TLBVirtual AddressTLB LookupCheck PermissionsPhysical AddressPage Fault ExceptionProtection FaultPage Table WalkPage Fault ExceptionPage Not PresentTLB ReloadTerminate Processmisshitrestart instructionpage presentelseokdeniedLoad Pagedone in hardwaredone in OS softwaredone in software or hardware

CS 3204 Fall 2008

*CS 3204 Fall 2008*TLB ReloadedTLB small: typically only caches 64-2,048 entriesWhat happens on a miss? must consult (walk) page table TLB Reload or RefillTLB Reload in software (MIPS)Via TLB miss handlers OS designer can pick any page table layout page table is only read & written by OSTLB Reload in hardware (x86)Hardware & software must agree on page table layout inasmuch as TLB miss handling is concerned page table is read by CPU, written by OSSome architectures allow either (PPC)

CS 3204 Fall 2008

*CS 3204 Fall 2008*Page Tables vs TLB ConsistencyNo matter which method is used, OS must ensure that TLB & page tables are consistentOn multiprocessor, this may require TLB shootdown For software-reloaded TLB: relatively easyTLB will only contain what OS handlers place into itFor hardware-reloaded TLB: two choicesUse same data structures for page table walk & page loading (hardware designers reserved bits for OSs use in page table)Use a layer on top (facilitates machine-independent implementation) this is the recommended approach for Pintos Project 3In this case, must update actual page table (on x86: page directory) that is consulted by MMU during page table walkCode is already written for you in pagedir.c

CS 3204 Fall 2008

*CS 3204 Fall 2008*Hardware/Software Split in PintosCPU cr3Machine-dependent Layer:pagedir.c codeMachine-independent Layer:your code & data structuressupplemental page table

CS 3204 Fall 2008