cs 35101 computer architecture spring 2008 week 11: 5.5, 5...

CS 35101 Ch5.75 Steinfadt, SP08 KSU

CS 35101Computer Architecture

Spring 2008

Week 11: 5.5, 5.7, 5.6

Materials adapted from Kevin Schaffer and Mary Jane Irwin(www.cse.psu.edu/~mji)

[adapted from D. Patterson slides]Single Cycle Disadvantages &Advantages


Multicycle Implementation Overview Each instruction step takes 1 clock cycle

Therefore, an instruction takes more than 1 clock cycle tocomplete

Not every instruction takes the same number of clockcycles to complete

Multicycle implementations allow faster clock rates different instructions to take a different number of clock

cycles functional units to be used more than once per instruction

as long as they are used on different clock cycles, as aresult

- only need one memory- only need one ALU/adder


Using Multiple Cycles Since instructions can take different number of

cycles to execute, can skip steps that are notneeded

Slow instructions don't slow down the entireprocessor

Can share hardware between steps However, control unit becomes more complicated


The Multicycle Datapath – A High Level View

Address

Read Data(Instr. or Data)

Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB A

LUou

t

Registers have to be added after every majorfunctional unit to hold the output value until it is usedin a subsequent clock cycle


Clocking the Multicycle Datapath

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB A

LUou

t

System Clock

MemWrite RegWrite

clock cycle


Break up the instructions into steps where each steptakes a clock cycle while trying to balance the amount of work to be done in each step use only one major functional unit per clock cycle

At the end of a clock cycle Store values needed in a later clock cycle by the current

instruction in a state element (internal register not visible tothe programmer)

IR – Instruction RegisterMDR – Memory Data RegisterA and B – Register File read data registersALUout – ALU output register

- All (except IR) hold data only between a pair of adjacent clockcycles (so they don’t need a write control signal)

Data used by subsequent instructions are stored inprogrammer visible state elements (i.e., Register File, PC,or Memory)

Our Multicycle Approach


The Complete Multicycle Data with Control

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Reading from or writing to any of the internal registers,Register File, or the PC occurs (quickly) at the beginning(for read) or the end of a clock cycle (for write)

Reading from the Register File takes ~50% of a clockcycle since it has additional control and accessoverhead (but reading can be done in parallel withdecode)

Had to add multiplexors in front of several of thefunctional unit input ports (e.g., Memory, ALU) becausethey are now shared by different clock cycles and/or domultiple jobs

All operations occurring in one clock cycle occur inparallel This limits us to one ALU operation, one Memory access,

and one Register File access per clock cycle

Our Multicycle Approach, con’t


New Control Signals ALUSrcA: selects first ALU operand to be either

the PC or the A register ALUSrcB: selects second ALU operand from: B

register, constant 4, sign-extended immediate,sign-extended and shifted immediate

MemtoReg: selects register file write data ascoming from either ALUOut or MDR

IorD: selects the memory address as coming fromeither PC or ALUOut


New Control Signals IRWrite: If asserted the memory output is written

to IR PCSource: Selects the new value for the PC from:

ALU, ALUOut, jump target address PCWrite: If asserted the PC is written PCWriteCond: If asserted and the zero output

from the ALU is 1 then the PC is written


Instruction Fetch

Instruction Decode and Register Fetch

R-type Instruction Execution, Memory Read/WriteAddress Computation, Branch Completion, orJump Completion

Memory Read Access, Memory Write Completionor R-type Instruction Completion

Memory Read Completion (Write Back)

INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

Five Instruction Steps


Use PC to get instruction from the memory and put itin the Instruction Register

Increment the PC by 4 and put the result back in thePC

Fetch instruction from memory IR ← Memory[PC]

Increment the PC PC ← PC + 4

Step 1: Instruction Fetch

Can we figure out the values of the control signals?

What is the advantage of updating the PC now?


Datapath Activity During Instruction Fetch

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Fetch Control Signals Settings

Start

Instr Fetch


Don’t know what the instruction is yet, so can only Read registers rs and rt in case we need them Compute the branch address in case the instruction is a

branch Fetch operands from register file

A ← Reg[IR[25:21]] B ← Reg[IR[20:16]]

Compute branch target address ALUOut ← PC + (SignExt(IR[15:0]) << 2)

Note we aren't setting any control lines based on theinstruction (since we don’t know what it is (the controllogic is busy "decoding" the op code bits))

Step 2: Instruction Decode and Register Fetch


Datapath Activity During Instruction Decode

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


ALU is performing one of four functions, based oninstruction type

Load/Store (lw and sw): Compute memory address ALUOut ← A + SignExt(IR[15:0])

R-type: Perform operation specified by instruction ALUOut ← A op B

Branch: Compare registers and set PC if equal if (A == B) PC ← ALUOut

Jump:Set PC to jump target address PC ← {PC[31:28] || (IR[25:0] << 2)}

Step 3 (instruction dependent)


Datapath Activity During lw & sw Execute

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Datapath Activity During R-type Execute

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Datapath Activity During beq Execute

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Datapath Activity During j Execute

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Execute Control Signals Settings

Start

Instr Fetch Decode

Execute

(Op = R-

type)

(Op =

beq)

(Op = lw or s

w) (Op = j)

Unless otherwise assigned

PCWrite,IRWrite, MemWrite,RegWrite=0 others=X

ALUSrcA=0ALUSrcB=11ALUOp=00

PCWriteCond=0

IorD=0MemRead;IRWrite

ALUSrcA=0ALUsrcB=01

PCSource,ALUOp=00PCWrite


Memory reference:Load: Read memory word into MDR MDR ← Memory[ALUOut]

Store: Write B into memory Memory[ALUOut] ← B

R-type: Write result to destination register Reg[IR[15:11]] ← ALUOut

Remember, the register write actually takes placeat the end of the cycle on the clock edge

Step 4 (also instruction dependent)


Datapath Activity During lw Memory Access

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Datapath Activity During sw Memory Access

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Datapath Activity During R-type Completion

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Memory Access Control Signals Settings

Start

Instr Fetch Decode

Memory Access

Execute

(Op = R-

type)

(Op =

beq)

(Op = lw or s

w) (Op = j)

(Op = lw)(Op = sw)




ALUSrcA=0ALUsrcB=01



PCWriteCond=0


PCWriteCond=0


PCWriteCond=0


PCSource=01PCWriteCond

PCSource=10PCWrite


All we have left is the write back into the registerfile the data just read from memory for lwinstruction

Load: Write result to destination register Reg[IR[20:16]] ← MDR

Step 5: Memory Read Completion (Write Back)


Datapath Activity During lw Write Back

Address


Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB

ALU

out

SignExtend

Shiftleft 2 ALU

control

Shiftleft 2

ALUOpControl

IRWriteMemtoReg

MemWriteMemRead

IorDPCWrite

PCWriteCond

RegDstRegWrite

ALUSrcAALUSrcB

zero

PCSource

1

1

1

1

1

10

0

0

0

0

0

2

2

3

4

Instr[5-0]

Instr[25-0]

PC[31-28]

Instr[15-0]

Instr[31-26]

32

28


Write Back Control Signals Settings

Start

Instr Fetch Decode

Write Back

Memory Access

Execute

(Op = R-

type)

(Op =

beq)

(Op = lw or s

w) (Op = j)

(Op = lw)(Op = sw)




ALUSrcA=0ALUsrcB=01



PCWriteCond=0


PCWriteCond=0


PCWriteCond=0


PCSource=01PCWriteCond

PCSource=10PCWrite

RegDst=1RegWrite

MemtoReg=0PCWriteCond=0

MemWriteIorD=1

PCWriteCond=0

MemReadIorD=1

PCWriteCond=0


RTL Summary

Reg[IR[20-16]]= MDR;

Write-back

MDR =Memory[ALUOut];

orMemory[ALUOut]

= B;

Reg[IR[15-11]] =ALUOut;

Memoryaccess

PC =PC[31-28]||(IR[25-0] << 2);

if(A==B)PC =

ALUOut;

ALUOut =A + sign-extend

(IR[15-0]);

ALUOut =A op B;

Execute

A = Reg[IR[25-21]];B = Reg[IR[20-16]];

ALUOut = PC +(sign-extend(IR[15-0])<< 2);

Decode

IR = Memory[PC];PC = PC + 4;

Instrfetch

JumpBranchMem RefR-typeStep


The x86 is an extremely complex instruction setarchitecture, and most of that complexity isembedded in the microcode. ... Every time themicroarchitecture must be changed, so must themicrocode, and all fundamental changes to either willexpose new areas in the microcode for which thepast is a poor guide to correctness.

The Pentium Chronicles, Colwell, pg. 66


How many cycles will it take to execute this code?

lw $t2, 0($t3)lw $t3, 4($t3)beq $t2, $t3, Label

#assume notadd $t5, $t2, $t3sw $t5, 8($t3)

Label: ...

What is going on during the 8th cycle of execution? In what cycle does the actual addition of $t2 and$t3 takes place?

In what cycle is the branch target address calculated?

Answering Simple Questions


Multicycle datapath control signals are not determinedsolely by the bits in the instruction e.g., op code bits tell what operation the ALU should be

doing, but not what instruction cycle is to be done next We can use a finite state machine for control

a set of states (current state stored in State Register) next state function

(determined by currentstate and the input)

output function (determined by currentstate and possibly the inputs)

Multicycle Control

Combinationalcontrol logic

State RegInst

Opcode

Datapathcontrolpoints

Next State

. . . . . .

. . .


In a Moore machine theoutput depends only on thestate; in a Mealy machinethe output depends on thestate and the inputs

So we are using a Mooremachine -- datapath controlsignals based only oncurrent state

Multicycle Control


State RegInst

Opcode

Datapathcontrolpoints

Next State

. . . . . .

. . .


State Machine


Complete State Machine


Control Unit The control unit for our multicycle datapath will be

a state machine The only input is the op field of the instruction; the

outputs are the control signals Each step may have multiple states if control

signals depend on the instruction


Finite State Machine Implementation


State RegInst[31-26]

NextState

Inputs

Out

puts

Op0

Op1

Op2

Op3

Op4

Op5

PCWritePCWriteCondIorDMemReadMemWriteIRWriteMemtoRegPCSourceALUOpALUSourceBALUSourceARegWriteRegDst

System Clock


Simplifying the Control Unit Design For an implementation of the full MIPS ISA instr’s

can take from 3 clock cycles to 20+ clock cycles resulting in finite state machines with hundreds to

thousands of states with even more arcs (statesequences)

- Such state machine representations become impossiblycomplex

Instead, can represent the set of control signals thatare asserted during a state as a low-level control“instruction” to be executed by the datapath

microinstructions “Executing” the microinstruction is equivalent to

asserting the control signals specified by themicroinstruction


Microprogramming A microinstruction has to specify

what control signals should be asserted what microinstruction should be executed next

Each microinstruction corresponds to one state in theFSM and is assigned a state number (or “address”)Sequential behavior – increment the state (address) of the current

microinstruction to get to the state (address) of the nextJump to the microinstruction that begins execution of the next MIPS

instruction (state 0)Branch to a microinstruction based on control unit input using

dispatch tables- need one for microinstructions following state 1- need another for microinstructions following state 2

The set of microinstructions that define a MIPSassembly language instruction (macroinstruction) isits microroutine


Defining a Microinstruction Format Format – the fields of the microinstruction and the

control signals that are affected by each field control signals specified by a field usually have functions

that are related format is chosen to simplify the representation and to

make it difficult to write inconsistent microinstructions- i.e., that allow a given control signal be set to two different

values

Make each field of the microinstruction responsiblefor specifying a nonoverlapping set of control signals signals that are never asserted simultaneously may share

the same field seven fields for our simple machine

- ALU control; SRC1; SRC2; Register control; Memory;PCWrite control; Sequencing


Microinstruction Fields

Seq, Fetch, Dispatch iSequencing

ALU, Cond, JumpPCWrite control

ReadPC, ReadALU, WriteMemory

Read, WriteALU, WriteMDRRegister control

B, 4, Ext, ExtShiftSrc2

PC, A, BSrc1

Add, Sub, FunctALU control

StringLabel

ValuesField


Creating the Microprogram Fetch microinstruction

Seq’ingPCWritecontrol

MemoryRegcontrol

SRC2SRC1ALUcontrol

Label(Addr)

SeqALURead PC4PCAddFetch(0)

compute PC + 4 fetch instrinto IR

write ALUoutput into

PC

go to µinstr1

Label field represents the state (address) of themicroinstruction

Fetch microinstruction assigned state (address) 0


The Entire Control Microprogram

FetchJumpJump1

FetchCondBASubBEQ1

FetchWriteALU

SeqBAFunctALU1

FetchWriteSW2

FetchWriteMDR

SeqReadALULW2

Dispatch 2ExtAAddMem1

Dispatch 1ReadExtShiftPCAdd

SeqALUReadPC4PCAddFetch

SequencingPCMemoryRegisterSrc 2Src 1ALULabel


Microcode Implementation

ControlPLA

Inst[31-26]

sequencingcontrol

Out

puts

Op0

Op1

Op2

Op3

Op4

Op5

PCWritePCWriteCondIorDMemReadMemWriteIRWriteMemtoRegPCSourceALUOpALUSourceBALUSourceARegWriteRegDst

System clock

Microprogram Counter

1

Adder

Addr select logic

AddrCtl


Control Path Design Alternatives

Initialrepresentation

Sequencingcontrol

Logicrepresentation

Implementationtechnique

Finite statediagram Microprogram

Explicit nextstate function

Microprogram counter+ dispatch PLAs

MicrocodeLogic

equations

ProgrammableLogic Array (PLA)

Microprogram representation advantages Easier to design, write, and debug


Exceptions An exception is an event that causes an

unscheduled transfer of control Also known as interrupts and traps Typically an interrupt is caused externally while an

exception or trap is caused internally Arithmetic overflow is an example of an exception;

an I/O device request is an example of aninterrupt


Handling Exceptions When hardware detects an exception it transfers

control to a software routine called an exceptionhandler which is typically a part of an operatingsystem

The hardware saves the value of the PC in theexception PC (EPC) register so it can return thereafter the exception is handled


Determining the Cause The hardware must tell the exception handler what

the cause of the exception was One way to do this is store a value into a special

Cause register (MIPS) Another way is to use vectored interrupts where

control is transferred to a different addressdepending on the cause


Exceptions to Implement Undefined instruction occurs when the op field

of an instruction indicates an undefined orunimplemented instruction

Arithmetic overflow occurs when the ALUdetects an overflow during an R-type instruction


Adding Exception Support EPC register saves the old PC; it is written when

EPCWrite is asserted Cause register records the cause of the exception;

it is written when CauseWrite is asserted IntCause indicates the cause of the exception Control is always transferred to 0x80000180


Adding Exception Support


Multicycle Advantages & Disadvantages Uses the clock cycle efficiently – the clock cycle is

timed to accommodate the slowest instruction step balance the amount of work to be done in each step restrict each step to use only one major functional unit

Multicycle implementations allow faster clock rates different instructions to take a different number of clock

cycles functional units to be used more than once per

instruction as long as they are used on different clockcycles

but Requires additional internal state registers, muxes,

and more complicated (FSM) control


Single Cycle vs. Multiple Cycle Timing

Clk Cycle 1

Multiple Cycle Implementation:

IFetch Dec Exec Mem WB

Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10

IFetch Dec Exec Memlw sw

IFetchR-type

Clk

Single Cycle Implementation:

lw sw Waste

Cycle 1 Cycle 2

multicycle clockslower than 1/5th ofsingle cycle clockdue to state registeroverhead

cs 35101 computer architecture spring 2008 week 11: 5.5, 5...

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