cs1104: computer organisation cs1104 lecture 4: logic gates and circuits cs1104
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CS1104: Computer Organisation
http://www.comp.nus.edu.sg/~cs1104
Lecture 4: Logic Gates and Circuits
CS1104-4 Lecture 4: Introduction to Logic Gates
2
Lecture 4:Logic Gates and Circuits
Logic Gates The Inverter The AND Gate The OR Gate The NAND Gate The NOR Gate The XOR Gate The XNOR Gate
Drawing Logic Circuit Analysing Logic Circuit Propagation Delay
CS1104-4 Lecture 4: Introduction to Logic Gates
3
Lecture 4: Logic Gates and Circuits
Universal Gates: NAND and NOR NAND Gate NOR Gate
Implementation using NAND Gates
Implementation using NOR Gates
Implementation of SOP Expressions
Implementation of POS Expressions
Positive and Negative Logic
Integrated Circuit Logic Families
CS1104-4 Logic Gates 4
Logic Gates Gate Symbols
EXCLUSIVE OR
a
ba.b
a
ba+b
a a'
a
b(a+b)'
a
b(a.b)'
a
ba b
a
ba.b&
a
ba+b1
AND
a a'1
a
b(a.b)'&
a
b(a+b)'1
a
ba b=1
OR
NOT
NAND
NOR
Symbol set 1 Symbol set 2
(ANSI/IEEE Standard 91-1984)
CS1104-4 Logic Gates: The Inverter 5
Logic Gates: The Inverter
The InverterA A'
0 11 0
A A' A A'
Application of the inverter: complement.
1
0
0
1
0
1
0
1
1
0
0
1
1
0
1
0
Binary number
1’s Complement
CS1104-4 Logic Gates: The AND Gate 6
Logic Gates: The AND Gate (1/2)
The AND Gate
A B A . B0 0 00 1 01 0 01 1 1
A
BA.B
&A
BA.B
CS1104-4 Logic Gates: The AND Gate 7
Logic Gates: The AND Gate (2/2)
Application of the AND Gate
1 sec
A
1 secEnable
A
EnableCounter
Reset to zero between Enable pulses
Register, decode and frequency display
CS1104-4 Logic Gates: The OR Gate 8
Logic Gates: The OR Gate
The OR Gate
1
A
BA+B
A
BA+B
A B A + B0 0 00 1 11 0 11 1 1
CS1104-4 Logic Gates: The NAND Gate 9
Logic Gates: The NAND Gate
The NAND Gate
&A
B(A.B)'
A
B(A.B)'
A
B(A.B)'
NAND Negative-OR
A B (A.B)'0 0 10 1 11 0 11 1 0
CS1104-4 Logic Gates: The NOR Gate 10
Logic Gates: The NOR Gate
The NOR Gate
NOR Negative-AND
1
A
B(A+B)'A
B(A+B)'
A
B(A+B)'
A B (A+B)'0 0 10 1 01 0 01 1 0
CS1104-4 Logic Gates: The XOR Gate 11
Logic Gates: The XOR Gate
The XOR Gate
=1A
BA B
A
BA B
A B A B0 0 00 1 11 0 11 1 0
CS1104-4 Logic Gates: The XNOR Gate 12
Logic Gates: The XNOR Gate
The XNOR Gate
A
B(A B)'
=1A
B(A B)'
A B (A B) '0 0 10 1 01 0 01 1 1
CS1104-4 Drawing Logic Circuit 13
Drawing Logic Circuit (1/2)
When a Boolean expression is provided, we can easily draw the logic circuit.
Examples:
(i) F1 = x.y.z' (note the use of a 3-input AND gate)
xy
z
F1
z'
CS1104-4 Drawing Logic Circuit 14
Drawing Logic Circuit (2/2)
(ii) F2 = x + y'.z (if we assume that variables and their complements are available)
(iii) F3 = x.y' + x'.z
x
y'z
F2
y'.z
x'z
F3
x'.z
x.y'xy'
CS1104-4 Quick Review Questions (1) 15
Quick Review Questions (1)
Textbook page 77.
Questions 4-1, 4-2.
CS1104-4 Analysing Logic Circuit 16
Analysing Logic Circuit
When a logic circuit is provided, we can analyse the circuit to obtain the logic expression.
Example: What is the Boolean expression of F4?
A'.B'
A'.B'+C (A'.B'+C)'
A'
B'
CF4
F4 = (A'.B'+C)' = (A+B).C'
CS1104-4 Propagation Delay 17
Propagation Delay (1/3) Every logic gate experiences some delay (though
very small) in propagating signals forward.
This delay is called Gate (Propagation) Delay.
Formally, it is the average transition time taken for the output signal of the gate to change in response to changes in the input signals.
Three different propagation delay times associated with a logic gate: tPHL: output changing from the High level to Low level
tPLH: output changing from the Low level to High level
tPD=(tPLH + tPHL)/2 (average propagation delay)
CS1104-4 Propagation Delay 18
Propagation Delay (2/3)
Input Output
Output
InputH
L
L
H
tPHL tPLH
CS1104-4 Propagation Delay 19
Propagation Delay (3/3)
A B C
Ideally, no delay:
1
0
1
0
0
1
time
Signal for C
Signal for B
Signal for A
In reality, output signals normally lag behind input signals:
1
0
1
0
0
1
time
Signal for C
Signal for B
Signal for A
CS1104-4 Calculation of Circuit Delays 20
Calculation of Circuit Delays (1/3) Amount of propagation delay per gate depends on:
(i) gate type (AND, OR, NOT, etc) (ii) transistor technology used (TTL,ECL,CMOS etc), (iii) miniaturisation (SSI, MSI, LSI, VLSI)
To simplify matters, one can assume (i) an average delay time per gate, or (ii) an average delay time per gate-type.
Propagation delay of logic circuit= longest time it takes for the input signal(s) to propagate to the
output(s).
= earliest time for output signal(s) to stabilise, given that input signals are stable at time 0.
CS1104-4 Calculation of Circuit Delays 21
Calculation of Circuit Delays (2/3) In general, given a logic gate with delay, t.
If inputs are stable at times t1,t2,..,tn, respectively; then the earliest time in which the output will be stable is:
max(t1, t2, .., tn) + t
LogicGate
t1
t2
tn
: :
max (t1, t2, ..., tn ) + t
To calculate the delays of all outputs of a combinational circuit, repeat above rule for all gates.
CS1104-4 Calculation of Circuit Delays 22
Calculation of Circuit Delays (3/3) As a simple example, consider the full adder circuit
where all inputs are available at time 0. (Assume each gate has delay t.)
where outputs S and C, experience delays of 2t and 3t, respectively.
XY S
C
Z
max(0,0)+t = t
t
0
0
0
max(t,0)+t = 2t
max(t,2t)+t = 3t2t
CS1104-4 Quick Review Questions (2) 23
Quick Review Questions (2)
Textbook page 77.
Questions 4-3 to 4-5.
CS1104-4 Universal Gates: NAND and NOR 24
Universal Gates: NAND and NOR AND/OR/NOT gates are sufficient for building any
Boolean functions. We call the set {AND, OR, NOT} a complete set of
logic.
However, other gates are also used because:(i) usefulness(ii) economical on transistors(iii) self-sufficient
NAND/NOR: economical, self-sufficientXOR: useful (e.g. parity bit generation)
CS1104-4 NAND Gate 25
NAND Gate (1/2)
NAND gate is self-sufficient (can build any logic circuit with it).
Therefore, {NAND} is also a complete set of logic.
Can be used to implement AND/OR/NOT.
Implementing an inverter using NAND gate:
(x.x)' = x' (T1: idempotency)
x x'
CS1104-4 NAND Gate 26
NAND Gate (2/2)
((x.y)'(x.y)')' = ((x.y)')' idempotency = (xy) involution
((x.x)'(y.y)')' = (x'.y')' idempotency = x''+y'' DeMorgan = x+y involution
Implementing AND using NAND gates:
Implementing OR using NAND gates:
xx.y
y
(x.y)'
x
x+y
y
x'
y'
CS1104-4 NOR Gate 27
NOR Gate (1/2)
NOR gate is also self-sufficient. Therefore, {NOR} is also a complete set of logic
Can be used to implement AND/OR/NOT.
Implementing an inverter using NOR gate:
(x+x)' = x' (T1: idempotency)
x x'
CS1104-4 NOR Gate 28
NOR Gate (2/2)
((x+x)'+(y+y)')'=(x'+y')' idempotency = x''.y'' DeMorgan = x.y involution
((x+y)'+(x+y)')' = ((x+y)')' idempotency = (x+y) involution
Implementing AND using NOR gates:
Implementing OR using NOR gates:
xx+y
y
(x+y)'
x
x.y
y
x'
y'
CS1104-4 Implementation using NAND gates
29
Implementation using NAND gates (1/2)
Possible to implement any Boolean expression using NAND gates.
Procedure:
(i) Obtain sum-of-products Boolean expression:
e.g. F3 = x.y'+x'.z
(ii) Use DeMorgan theorem to obtain expression using 2-level NAND gates
e.g. F3 = x.y'+x'.z
= (x.y'+x'.z)' ' involution
= ((x.y')' . (x'.z)')' DeMorgan
CS1104-4 Implementation using NAND gates
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Implementation using NAND gates (2/2)
F3 = ((x.y')'.(x'.z)') ' = x.y' + x'.z
x'z
F3
(x'.z)'
(x.y')'xy'
CS1104-4 Implementation using NOR gates 31
Implementation using NOR gates (1/2)
Possible to implement any Boolean expression using NOR gates.
Procedure:
(i) Obtain product-of-sums Boolean expression:
e.g. F6 = (x+y').(x'+z)
(ii) Use DeMorgan theorem to obtain expression using 2-level NOR gates.
e.g. F6 = (x+y').(x'+z)
= ((x+y').(x'+z))' ' involution
= ((x+y')'+(x'+z)')' DeMorgan
CS1104-4 Implementation using NOR gates 32
Implementation using NOR gates (2/2)
F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)
x'z
F6
(x'+z)'
(x+y')'xy'
CS1104-4 Implementation of SOP Expressions
33
Implementation of SOP Expressions (1/2)
Sum-of-Products expressions can be implemented using: 2-level AND-OR logic circuits 2-level NAND logic circuits
AND-OR logic circuit
F = A.B + C.D + E
F
A
B
D
C
E
CS1104-4 Implementation of SOP Expressions
34
Implementation of SOP Expressions (2/2)
NAND-NAND circuit (by circuit transformation)
a) add double bubbles
b) change OR-with- inverted-inputs to NAND & bubbles at inputs to their complements
F
A
B
D
C
E
A
B
D
C
E'
F
CS1104-4 Implementation of POS Expressions
35
Implementation of POS Expressions (1/2)
Product-of-Sums expressions can be implemented using: 2-level OR-AND logic circuits 2-level NOR logic circuits
OR-AND logic circuit
G = (A+B).(C+D).E
G
A
B
D
C
E
CS1104-4 Implementation of POS Expressions
36
Implementation of POS Expressions (2/2)
NOR-NOR circuit (by circuit transformation):
a) add double bubbles
b) changed AND-with- inverted-inputs to NOR & bubbles at inputs to their complements
G
A
B
D
C
E
A
B
D
C
E'
G
CS1104-4 Quick Review Questions (3) 37
Quick Review Questions (3)
Textbook page 77.
Questions 4-6 to 4-8.
CS1104-4 Positive & Negative Logic 38
Positive & Negative Logic (1/3)
In logic gates, usually: H (high voltage, 5V) = 1 L (low voltage, 0V) = 0
This convention is known as positive logic.
However, the reverse convention, negative logic possible: H (high voltage) = 0 L (low voltage) = 1
Depending on convention, same gate may denote different Boolean function.
CS1104-4 Positive & Negative Logic 39
Positive & Negative Logic (2/3)
A signal that is set to logic 1 is said to be asserted, or active, or true.
A signal that is set to logic 0 is said to be deasserted, or negated, or false.
Active-high signal names are usually written in uncomplemented form.
Active-low signal names are usually written in complemented form.
CS1104-4 Positive & Negative Logic 40
Positive & Negative Logic (3/3)
Positive logic:
Negative logic:
EnableActive High: 0: Disabled 1: Enabled
Enable
Active Low: 0: Enabled 1: Disabled
CS1104-4 Integrated Circuit Logic Families 41
Integrated Circuit Logic Families (1/2)
Some digital integrated circuit families: TTL, CMOS, ECL. TTL: Transistor-Transistor Logic.
Uses bipolar junction transistors Consists of a series of logic circuits: standard TTL, low-power
TTL, Schottky TTL, low-power Schottky TTL, advanced Schottky TTL, etc.
TTL Series Prefix Designation Example of Device
Standard TTL 54 or 74 7400 (quad NAND gates)
Low-power TTL 54L or 74L 74L00 (quad NAND gates)
Schottky TTL 54S or 74S 74S00 (quad NAND gates)
Low-powerSchottky TTL
54LS or 74LS 74LS00 (quad NAND gates)
CS1104-4 Integrated Circuit Logic Families 42
Integrated Circuit Logic Families (2/2)
CMOS: Complementary Metal-Oxide Semiconductor. Uses field-effect transistors
ECL: Emitter Coupled Logic. Uses bipolar circuit technology. Has fastest switching speed but high power consumption.
Performance characteristics Propagation delay time. Power dissipation. Fan-out: Fan-out of a gate is the maximum number of inputs
that the gate can drive. Speed-power product (SPP): product of the propagation
delay time and the power dissipation.
CS1104-4 Summary 43
SummaryLogic Gates
AND, OR, NOT
NAND
NOR
Drawing Logic Circuit
Analysing Logic Circuit
Given a Boolean expression, draw the circuit.
Given a circuit, find the function.
Implementation of a Boolean expression using these Universal gates.
Implementation of SOP and POS Expressions
Positive and Negative Logic
Concept of Minterm and Maxterm
CS1103 Chapter 1: Introduction
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