cs222: x86 isa computer arithmetic · 2017-04-12 · intel x86 features • complexity: – it...
TRANSCRIPT
CS222: X86 ISA & Computer Arithmetic
Dr. A. Sahu
Dept of Comp. Sc. & Engg.Dept of Comp. Sc. & Engg.
Indian Institute of Technology Guwahati
1
OutlineOutline• CISC
– X86 ISA: Intel architectures history
• Computer Arithmetic's:Computer Arithmetic s: – Integer, Float, Double: ALU, FU‐IFU/SFU/DFU
Bi t ti• Binary representation
• Adder/Substractor/
• Variation of Adder
VAX instruction with 6 operandsVAX instruction with 6 operands
addp6 op1 op2 op3 op4 op5 op6addp6 op1, op2, op3, op4, op5, op6
⇒add two packed decimal numbers
op1, op2: length and start addr of number1
op3, op4: length and start addr of number2
op5 op6: length and start addr of sumop5, op6: length and start addr of sum
Intel x86 historyIntel x86 historyGrown from 4 bit ⇒ 8 bit ⇒ 16 bit ⇒ 32 bit
• 1978: 8086 is announced (16 bit architecture)• 1980: 8087 floating point coprocessor is added• 1982: 80286 increases address space to 24 bits, +instructions
• 1985: 80386 extends to 32 bits new addressing• 1985: 80386 extends to 32 bits, new addressing modes
• 1989‐1995: 80486, Pentium, Pentium Pro add a few1989 1995: 80486, Pentium, Pentium Pro add a few instr (designed for higher performance)
• 1997: MMX is added
Comments on Intel x86Comments on Intel x86• “This history illustrates the impact of the golden handcuffs of compatibility”
• “adding new features as someone might add g gclothing to a packed bag”
• “an architecture that is difficult to explain andan architecture that is difficult to explain and impossible to love”
• “what the 80x86 lacks in style is made up in• what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”perspective
Intel x86 featuresIntel x86 features• Complexity:
I t ti ( 350) f 1 t 17 b t l– Instructions (~350) from 1 to 17 bytes long– one operand must act as both a src and dstone operand can come from memory– one operand can come from memory
– complex addressing modes, e.g., “base or scaled index with 8 or 32 bit displacement”index with 8 or 32 bit displacement
– Permitted instruction ‐ address mode combinations irregular (lots of special cases, hard to learn!)
– Effect by each instruction on condition codes is somewhat complex irregularsomewhat complex, irregular
Intel x86 features – contd.Intel x86 features contd.
• Saving grace:Saving grace:– the most frequently used instructions are not too difficult to buildnot too difficult to build
– compilers avoid the portions of the architecture that are slowarchitecture that are slow
L b A M C 86 A hi• Larrabee: A Many Core x86 Architecture for Visual Computing (Craped in 2010)
Bus Interface Unit
C BUS
Q6Q6Q5Q5Q4Q4Q3Q3Q2Q2Q1Q1
SUM
CS (Code Seg Reg)CS (Code Seg Reg)DS (Data Seg Reg )DS (Data Seg Reg )ES (Extra Seg Reg )ES (Extra Seg Reg )SS (Stack Seg Reg)SS (Stack Seg Reg)
IP (Intr Ptr) Sequencer( )IP (Intr Ptr)OperandOperandInDirectInDirect
SequencerExecution
Unit A BUS
AHAH ALALBHBH BLBLCHCH CLCLDHDH DLDL
SI (Source Idx )SI (Source Idx )DI (Dest Idx)
Temp ATemp ATemp B Temp B Temp CTemp C
( )DI (Dest. Idx)BP (Base Ptr )BP (Base Ptr )SP (Stack Ptr)SP (Stack Ptr)
Z (Flag Reg)
ALU
• AX ‐ the accumulator register (divided into AH / AL) AH AL• BX ‐ the base address register (divided into BH / BL)
• CX ‐ the count register (divided into CH / CL)
• DX ‐ the data register (divided into DH / DL)
BHBH BLBLCHCH CLCLDHDH DLDL
DX the data register (divided into DH / DL)
• SI ‐ source index register.
d i i i d i
SI (Source Idx )DI (Dest. Idx)DI (Dest. Idx)BP (Base Ptr )BP (Base Ptr )SP (St k Pt )• DI ‐ destination index register.
• BP ‐ base pointer.
• SP ‐ stack pointer.
SP (Stack Ptr)
CS (Code Seg Reg)
Z (Flag Reg)
CS (Code Seg Reg)DS (Data Seg Reg )DS (Data Seg Reg )ES (Extra Seg Reg )ES (Extra Seg Reg )SS (Stack Seg Reg)SS (Stack Seg Reg)
IP (Intr Ptr)IP (Intr Ptr)
AH ALEAX31 15 7 0
BHBH BLBLCHCH CLCLDHDH DLDL
EBXEBXECXECXEDXEDX
SI (Source Idx )DI (Dest. Idx)DI (Dest. Idx)BP (Base Ptr )BP (Base Ptr )SP (St k Pt )
ESIEDIEDIEBPEBPESP
Extended
SP (Stack Ptr)
CS (Code Seg Reg)
Z (Flag Reg)
ESP
ECS
EZ
CS (Code Seg Reg)DS (Data Seg Reg )DS (Data Seg Reg )ES (Extra Seg Reg )ES (Extra Seg Reg )SS (Stack Seg Reg)
ECSEDSEDSEESEESESS SS (Stack Seg Reg)
IP (Intr Ptr)IP (Intr Ptr)
ESS
EIPEIP
• 1978: 8086 (16 bit architecture)• 1978: 8086 (16 bit architecture)• 1980: 8087
• Floating point coprocessor is added
• 1982: 80286 • Increases address space to 24 bits
• 1985: 80386: • 32 bits Add, • Virtual Mem & new add modes • Protected mode (OS support)
• 1989-95: 80486/Pentium/Pro• Added a few instructions of base MMX
• 1997: Pentium II• 1997: Pentium II • 57 new “MMX” instructions are added,
• 1999: Pentium III:• 1999: Pentium III: • Out of Order, added another 70 Streaming SIMD Ext (SSE)
• 2001: Pentium 4• 2001: Pentium 4• Net burst, another 144 instructions (SSE2)
• 2003: PI4 HT Trace Cache• 2003: PI4 HT, Trace Cache• 2005: Centrino, low power
2007 C hit t D• 2007: Core architecture, Duo • 2008: Atom, Quad core with HT….• 2009---:Multi core (Large chip multiprocessor)
Intel x86 : peculiar featureIntel x86 : peculiar featureUpto 3 “prefixes” for an instruction
• Override default data size
• Override default segment registerOverride default segment register
• Lock bus for a semaphore
R t th f ll i i t ti• Repeat the following instruction
• Override default address size
RISC /CISC ContributionRISC /CISC Contribution
• PowerPC : RISC with powerful branchPowerPC : RISC with powerful branch instructions
• SPARC : RISC with register windows• SPARC : RISC with register windows
• VAX : CISC with addressing modes orthogonal dto opcodes
• Intel X86 : CISC with code compatibility over several generations
Computer Arithmetic: C Assembly Machine
• C : short int long float doubleC : short, int, long, float, double
• 16 bit, 32 bit, 32 bit, 32 bit, 64 bit
Si d/ i d• Signed/Unsigned
• Have a FU in your processor– Processor is capable to do it in hardware
– 8086: No support of FP, 8087 FP Co processor
• If you don’t have FPU : Write FP in software– $gcc –mfloat‐soft –S test c$gcc mfloat soft S test.c
– undefined reference to `__mulsf3'15
RepresentationRepresentation• Int’s are not Integers, Float’s are not Reals
• Int : 8, 16, 32, 64 bit (char, short, int, long)
• Real – Fixed point: N bit Int part . M for real part (Software Emul)
• User defiened
– Floating point: 32,64 (float‐SingleFP/double‐doubleFP)
• IEEE 754 format
16
Basic Units of ComputerBasic Units of Computer
InstructionData
PC
InstructionMemory
AddressInstruction
Register FILE
AddressReg#
Reg#Data
Memory ALU
Instruction FILEReg#
Reg#
Data
17
ALU: Arithmetic and Logic UnitALU: Arithmetic and Logic Unit
• Binary arithmetic and ALU design• Signed operations, overflow• Compare/Shift A
R l• Multiplier design• Divider design ALUB
Result
• Speeding up addition/subtraction• Floating point representation
and operations• Floating point unit design
Operation
18