cs2252-nol
TRANSCRIPT
ByRHARINI
CS2252MICROPROCESSORS AND MICROCONTROLLERS
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
AIM
To have an in depth knowledge of the architecture and programming of 8-bit
and 16-bit Microprocessors Microcontrollers and to study how to interface
various peripheral devices with them
OBJECTIVE
To study the architecture and Instruction set of 8085 and 8086
To develop assembly language programs in 8085 and 8086
To design and understand multiprocessor configurations
To study different peripheral devices and their interfacing to 80858086
To study the architecture and programming of 8051 microcontroller
UNIT I THE 8085 AND 8086 MICROPROCESSORS8085 Microprocessor architecture-Addressing modes- Instruction set-Programming the 8085
UNIT II 8086 SOFTWARE ASPECTS Intel 8086 microprocessor - Architecture - Signals- Instruction Set-Addressing Modes-Assembler Directives- Assembly Language Programming-Procedures-Macros-Interrupts And Interrupt Service Routines-BIOS function calls
UNIT III MULTIPROCESSOR CONFIGURATIONS Coprocessor Configuration ndash Closely Coupled Configuration ndash Loosely Coupled Configuration ndash8087 Numeric Data Processor ndash Data Types ndash Architecture ndash8089 IO Processor ndashArchitecture ndashCommunication between CPU and IOP
UNIT IV IO INTERFACING Memory interfacing and IO interfacing with 8085 ndash parallel communication interface ndash serial communication interface ndash timer-keyboarddisplay controller ndash interrupt controller ndash DMA controller (8237) ndash applications ndash stepper motor ndash temperature control
UNIT V MICROCONTROLLERS Architecture of 8051 Microcontroller ndash signals ndash IO ports ndash memory ndash counters and timers ndash serial data IO ndash interrupts-Interfacing -keyboard LCDADC amp DAC
UNIT I
THE 8085 MICROPROCESSOR
11 Introduction to 8085 12 Microprocessor architecture 13 Instruction set 14 Addressing modes 15 Programming the 8085
11 8085 PROCESSOR
bullThe first microprocessor was introduced in 1970 by Intel (named 4004)bull It ran at the speed of 108KHzbull Four years later Intel created the 8080 running at just over 2 Mhz bullThis microprocessor was used on the worlds firs personal computer named Altair bullAlso at this time IBM started researching for their microprocessor called POWER (Performance Optimization With Enhanced RISC)
12 Microprocessor architecture
Control Unit Arithmetic Logic Unit Registers Accumulator Flags Program Counter (PC) Stack Pointer (SP) Instruction RegisterDecoder Memory Address Register General Purpose Registers Control Generator Register Selector Microprogramming
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
AIM
To have an in depth knowledge of the architecture and programming of 8-bit
and 16-bit Microprocessors Microcontrollers and to study how to interface
various peripheral devices with them
OBJECTIVE
To study the architecture and Instruction set of 8085 and 8086
To develop assembly language programs in 8085 and 8086
To design and understand multiprocessor configurations
To study different peripheral devices and their interfacing to 80858086
To study the architecture and programming of 8051 microcontroller
UNIT I THE 8085 AND 8086 MICROPROCESSORS8085 Microprocessor architecture-Addressing modes- Instruction set-Programming the 8085
UNIT II 8086 SOFTWARE ASPECTS Intel 8086 microprocessor - Architecture - Signals- Instruction Set-Addressing Modes-Assembler Directives- Assembly Language Programming-Procedures-Macros-Interrupts And Interrupt Service Routines-BIOS function calls
UNIT III MULTIPROCESSOR CONFIGURATIONS Coprocessor Configuration ndash Closely Coupled Configuration ndash Loosely Coupled Configuration ndash8087 Numeric Data Processor ndash Data Types ndash Architecture ndash8089 IO Processor ndashArchitecture ndashCommunication between CPU and IOP
UNIT IV IO INTERFACING Memory interfacing and IO interfacing with 8085 ndash parallel communication interface ndash serial communication interface ndash timer-keyboarddisplay controller ndash interrupt controller ndash DMA controller (8237) ndash applications ndash stepper motor ndash temperature control
UNIT V MICROCONTROLLERS Architecture of 8051 Microcontroller ndash signals ndash IO ports ndash memory ndash counters and timers ndash serial data IO ndash interrupts-Interfacing -keyboard LCDADC amp DAC
UNIT I
THE 8085 MICROPROCESSOR
11 Introduction to 8085 12 Microprocessor architecture 13 Instruction set 14 Addressing modes 15 Programming the 8085
11 8085 PROCESSOR
bullThe first microprocessor was introduced in 1970 by Intel (named 4004)bull It ran at the speed of 108KHzbull Four years later Intel created the 8080 running at just over 2 Mhz bullThis microprocessor was used on the worlds firs personal computer named Altair bullAlso at this time IBM started researching for their microprocessor called POWER (Performance Optimization With Enhanced RISC)
12 Microprocessor architecture
Control Unit Arithmetic Logic Unit Registers Accumulator Flags Program Counter (PC) Stack Pointer (SP) Instruction RegisterDecoder Memory Address Register General Purpose Registers Control Generator Register Selector Microprogramming
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
OBJECTIVE
To study the architecture and Instruction set of 8085 and 8086
To develop assembly language programs in 8085 and 8086
To design and understand multiprocessor configurations
To study different peripheral devices and their interfacing to 80858086
To study the architecture and programming of 8051 microcontroller
UNIT I THE 8085 AND 8086 MICROPROCESSORS8085 Microprocessor architecture-Addressing modes- Instruction set-Programming the 8085
UNIT II 8086 SOFTWARE ASPECTS Intel 8086 microprocessor - Architecture - Signals- Instruction Set-Addressing Modes-Assembler Directives- Assembly Language Programming-Procedures-Macros-Interrupts And Interrupt Service Routines-BIOS function calls
UNIT III MULTIPROCESSOR CONFIGURATIONS Coprocessor Configuration ndash Closely Coupled Configuration ndash Loosely Coupled Configuration ndash8087 Numeric Data Processor ndash Data Types ndash Architecture ndash8089 IO Processor ndashArchitecture ndashCommunication between CPU and IOP
UNIT IV IO INTERFACING Memory interfacing and IO interfacing with 8085 ndash parallel communication interface ndash serial communication interface ndash timer-keyboarddisplay controller ndash interrupt controller ndash DMA controller (8237) ndash applications ndash stepper motor ndash temperature control
UNIT V MICROCONTROLLERS Architecture of 8051 Microcontroller ndash signals ndash IO ports ndash memory ndash counters and timers ndash serial data IO ndash interrupts-Interfacing -keyboard LCDADC amp DAC
UNIT I
THE 8085 MICROPROCESSOR
11 Introduction to 8085 12 Microprocessor architecture 13 Instruction set 14 Addressing modes 15 Programming the 8085
11 8085 PROCESSOR
bullThe first microprocessor was introduced in 1970 by Intel (named 4004)bull It ran at the speed of 108KHzbull Four years later Intel created the 8080 running at just over 2 Mhz bullThis microprocessor was used on the worlds firs personal computer named Altair bullAlso at this time IBM started researching for their microprocessor called POWER (Performance Optimization With Enhanced RISC)
12 Microprocessor architecture
Control Unit Arithmetic Logic Unit Registers Accumulator Flags Program Counter (PC) Stack Pointer (SP) Instruction RegisterDecoder Memory Address Register General Purpose Registers Control Generator Register Selector Microprogramming
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
UNIT I THE 8085 AND 8086 MICROPROCESSORS8085 Microprocessor architecture-Addressing modes- Instruction set-Programming the 8085
UNIT II 8086 SOFTWARE ASPECTS Intel 8086 microprocessor - Architecture - Signals- Instruction Set-Addressing Modes-Assembler Directives- Assembly Language Programming-Procedures-Macros-Interrupts And Interrupt Service Routines-BIOS function calls
UNIT III MULTIPROCESSOR CONFIGURATIONS Coprocessor Configuration ndash Closely Coupled Configuration ndash Loosely Coupled Configuration ndash8087 Numeric Data Processor ndash Data Types ndash Architecture ndash8089 IO Processor ndashArchitecture ndashCommunication between CPU and IOP
UNIT IV IO INTERFACING Memory interfacing and IO interfacing with 8085 ndash parallel communication interface ndash serial communication interface ndash timer-keyboarddisplay controller ndash interrupt controller ndash DMA controller (8237) ndash applications ndash stepper motor ndash temperature control
UNIT V MICROCONTROLLERS Architecture of 8051 Microcontroller ndash signals ndash IO ports ndash memory ndash counters and timers ndash serial data IO ndash interrupts-Interfacing -keyboard LCDADC amp DAC
UNIT I
THE 8085 MICROPROCESSOR
11 Introduction to 8085 12 Microprocessor architecture 13 Instruction set 14 Addressing modes 15 Programming the 8085
11 8085 PROCESSOR
bullThe first microprocessor was introduced in 1970 by Intel (named 4004)bull It ran at the speed of 108KHzbull Four years later Intel created the 8080 running at just over 2 Mhz bullThis microprocessor was used on the worlds firs personal computer named Altair bullAlso at this time IBM started researching for their microprocessor called POWER (Performance Optimization With Enhanced RISC)
12 Microprocessor architecture
Control Unit Arithmetic Logic Unit Registers Accumulator Flags Program Counter (PC) Stack Pointer (SP) Instruction RegisterDecoder Memory Address Register General Purpose Registers Control Generator Register Selector Microprogramming
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
UNIT I
THE 8085 MICROPROCESSOR
11 Introduction to 8085 12 Microprocessor architecture 13 Instruction set 14 Addressing modes 15 Programming the 8085
11 8085 PROCESSOR
bullThe first microprocessor was introduced in 1970 by Intel (named 4004)bull It ran at the speed of 108KHzbull Four years later Intel created the 8080 running at just over 2 Mhz bullThis microprocessor was used on the worlds firs personal computer named Altair bullAlso at this time IBM started researching for their microprocessor called POWER (Performance Optimization With Enhanced RISC)
12 Microprocessor architecture
Control Unit Arithmetic Logic Unit Registers Accumulator Flags Program Counter (PC) Stack Pointer (SP) Instruction RegisterDecoder Memory Address Register General Purpose Registers Control Generator Register Selector Microprogramming
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
11 8085 PROCESSOR
bullThe first microprocessor was introduced in 1970 by Intel (named 4004)bull It ran at the speed of 108KHzbull Four years later Intel created the 8080 running at just over 2 Mhz bullThis microprocessor was used on the worlds firs personal computer named Altair bullAlso at this time IBM started researching for their microprocessor called POWER (Performance Optimization With Enhanced RISC)
12 Microprocessor architecture
Control Unit Arithmetic Logic Unit Registers Accumulator Flags Program Counter (PC) Stack Pointer (SP) Instruction RegisterDecoder Memory Address Register General Purpose Registers Control Generator Register Selector Microprogramming
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
12 Microprocessor architecture
Control Unit Arithmetic Logic Unit Registers Accumulator Flags Program Counter (PC) Stack Pointer (SP) Instruction RegisterDecoder Memory Address Register General Purpose Registers Control Generator Register Selector Microprogramming
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8085 ARCHITECTURE CONTD
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
13 INSTRUCTION SET
BASED ON FUNCTIONS
Data Transfer Instructions
Arithmetic Instructions
Logical Instructions
Branch Instructions
Machine Control
BASED ON LENGTH
One-word or 1-byte instructions
Two-word or 2-byte instructions
Three-word or 3-byte instructions
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8085 Instruction Set
The 8085 instructions can be classified as follows
Data transfer operations Between Registers Between Memory location and a Registers Direct write to a RegisterMemory Between IO device and Accumulator
Arithmetic operations (ADD SUB INR DCR)
Logic operations
Branching operations (JMP CALL RET)
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8085 Instruction Types
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8085 Instruction Types
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8085 Instruction Types
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
PIN DIAGRAM
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
15 ADDRESSING MODES
Implied Addressing
The addressing mode of certain instructions is implied by the instructionrsquos function For example the STC (set carry flag) instruction deals only with the carry flag the
DAA (decimal adjust accumulator) instruction deals with the accumulator Register Addressing
Quite a large set of instructions call for register addressing With these instructions specify one of the registers A through E H or L as well as the operation code With these instructions the accumulator is implied as a second operand For example the instruction CMP E may be interpreted as compare the contents of the E register with the contents of the accumulator
Most of the instructions that use register addressing deal with 8-bit values However a few of these instructions deal with 16-bit register pairs For example the PCHL instruction exchanges the contents of the program counter with the contents of the H and L registers
Immediate Addressing
Instructions that use immediate addressing have data assembled as a part of the instruction itself For example the instruction CPI C may be interpreted as lsquocompare the contents of the accumulator with the letter C When assembled this instruction has the hexadecimal value FE43 Hexadecimal 43 is the internal
representation for the letter C When this instruction is executed the processor fetches the first instruction byte and determines that it must fetch one more byte The processor fetches the next byte into one of its internal registers and then performs the compare operation
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
ADDRESSING MODES CONTDhellip
Direct AddressingJump instructions include a 16-bit address as part of the instruction For
example the instruction JMP 1000H causes a jump to the hexadecimal address 1000 by replacing the current contents of the program counter with the new value
1000H Instructions that include a direct address require three bytes of storage one for
the instruction code and two for the 16-bit address Register Indirect Addressing
Register indirect instructions reference memory via a register pair Thus the instruction MOV MC moves the contents of the C register into the memory
address stored in the H and L register pair The instruction LDAX B loads the accumulator with the byte of data specified by the address in the B and C register pair
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
UNIT- II
Intel 8086 microprocessor
Architecture
Signals
Instruction set
Addressing modes
Assembler directives
Assembly language programming
Procedures
Macros
Interrupts and interrupt service routines
BIOS Function Calls
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8086 ARCHITECTUREampPIN DIAGRAM
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8086 FEATURES
16-bit Arithmetic Logic Unit
16-bit data bus (8088 has 8-bit data bus)
20-bit address bus - 220 = 1048576 = 1 meg
The address refers to a byte in memory
In the 8088 these bytes come in on the 8-bit data bus In the 8086 bytes at
even addresses come in on the low half of the data bus (bits 0-7) and bytes at
odd addresses come in on the upper half of the data bus (bits 8-15)
The 8086 can read a 16-bit word at an even address in one operation and at an
odd address in two operations The 8088 needs two operations in either case
The least significant byte of a word on an 8086 family microprocessor is at the
lower address
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
16-bit Registers
CS
SS
DS
ES
Segment
BP
Index
SP
SI
DI
AH
BH
CH
DH DL
CL
BL
AL
General Purpose
Status and Control
Flags
IP
AX
BX
CX
DX
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8086 ARCHITECTURE
The 8086 has two parts the Bus Interface Unit (BIU) and
the Execution Unit (EU)
The BIU fetches instructions reads and writes data and computes the 20-bit address
The EU decodes and executes the instructions using the 16-bit ALU
The BIU contains the following registers
IP - the Instruction PointerCS - the Code Segment RegisterDS - the Data Segment RegisterSS - the Stack Segment RegisterES - the Extra Segment Register
The BIU fetches instructions using the CS and IP written CSIP to contract the 20-bit address Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
INTERNAL BLOCK
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
PROGRAM MODEL
8086 Programmerrsquos Model
ESCSSSDSIP
AHBHCHDH
ALBLCLDL
SPBP
SIDI
FLAGS
AXBX
CX
DX
Extra SegmentCode Segment
Stack SegmentData SegmentInstruction Pointer
Accumulator
Base RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register
BIU registers
(20 bit adder)
EU registers
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
808688 internal registers 16 bits (2 bytes each)
AX BX CX and DX are twobytes wide and each byte can
be accessed separately
These registers are used as memory pointers
These registers are used as memory pointers
Flags will be discussed later
Segment registers are usedas base address for a segment
in the 1 M byte of memory
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
The 80868088 Microprocessors Registers
bull Registersndash Registers are in the CPU and are referred to by specific names
ndash Data registersbull Hold data for an operation to be performed
bull There are 4 data registers (AX BX CX DX)
ndash Address registersbull Hold the address of an instruction or data element
bull Segment registers (CS DS ES SS)
bull Pointer registers (SP BP IP)
bull Index registers (SI DI)
ndash Status registerbull Keeps the current status of the processor
bull On an IBM PC the status register is called the FLAGS register
ndash In total there are fourteen 16-bit registers in an 80868088
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Data Registers AX BX CX DX
bull Instructions execute faster if the data is in a register
bull AX BX CX DX are the data registers
bull Low and High bytes of the data registers can be accessed separatelyndash AH BH CH DH are the high bytes
ndash AL BL CL and DL are the low bytes
bull Data Registers are general purpose registers but they also perform special functions
bull AX ndash Accumulator Register
ndash Preferred register to use in arithmetic logic and data transfer instructions because it generates the shortest Machine Language Code
ndash Must be used in multiplication and division operations
ndash Must also be used in IO operations
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
bull BXndash Base Register
ndash Also serves as an address register
ndash Used in array operations
ndash Used in Table Lookup operations (XLAT)
bull CXndash Count register
ndash Used as a loop counter
ndash Used in shift and rotate operations
bull DXndash Data register
ndash Used in multiplication and division
ndash Also used in IO operations
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Pointer and Index Registers
bull Contain the offset addresses of memory locations
bull Can also be used in arithmetic and other operations
bull SP Stack pointer ndash Used with SS to access the stack segment
bull BP Base Pointerndash Primarily used to access data on the stack
ndash Can be used to access data in other segments
bull SI Source Index registerndash is required for some string operations
ndash When string operations are performed the SI register points to memory locations in the data segment which is addressed by the DS register Thus SI is associated with the DS in string operations
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
bull DI Destination Index register ndash is also required for some string operations
ndash When string operations are performed the DI register points to memory locations in the data segment which is addressed by the ES register Thus DI is associated with the ES in string
operationsbull The SI and the DI registers may also be used to access data
stored in arrays
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Segment Registers - CS DS SS and ES
bull Are Address registers
bull Store the memory addresses of instructions and data
bull Memory Organizationndash Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1
meg of addressable memory
ndash Addresses are expressed as 5 hex digits from 00000 - FFFFF
ndash Problem But 20 bit addresses are TOO BIG to fit in 16 bit registers
ndash Solution Memory Segmentbull Block of 64K (65536) consecutive memory bytes
bull A segment number is a 16 bit number
bull Segment numbers range from 0000 to FFFF
bull Within a segment a particular memory location is specified with an offset
bull An offset also ranges from 0000 to FFFF
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Segmented Memory
Segmented memory addressing absolute (linear) address is a combination of a 16-bit segment value added to a 16-bit offset
li ne
ar a
ddre
sse
s
one segment
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Memory Address GenerationMemory Address Generation
bull The BIU has a dedicated adder for determining physical memory addresses
Intel
Physical Address (20 Bits)
Adder
Segment Register (16 bits) 0 0 0 0
Offset Value (16 bits)
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Example Address CalculationExample Address Calculation
bull If the data segment starts at location 1000h and a data reference contains the address 29h where is the actual data
Intel
Offset 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
2 9
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Segment
0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1Address
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
SEGMENTOFFSET ADDRESS
bull Logical Address is specified as segmentoffset
bull Physical address is obtained by shifting the segment address 4 bits to the left and adding the offset address
bull Thus the physical address of the logical address A4FB4872 is A4FB0
+ 4872
A9822
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
EXAMPLE
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Segment Register
Offset
Physical orAbsolute Address
CSIP = 40056Logical Address
0H
0FFFFFH
Memory0
+
CS
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
The offset is the distance in bytes from the start of the segmentThe offset is given by the IP for the Code SegmentInstructions are always fetched with using the CS register
The physical address is also called the absolute address
THE CODE SEGMENT
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
THE DATA SEGMENT
Data is usually fetched with respect to the DS registerThe effective address (EA) is the offsetThe EA depends on the addressing mode
Memory
Segment Register
Offset
Physical Address
+
DS
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DSEA
0H
0FFFFFH
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
THE STACK SEGMENT
Segment Register
Offset
Physical Address
Memory
+
SS
SP
0A00
0100
0A000H
0A100H
0A00 0
0100
0A100H
The stack is always referenced with respect to the stack segment registerThe stack grows toward decreasing memory locationsThe SP points to the last or top item on the stack
PUSH - pre-decrement the SPPOP - post-increment the SP
The offset is given by the SP register
SSSP
0H
0FFFFFH
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Carry flag
Parity flag
Auxiliary flag
Zero
Overflow
Direction
Interrupt enable
Trap
Sign6 are status flags3 are control flag
Flags
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
bull CF (carry) Contains carry from leftmost bit following arithmetic also contains last bit from a shift or rotate operation
Flag Register
Flag O D I T S Z A P C
Bit no 15 14 13 12 1110
9 8 7 6 5 4 3 2 1 0
bull Conditional flags
ndash They are set according to some results of arithmetic operation You do not need to alter the value yourself
bull Control flags
ndash Used to control some operations of the MPU These flags are to be set
by you in order to achieve some specific purposes
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Flag Register
OF (overflow) Indicates overflow of the leftmost bit during arithmetic
DF (direction) Indicates left or right for moving or comparing string data
IF (interrupt) Indicates whether external interrupts are being processed or
ignored
TF (trap) Permits operation of the processor in single step mode
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero
(1=yes)
AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic
PF (parity) Indicates the number of 1 bits that result from an operation
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Macros
avoid repetitious SAS code
create generalizable and flexible SAS code
pass information from one part of a SAS job to another
conditionally execute data steps and PROCs
dynamically create code at execution time
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Example
Simple macro variable
let dsn=LAB
title DATA SET ampdsn
proc contents data=ampdsn
run
proc print data=ampdsn(obs=10)
run
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Procedures
Initial call to run an external program
Run a LCA model to simulate data
Estimate a model of simulated data
Collect necessary output
Check if output read is indeed output wanted
Collect output in a single data matrix
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Instruction Set
Mov destination source
add inc dec and sub instructions
InputOutput
String Instructions
Machine Control
Flag Manipulation
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Addressing Modes
Immediate addressing
Register addressing
Direct addressing
Indirect addressing
Implied addressing
Indexed addressing
Relative addressing
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Interrupts ampInterrupt Service Routine
An interrupt signals the processor to suspend its current activity (ie running your program) and to pass control to an interrupt service
program (ie part of the operating system)
A software interrupt is one generated by a program (as opposed to one generated by hardware)
The 8086 int instruction generates a software interrupt
It uses a single operand which is a number indicating which MSDOS subprogram is to be invoked
This subprogram handles a variety of IO operations by calling appropriate subprograms
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
MAXIMUM MODE
Maximum mode
Maximum mode is designed to be used with a coprocessor exists in the system
All the control signals (except RD) are not generated by the microprocessor
But we still need those control signals
Solution
8288
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8086 maximum amp minimum modes
8086 maximum amp minimum modes The mode is controlled by MNMX Maximum mode is obtained by connecting MNMX to low and
minimum mode is by connecting it to high Having two different modes (minimum and maximum) is used
only 80888086 Each mode enables a different control structure Minimum mode operation and control signals are very similar to
those of 8085 So 8085 8-bit peripherals can be used with 8086 without special
considerations Easy and least expensive way to build single processor systems
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
S2 S1 S0 operation signal
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read IO port IORC
0 1 0 Write IO port IOWC AIOWC
0 1 1 Halt none
1 0 0 Instruction Fetch MRDC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC AMWC
1 1 1 Passive none
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
UNIT III
Coprocessor Configuration
Closely Coupled Configuration
Loosely Coupled Configuration
8087 Numeric Data Processor-architecture
Data types
8089 IO Processor-Architecture
Communication between CPU and IOP
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
PIN DIAGRAM OF 8087
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Architecture of 8087
Two Units 1048729Control Unit 1048729Execution Unit
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Control Unit
1048729Control unit To synchronize the operation of the coprocessor and the processor 1048729This unit has a Control word and Status word and Data Buffer 1048729If instruction is an ESCape (coprocessor) instruction the coprocessor executes it if not the microprocessor executes 1048729Status register reflects the over all operation of the coprocessor
Status Register
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Status Register
C3-C0 Condition code bits TOP Top-of-stack (ST) ES Error summary PE Precision error UE Under flow error OE Overflow error ZE Zero error DE Denormalized error IE Invalid error B Busy bit1048729B-Busy bit indicates that coprocessor is busy executing a task Busy can be tested by examining the status
or by using the FWAIT instruction 1048729C3-C0 Condition code bits indicates conditions about the coprocessor1048729TOP- Top of the stack (ST) bit indicates the current register address as the top of the stack1048729ES-Error summary bit is set if any unmasked error bit (PE UE OE ZE DE or IE) is set In the 8087 the
error summary is also caused a coprocessor interrupt1048729PE- Precision error indicates that the result or operand executes selected precision1048729UE-Under flow error indicates the result is too large to be represent with the current precision selected by
the control word1048729OE-Over flow error indicates a result that is too large to be represented If this error is masked the
coprocessor generates infinity for an overflow error1048729ZE-A Zero error indicates the divisor was zero while the dividend is a non-infinity or non-zero number1048729DE-Denormalized error indicates at least one of the operand is denormalized1048729IE-Invalid error indicates a stack overflow or underflow indeterminate from (000-0
etc) or the use of a NAN as an operand This flag indicates error such as those producedby taking the square root of a negative number
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
CONTROL REGISTER
Control register selects precision rounding control infinity control It also masks an unmasks the exception bits that correspond to the rightmost Six bits of
status register Instruction FLDCW is used to load the value into the control register
IC Infinity control RC Rounding control PC Precision control PM Precision control UM Underflow mask OM Overflow mask ZM Division by zero mask DM Denormalized operand mask IM Invalid operand mask
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IC ndashInfinity control selects either affine or projective infinity Affine allows positive and negative infinity while projective assumes infinity is unsigned
INFINITY CONTROL0 = Projective1 = Affine
RC ndashRounding control determines the type of rounding ROUNDING CONTROL
00=Round to nearest or even01=Round down towards minus infinity10=Round up towards plus infinity11=Chop or truncate towards zero
PC- Precision control sets the precision of he result as define in table PRECISION CONTROL00=Single precision (short)01=Reserved10=Double precision (long)11=Extended precision (temporary) Exception Masks ndash It Determines whether the error indicated by the exception affectsthe error bit in the status register If a logic1 is placed in one of the exception control bitscorresponding status register bit is masked off
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Numeric Execution Unit
This performs all operations that access and manipulate the numeric data in thecoprocessorrsquos registers
Numeric registers in NUE are 80 bits wide NUE is able to perform arithmetic logical and transcendental operations as well as
supply a small number of mathematical constants from its on-chip ROM Numeric data is routed into two parts ways a 64 bit mantissa bus and
a 16 bit signexponent bus
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Data Types
Internally all data operands are converted to the 80-bit temporary real formatWe have 3 types Integer data type Packed BCD data type Real data typeExampleConverting a decimal number into a Floating-point number1) Converting the decimal number into binary form2) Normalize the binary number3) Calculate the biased exponent4) Store the number in the floating-point formatExample Step Result1) 100252) 110010001 = 110010001 263) 110+01111111=100001014 ) Sign = 0 Exponent =10000101 Significand = 10010001000000000000000 In step 3 the biased exponent is the exponent a 26 or 110plus a bias of 01111111(7FH)
single precision no use 7F and double precision no use 3FFFH IN step 4 the information found in prior step is combined to form the floating point no
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
UNIT V
Architecture of 8051 Signals Operational features Memory and IO addressing Interrupts Instruction set Applications
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
RAM ROM
IO Port
TimerSerial COM Port
Microcontroller
CPU
A smaller computer On-chip RAM ROM IO ports Example Motorolarsquos 6811 Intelrsquos 8051 Zilogrsquos Z8 and PIC 16X
A single chip
Microcontroller
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Microprocessor CPU is stand-alone RAM
ROM IO timer are separate designer can decide on the
amount of ROM RAM and IO ports
expansive versatility general-purpose
Microcontroller
bull CPU RAM ROM IO and timer are all on a single chip
bull fix amount of on-chip ROM RAM IO ports
bull for applications in which cost power and space are critical
bull single-purpose
Microprocessor vs Microcontroller
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 IO Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
TimerCounter
Bus Control
TxD RxDP0 P1 P2 P3
AddressData
Counter Inputs
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Pin Description of the 8051
1234567891011121314151617181920
4039383736353433323130292827262524232221
P10P11P12P13P14P15P16P17RST
(RXD)P30(TXD)P31
(T0)P34(T1)P35
XTAL2XTAL1
GND
(INT0)P32(INT1)P33
(RD)P37(WR)P36
VccP00(AD0)P01(AD1)P02(AD2)P03(AD3)P04(AD4)P05(AD5)P06(AD6)P07(AD7)EAVPPALEPROGPSENP27(A15)P26(A14)P25(A13)P24(A12)P23(A11)P22(A10)P21(A9)P20(A8)
8051(8031)
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Figure (b) Power-On RESET Circuit
30 pF
30 pF
82 K
10 uF+
Vcc
110592 MHz
EAVPPX1
X2
RST
31
19
18
9
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Port 0 with Pull-Up Resistors
P00P01P02P03P04P05P06P07
DS5000
8751
8951
Vcc10 K
Port 0
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Stack in the 8051
The register used to access the stack is called SP (stack pointer) register
The stack pointer in the 8051 is only 8 bits wide which means that it can take value 00 to FFH When 8051 powered up the SP register contains value 07
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Timer Timer
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Interrupt
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Numerical Bases Used in Programming
Hexadecimal
Binary
BCD
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Hexadecimal Basis
Hexadecimal Digits
1 2 3 4 5 6 7 8 9 A B C D E F
A=10 B=11 C=12 D=13 E=14 F=15
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Decimal Binary BCD amp Hexadecimal Numbers
(43)10=
(0100 0011)BCD=
( 0010 1011 )2 =
( 2 B )16
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Register Addressing Mode
MOV Rn A n=07
ADD A Rn
MOV DPL R6
MOV DPTR A
MOV Rm Rn
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Direct Addressing Mode
Although the entire of 128 bytes of RAM can be accessed using direct addressing mode it is most often used to access RAM loc 30 ndash 7FH
MOV R0 40HMOV 56H AMOV A 4 equiv MOV A R4MOV 6 2 copy R2 to R6
MOV R6R2 is invalid
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Immediate Addressing Mode
MOV A65H
MOV R665H
MOV DPTR2343H
MOV P165H
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
SETB bit bit=1CLR bit bit=0
SETB C CY=1SETB P00 bit 0 from port 0 =1SETB P37 bit 7 from port 3 =1SETB ACC2 bit 2 from ACCUMULATOR =1SETB 05 set high D5 of RAM loc 20h
Note
CLR instruction is as same as SETBie
CLR C CY=0
But following instruction is only for CLRCLR A A=0
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
DEC byte byte=byte-1
INC byte byte=byte+1
INC R7
DEC A
DEC 40H [40]=[40]-1
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
LOOP and JUMP Instructions
JZ Jump if A=0
JNZ Jump if A=0
DJNZ Decrement and jump if A=0
CJNE Abyte Jump if A=byte
CJNE regdata Jump if byte=data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Conditional Jumps
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Call instruction
SETB P00CALL UPCLR P00RET
UP
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
UNIT IV
Memory Interfacing and IO interfacing Parallel communication interface Serial communication interface Timer Keyboard display controller Interrupt controller DMA controller
Programming and applications
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Accessing IO Devices
IO address mapping Memory-mapped IO
Reading and writing are similar to memory readwrite
Uses same memory read and write signals Most processors use this IO mapping
Isolated IO Separate IO address space Separate IO read and write signals are needed Pentium supports isolated IO
64 KB address space Can be any combination of 8- 16- and 32-bit IO ports
Also supports memory-mapped IO
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Accessing IO Devices (contrsquod)
Accessing IO ports in Pentium Register IO instructions
in accumulator port8 direct format Useful to access first 256 ports
in accumulatorDX indirect format DX gives the port address
Block IO instructions ins and outs
Both take no operands---as in string instructions ins port address in DX memory address in ES(E)DI outs port address in DX memory address in ES
(E)SI We can use rep prefix for block transfer of data
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
An Example IO Device
Keyboard Keyboard controller scans and reports
Key depressions and releases
Supplies key identity as a scan code Scan code is like a sequence number of the key
Keyrsquos scan code depends on its position on the keyboard
No relation to the ASCII value of the key
Interfaced through an 8-bit parallel IO port Originally supported by 8255 programmable
peripheral interface chip (PPI)
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
An Example IO Device (contrsquod)
8255 PPI has three 8-bit registers Port A (PA) Port B (PB) Port C (PC)
These ports are mapped as follows8255 register Port address
PA (input port) 60H
PB (output port) 61H
PC (input port) 62H
Command register 63H
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
An Example IO Device (contrsquod)
Mapping of 8255 IO ports
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
An Example IO Device (contrsquod)
Mapping IO ports is similar to mapping memory Partial mapping Full mapping
See our discussion in Chapter 16
Keyboard scan code and status can be read from port 60H 7-bit scan code is available from
PA0 ndash PA6 Key status is available from PA7
PA7 = 0 ndash key depressed PA0 = 1 ndash key released
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer
Data transfer involves two phases A data transfer phase
It can be done either by Programmed IO DMA
An end-notification phase Programmed IO Interrupt
Three basic techniques Programmed IO DMA Interrupt-driven IO (discussed in Chapter 20)
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
Programmed IO Done by busy-waiting
This process is called polling
Example Reading a key from the keyboard involves
Waiting for PA7 bit to go low Indicates that a key is pressed
Reading the key scan code Translating it to the ASCII value Waiting until the key is released
Program 191 uses this process to read input from the keyboard
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
Direct memory access (DMA) Problems with programmed IO
Processor wastes time polling In our example
Waiting for a key to be pressed Waiting for it to be released
May not satisfy timing constraints associated with some devices
Disk read or write
DMA Frees the processor of the data transfer
responsibility
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
DMA is implemented using a DMA controller DMA controller
Acts as slave to processor
Receives instructions from processor
Example Reading from an IO device Processor gives details to the DMA controller
IO device number
Main memory buffer address
Number of bytes to transfer
Direction of transfer (memory IO device or vice versa)
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
Steps in a DMA operation Processor initiates the DMA controller
Gives device number memory buffer pointer hellip Called channel initialization
Once initialized it is ready for data transfer When ready IO device informs the DMA
controller DMA controller starts the data transfer process
Obtains bus by going through bus arbitration Places memory address and appropriate control signals Completes transfer and releases the bus Updates memory address and count value If more to read loops back to repeat the process
Notify the processor when done Typically uses an interrupt
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
DMA controller details
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
DMA transfer timing
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
8237 DMA controller
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod)
8237 supports four DMA channels It has the following internal registers
Current address register One 16-bit register for each channel Holds address for the current DMA transfer
Current word register Keeps the byte count Generates terminal count (TC) signal when the count goes from
zero to FFFFH Command register
Used to program 8257 (type of priority hellip)
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Data Transfer (contrsquod) Mode register
Each channel can be programmed to Read or write Autoincrement or autodecrement the address Autoinitialize the channel
Request register For software-initiated DMA
Mask register Used to disable a specific channel
Status register Temporary register
Used for memory-to-memory transfers
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
What is a Timer
A device that uses high speed clock input to provide a series of time or count-related events
divide 000000
0x1206
IO Control
Clock Divider
Counter Register
Reload on Zero
Countdown Register
Interrupt to Processor
System Clock
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Inside the Timer
High Byte Low ByteCounter Register at offsets 0x04 0x00 (write only)
Current Counter (not directly readable by software)
GO Register offset 0x08 immediately moves Counter Reg value into Current Counter
Latch Register offset 0x0C write a ``1 to immediately write Current Counter value to readable Latch Reg
Latched Counter at offsets 0x04 0x00 (read only)
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Setting the Timers Counter Registers
Counter is usually programmed to reach zero X times per second To program the timer to reach zero 100 times per second Example For a 2 MHz-based timer 2MHz 100 = 20000
define TIMER1 0x10200050
int time
time = 2000000 100
timer = (timer_p) TIMER1
timer gtcountLow = (unsigned char) (time amp 0xff)
timer gtcountHigh = (unsigned char) ((time gt 8) amp 0xff)
timer gtgo = (unsigned char) 0x1
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Interrupt vs Polled IO
Polled IO requires the CPU to ask a device (eg toggle switches) if the device requires servicing
For example if the toggle switches have changed position Software plans for polling the devices and is written to know when a device will be
serviced Interrupt IO allows the device to interrupt the processor announcing that the device
requires attention This allows the CPU to ignore devices unless they request servicing (via interrupts) Software cannot plan for an interrupt because interrupts can happen at any time
therefore software has no idea when an interrupt will occur This makes it more difficult to write code
Processors can be programmed to ignore interrupts We call this masking of interrupts Different types of interrupts can be masked (IRQ vs FIQ)
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IRQ and FIQ
Program Status Register
To disable interrupts set the corresponding ldquoFrdquo or ldquoIrdquo bit to 1 On interrupt processor switches to FIQ32_mode registers or IRQ32_mode
registers On any interrupt (or) Switch register banks
Copy PC and CPSR to R14 and SPSR Change new CPSR mode bits SWI Trap
N31 30 29 28 27 hellip 8 7 6 5 4 3 2 1 0
Z C V I F M4 M3 M2 M1 M0
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
INTERFACING
Static RAM interfacing Procedure Configuration Dynamic RAM interfacing
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
IO Port Interfacing
Steps in Interfacing Methods of interfacing
a) IO Mapped
b) Memory Mapped
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
PIO 8255
Programmable input output Port Architecture Signals Modes Of Operationa) BSR Modeb) IO Modesi) Mode 0(Basic IO Mode)ii) Mode 1 (Strobed IO Mode)iii) Mode 2 (Strobed Bidirectional Mode)
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Controller 8259
Programmable Interrupt Controller Architecture and Signal Descriptions Interrupt Sequence Command worda) Initialization Command word (ICWs)b) Operation Command wordsModes of operation1Nested mode2Fully Nested Mode3Poll modeAutomatic EOI Mode
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
Display Controller 8279
Output Mode
1)Display Scan
2) Display EntryCommand words
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
8251 USART
Methods of Data communication
a) Simplex
b) Duplex
c) Half Duplex Architecture Control Word
a) Mode Instruction control word
b) Command instruction control word
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
TEXT BOOKS
Ramesh SGaonkar ldquoMicroprocessor - Architecture Programming
and Applications with the 8085rdquo Penram International publishing
private limited fifth edition
(UNIT-1 ndash Chapters 356 and programming examples from
chapters 7-10)
AK Ray amp KMBhurchandi ldquoAdvanced Microprocessors and
peripherals- Architectures Programming and Interfacingrdquo TMH
2002 reprint (UNITS 2 to 5 ndash Chapters 1-6 71-73 8 16)
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004
REFERENCES
Douglas VHall ldquoMicroprocessors and Interfacing Programming and
Hardwarerdquo TMH Third edition
Yu-cheng Liu Glenn AGibson ldquoMicrocomputer systems The 8086 8088
Family architecture Programming and Designrdquo PHI 2003
Mohamed Ali Mazidi Janice Gillispie Mazidi ldquoThe 8051 microcontroller and
embedded systemsrdquo Pearson education 2004