cs311-computer organizationmemory systemlecture 5 -1 lecture 5 storage system

CS311-Computer Organization Memory System Lecture 5 -1

Lecture 5Lecture 5

Storage SystemStorage SystemLecture 5Lecture 5

Storage SystemStorage System


Lecture 5: Lecture 5: Memory SystemMemory System

Lecture 5: Lecture 5: Memory SystemMemory System

In this lecture, we will study• Storage Hierarchy

• Main Memory – Main memory cell

» Static Cell and Dynamic Cell– RAM

» Organization of RAM chip» Construction Main Memory using RAM chips» Dynamic RAM and Refreshing

– Main Memory Timing Parameters

• Memory Bus Architectures– System Bus(single bus) architecture– 2-Bus architecture– Memory Bus and Multiple I/O Bus architecture


In this lecture, we will study(Continue)• Auxiliary Storage

– Magnetic Tape– Disk

» Moving Head Disk» Fixed Head Disk

• Characteristics of Storage• Main Memory Addressing

– Address Space and Storage Space– Method of accessing method using address– Method of representing address– Method of mapping address to the storage space– Precision of address

• Addressing patterns of programs

Lecture 5:Lecture 5:Memory SystemMemory System

Lecture 5:Lecture 5:Memory SystemMemory System


Memory SystemMemory SystemMemory SystemMemory System

• Storage Access Time and Storage Capacity have been the major limitations of the hardware resource to the programmers• Thus when you design a storage system, Time and Space must be traded off– If you need a very fast storage access time, you should have a

large capacity main memory by sacrificing the storage capacity– If you need a very large storage capacity, you should have the

secondary storage by sacrificing the storage access time


2 Types of Storage Systems2 Types of Storage Systems2 Types of Storage Systems2 Types of Storage Systems

• System with a Single Storage System– Main Memory only

– Embedded computers for simple applications

• System with Hierarchical Storage System– Conventional system with Primary Memory and Secondary

Storage

– Primary Memory» Random Accessible(addressable) » Relatively small capacity

– Secondary Storage(Auxiliary Storage)» Access through I/O class instructions via I/O bus or channel» Slower and cheaper than main memory


Storage HierarchyStorage HierarchyStorage HierarchyStorage Hierarchy

Storage Hierarchy– Different storage M1, M2, … , MS, with different characteristics

Storage Capacity Access Time Cost M1 S1 t1 C1 M2 S2 t2 C2

… … … …

MS SS tS CS – Storage Hierarchy provides;

» Capacity: MS (Capacity = Capacity of the lowest level storage)» Access Time: t1 (AT= AT of the highest level storage) » Cost: CS (Cost= Cost of the lowest level storage)

e.g. M1- M2- M3 = Cache - Main Memory – Disk hierarchy Capacity = Capacity of the Disk Access Time = Access time of the Cache Cost = Cost of the Disk

S1<S2<…<ss

t1<t2<…<ts

C1>C2>…>Cs


Memory AccessMemory AccessMemory AccessMemory Access

• Two Registers are needed in CPU for memory access– MAR(Memory Address Register)

» A register that needs to be stored with address by CPU for memory access– MBR(Memory Buffer Register or Memory Data Register)

» A register that stores data for memory access» For Read access, memory puts the data read from memory» For Write access, CPU puts the data to be stored in memory

• Read Access– CPU stores address into MAR and the CU sends Read control signal to Memory– Memory puts the data read from memory into MBR– Read data appears in MBR after the memory access time

• Write Access– CPU stores address in MAR and data in MBR and CU sends Write control signal

to Memory – Storing data completes after the memory cycle time


Memory Access Time/Cycle TimeMemory Access Time/Cycle TimeMemory Access Time/Cycle TimeMemory Access Time/Cycle Time

• Cycle Time– Time from a memory access to the next memory access

• Access Time– Time from sending an address and Read control signal to the

memory to the time when the read data is available

Access Time

Cycle Time

Send address(MAR)

RSend address for the next access

t

Read dataavailableMBR


Main Memory Timing Main Memory Timing ParametersParameters

Main Memory Timing Main Memory Timing ParametersParameters

2 different accesses;– Read Access

– Write Access

2 different timing parameters;– Access Time From

the time when address and control signal R is applied to the time when the data is in MBR.

Represents the time when the read data is available.

– Cycle Time From the time when address and control signal R is applied to the time when the next address and control signal R can be applied.

Represents how often memory can be accessed.

In generalAccess Time < Cycle Time

MAR addressApply R(read) control signal to MMBR data

MAR addressMBR dataApply W(write) control signal to M


Main MemoryMain MemoryMain MemoryMain Memory

Main Memory• Only Storage that CPU can directly access• Random Access Memory

– Random Access Memory is accessed by using Address– Each location in which a unit of information can be stored is

assigned a unique address– Address is used to access a unit of information at the desired

location– Access time is constant, i.e., independent of memory location

or address» Memory Access

• Read Access • Write Access


Main Memory OrganizationMain Memory OrganizationMain Memory OrganizationMain Memory Organization

• Memory Cell• Memory Word(or Byte)• Block(or Page or Segment)• RAM Chip

Memory System

Memory Bank

...

Memory Bank

RAM RAM … … RAM RAM

• Memory Module• Memory Bank• Memory System

Memory Module Memory Module

...

RAM RAM … … RAM RAM

Memory Module Memory Module

...


Time OutTime OutTime OutTime Out

• 매일 매일 일 때문에 바쁘게 살아가는 부부가 있었다 .

• 큰 아들이 신병훈련을 마치고 퇴소식을 갖게 되었으므로 부부는 그 식에 참석하러 가기로 했다 .

• 그들은 이 번 여행을 그들 둘만의 특별한 여행으로 만들고 싶었다 .

• 그들은 아들과 헤어진 후 five star 호텔에 투숙해서 호화판 저녁식사를 하며 즐겁게 보낸 다음 호텔 방으로 올라갔다 .

• 약 15 분쯤 지나서 누가 방문을 두드렸다 . 방문을 열어보니 아들이 환하게 웃으며 서 있었다 .

• “ 어머니 오늘 저녁을 어머니 아버지와 함께 지내려고 왔어요 !”


Model of a Memory CellModel of a Memory CellModel of a Memory CellModel of a Memory Cell

S Q SRFR Q’

DI

R(1: Read, 0: Write)(control signal)

DO

SEL(address bit)

SEL

DODI

R

cell

For an Access:SEL=1

Read: SEL . RWrite: SEL . R’


SRAM - Static Memory ChipSRAM - Static Memory ChipSRAM - Static Memory ChipSRAM - Static Memory Chip

Static RAM - SRAM– Preserve stored information as long as the power is on:

Access Time and Cycle Time are approximately equal

– Current demand is steady -> low cost power supply is OK

– A cell is made of several transistors, thus chip density is lower than DRAM

– Chip is organized in the form of (n x m)-bit(cell)

» Allows to access m bits(usually m=8, a byte) in one access

– Faster access time and more expensive than DRAM - For small quantity applications, SRAM pays off


DRAM - Dynamic Memory ChipDRAM - Dynamic Memory ChipDRAM - Dynamic Memory ChipDRAM - Dynamic Memory Chip

Dynamic Cell - DRAM– Information is stored in the form of charge, thus, stored

information is discharged as the time elapses even if power is on– Made of a single transistor, thus chip density is higher than SRAM– To preserve the stored information, needs periodic refresh,

Refresh Cycle (2mSec)» Peak load for current » Usually refresh logic is provided on the chip» Access Time < Cycle Time

– Chip is organized in the form of (n x 1)-bit» Allows to access 1 bit per access

– Much slower access time than SRAM» For large capacity applications, DRAM pays off


DRAM - RefreshDRAM - RefreshDRAM - RefreshDRAM - Refresh

Refresh Operation[1] All the cells in a selected row are read to the particular

cells, one for each column in an extra row

[2] From this extra row, cells in the selected row are recharged

CellArray

Refresh Buffer

...

• Refresh by 1 row at a time, all the cells in a row together1 refresh operation requires the Row Addressm rows require m refresh operations

• Refresh CounterProvides a Row Address for a refresh operationCounter advances for the next row address to refresh


Refresh MethodsRefresh MethodsRefresh MethodsRefresh Methods

Refresh Methods

Transparent1/2 of memory cycles to CPU and I/O and 1/2 for refresh

Cycle StealA Time-out signal generates a cycle steal request at the period of (Refresh Cycle Time / Number of row) to refresh a row

BurstRefresh request is made in every refresh cycle to refresh all rows, one row by one in succession


Cell Layout in RAMCell Layout in RAMCell Layout in RAMCell Layout in RAM

Square layout of cells - Accommodate largest

number of cells in the same chip area

- e.g. 64 x 64 layout


(8 x 8) RAM Chip Organization(8 x 8) RAM Chip Organization(8 x 8) RAM Chip Organization(8 x 8) RAM Chip Organization

DI0 DI1 DI2 . . . DI7

DO0 DO1 DO2 . . . DO3

a0

a1

a2

CSR/W8 x 8

0,0 0,1 0,2 0,7

1,0 1,1 1,2 1,7

2,0

7,0

2,1 2,2 2,7

7,1 7,2 7,7

a0

a1

a2

...

Ad

dre

ss

Ad

dre

ss D

ecod

er

0

1

2

7

DI0 DI1 DI2 . . . DI8

Write Amplifier . . .

ChipSelect

CSRead Buffer/Sense Amplifier . . .

DO0 DO1 DO2 DO7

R/W

SELDI DO

R


Construction of Memory Construction of Memory with RAMwith RAM

Construction of Memory Construction of Memory with RAMwith RAM

e.g. Construction of (1K × 32) Memory– (8 × 8) RAM Chips

1024/8 × x 32/8 = 128 × 4 = 512

– (64 × 1) RAM Chips – 1024/64 × 32/1 = 16 × 32 = 512

(n × m) Memory using (p × q) RAM– Number of chips to get m-bit word = m/q– Number of chips to get n words = n/p– Number of chips to get (n x m) memory = n/p × m/q


(16 x 16) Memory (16 x 16) Memory Using (8 x 8) RAM Using (8 x 8) RAM (16 x 16) Memory (16 x 16) Memory Using (8 x 8) RAM Using (8 x 8) RAM

. . .

. . .

DI’s

DO’s

CSR/W

a0

a1

a2

U0

Control Bus(R/W)

Address Bus (a0a1a2)Address Bus (a3)

Data Bus (d8 ~ d15)Data Bus (d0 ~ d7)

Mem

ory

Bu

sDI’s

DO’s

CSR/W

a0

a1

a2

U1DI’s DI’s

DO’s

CSR/W

a0

a1

a2

U3

DI’sDI’sa0

a1

a2DO’s

CSR/W

U2DI’sa0

a1

a2

. . . . . . . . .

. . . . . . . . .


Refreshing DRAM:Refreshing DRAM:

Refresh Counter Refresh CounterRefreshing DRAM:Refreshing DRAM:

Refresh Counter Refresh Counter

a0 a1 a2 a3 a4

A0 A1 A2 A3 A4

A0

A1

A2

A3

A4

Refresh

To memory

32 x 32 DRAM array


Memory Bus ArchitectureMemory Bus ArchitectureMemory Bus ArchitectureMemory Bus Architecture

System BusSystem Bus - Simple single bus

. . .

MainMemory

CPU I/O I/O

System Bus

– Most often found in low cost PCs– Single bus prevents concurrent data transfers– CPU communicates with and controls I/O devices as it

accesses memory – Both roles of memory and I/O buses, value on the

address bus determines role of the bus


2-Bus Architecture2-Bus Architecture2-Bus Architecture2-Bus Architecture

– CPU communicates with I/O over I/O Bus– CPU and DMA Controller access memory over Memory Bus– Permits high speed Memory Bus with short interconnection length– I/O data and I/O address bus width can be narrower than Memory

Bus– Multi-port memory has internal scheme which handles and

coordinates each port

MainMemory

CPU

I/OController(DMAC)

I/ODevice

I/ODevice

...

Mem

ory B

us

I/O

Bu

s


Memory Bus/Multiple I/O Memory Bus/Multiple I/O Bus ArchitectureBus Architecture

Memory Bus/Multiple I/O Memory Bus/Multiple I/O Bus ArchitectureBus Architecture

– CPU, I/O Channels, and Memory communicate over Memory Bus– Several channels can be active at the same time– I/O channel multiplexes slower devices

MainMemory

CPU

I/OChannel

I/OChannel

...

To I/O Controllers and/or Adapters

Memory Bus


Oak Valley resort in Fall


Auxiliary StorageAuxiliary Storage


Auxiliary StorageAuxiliary StorageAuxiliary StorageAuxiliary Storage

• Sequential Access Storage Device(SASD)

– Magnetic Tapes

» Reel Tape

» Cassette, cartridge

• Direct Access Storage Device(DASD)

– Magnetic Disks

» Moving head disk - Diskette

» Fixed head disk - Hard disk


Storage Organization– Store Files, separated by EOF– Files consist of Blocks, separated by IRG(inter-record gap)– Blocks contain Records, a basic information unit

Tape Access - to read record R4 in Filei

– Read in forward direction until EOF of Filei-1

– Continue read in forward direction Until the first IRG

– Continue read– Sequential Access

Magnetic TapeMagnetic TapeMagnetic TapeMagnetic Tape

File i

block block block

R1 R2 R3 R4 R5

IRG EOF


Magnetic DiskMagnetic DiskMagnetic DiskMagnetic Disk

Sector m Sector 0

Track 0Track 1

Track m

Moving Head Disk

Cylinder

Track

Surface

Fixed Head Disk

Tracks


AddressDrive No. / Surface No. / Track(Cylinder) No. / Sector No.

Random Accessible Storage

Access Time– Seek Time consists of

» Time to position the read/write head to the desired track» Intra-Cylinder access does not need seek time

» Fixed Head Disk does not have seek time unless current access requires to access from the different disk drive

– Head Switching Time» Time to activate a head when the head used for the last access is

different from the one that is going to be used for the current access» Both Moving and Fixed Head Disk require head switching time

Magnetic DiskMagnetic DiskMagnetic DiskMagnetic Disk


Access Characteristics Access Characteristics of Storage Systemsof Storage Systems

Access Characteristics Access Characteristics of Storage Systemsof Storage Systems

Distance of Storage Locations

Access

Tim

e

RAMDASDSASD

Seek Time


Memory BandwidthMemory BandwidthMemory BandwidthMemory Bandwidth

Memory

CPUDASD

orSASD

I/ODev

I/ODev...

Memory Bus

Use of Memory Bandwidth

CPU - Read Instructions from memory Read Operands from memory Store Results to memory

I/O - Initially read Program and Data from input device to memory before running

- (Read Operands from input device to Memory for processing) - Write the Results of execution of the program to the output

device

CPU and I/O device(s) are competing to use memory bus, causing a Bottleneck at the Memory Bus


AddressAddressAddressAddress

• Address– Assigned to each stored object to retrieve the object later via its

address

– Eventually needed to be mapped onto a physical memory location

– In most current systems, an Address and a Memory Location are distinct concepts related by the Mapping Function

– 1-1 mapping implies that the an address and the memory location are referred to synonymously

• Address Space

MappingFunctionMappingFunction

Address Space Memory Space

Addresses visibleto programmers

StorageLocations


Address Design ConsiderationsAddress Design ConsiderationsAddress Design ConsiderationsAddress Design Considerations

• Efficient Specifications of addresses• Independence of Address Space• Services to users


Address Design Considerations:Address Design Considerations:

Address Specification EfficiencyAddress Specification EfficiencyAddress Design Considerations:Address Design Considerations:

Address Specification EfficiencyAddress Specification Efficiency

– Space considerations» Minimize the umber of bits to specify address in an instruction

» Minimize the size of mapping tables, descriptors, etc

– Time considerations» Minimize time to retrieve an operand, and update the address s

tructure

» Minimize the time for automatic generation of addresses by compiler



Independence of Address SpaceIndependence of Address SpaceAddress Design Considerations:Address Design Considerations:

Independence of Address SpaceIndependence of Address Space

– Relocatability» Speedy relocation of user jobs in Multiprogramming enviro

nment

» Make the garbage collection fast

– Portability» By uncoupling the address space from memory space pro

gram for one computer can be run in different computers


MultiprogrammingMultiprogrammingMultiprogrammingMultiprogramming

• CPU is the most expensive hardware resource– With respect to Memory, Secondary storage(such as disks),

I/O

• We would like to keep the CPU busy all the time• What makes CPU from busy all the time?

– Mainly I/O operations including disk accesses

• What can we do about it so that the expensive CPU time cannot be wasted?– Provide more jobs, i.e., have multiple of programs in the

memory which are ready to be executed

– When the execution of one job causes CPU idle, immediately initiate another job ready to be executed in the memory


MultiprogrammingMultiprogrammingMultiprogrammingMultiprogramming

Job 1 Job 2 Job 3 Job4 Job 5

WaitingJob

WaitingJob

WaitingJob

Job4Job 3Job 3


Multiprogramming:Multiprogramming:

RelocationRelocationMultiprogramming:Multiprogramming:

RelocationRelocation

Job 1 Job 2 Job 3 Job4 Job 5Job4Waiting

Job

WaitingJob



RelocationRelocationMultiprogramming:Multiprogramming:

RelocationRelocation


WaitingJob

Job4

WaitingJob

Job4



Garbage CollectionGarbage CollectionMultiprogramming:Multiprogramming:

Garbage CollectionGarbage Collection


Job7Job 6

Job 2 Job 3 Job4 Job 5

Job 8

Job 8



Services to UsersServices to UsersAddress Design Considerations:Address Design Considerations:

Services to UsersServices to Users

– Provide illusion of much larger memory than the actual

» virtual storage

– Provide Protection and Sharing for Multiprogramming

SharedRoutine

Referencethat needsprotection;• Security • Privacy

job1

Job3(currently running)

job4

job2

Sub A

job1

Job3(currently running)

job4

job2

Sub A

Sub A

Sub A


Time Out Time Out Time Out Time Out

• 오래 전부터 사업상 알고 지내는 두 남자가 함께 거리를 걸어가던 중 한 남자가 당황해 하며 말했다 .

• “ 야단났네 , 내 마누라가 내 정부와 함께 이리로 오고 있어 .”

• “ 어이쿠 !” 다른 남자가 말했다 . “ 내 마누라와 정부도 함께 이리로 오고 있는데 .”


Basic Addressing ModesBasic Addressing ModesBasic Addressing ModesBasic Addressing Modes

OP-code Ri Rx X Ri: Arbitrary address registerRx: Index RegisterRb: Base Address Register

Register Direct [Ri]

Modes Operand

Immediate X

Memory Indirect M[M[X]]

Direct M[X]Register Indirect M[[Ri]]

Base + Displacement M[[Rb] + X]Indexed; M[X + [Rx]];

Auto-increment [Rx] [Rx]+1Auto-decrement [Rx] [Rx]-1

Base + Index M[[Rb] + [Rx] + X] Register-Memory Indirect M[M[[Ri]]]


Properties of address:Properties of address:

Operand Access Method from the Operand Access Method from the Specified AddressSpecified Address


Operand Access Method from the Operand Access Method from the Specified AddressSpecified Address

• Direct Address: ADD X (EFA=X; AC <= AC+M[X] )

– 1 memory access per operand– Consumes a lot of instruction bits for a direct address

• Indirect Address ADD @X (EFA=M[X]; AC <= AC+M[M[X]] )

– At least 2 memory accesses per operand – Indirect by a bit flag(if MSB of the accessed address is 1 then further indirect) – Register indirection : 1 memory + 1 reg accesses per operand access

• Calculated Address ADD $X (EFA=M[X+[R]]; AC <= AC+M[X+[R]])

– 1 memory access + 1 register access plus calculation per operand– Little shorter than direct address --> saves instruction bits

• Immediate Address ADD #X (EFA=na; AC <= AC+X)

– No memory access for operand– Consumes a lot of instruction bits


ExampleExampleExampleExample

ADD 100Make an addition of the number 50 stored in AC(data register in CPU) and the operand obtained using 100.Assume that an address register Rb(Base Address Register) contains 150.What would be the results of additions?

200

200

100125

213

250

100 is a direct address : 50 + 200 = 250100 is an indirect address: 50 + M[M[100]] = 50 + M[200] = 50 + 125 = 175100 is a calculated address using Rb: 50 + M[100 + [Rb]] = 50 + M[250]

= 50 + 213 = 263100 is an immediate address: 50 + 100 = 150


• Full Address LDA X (EFA=X; AC<-M[X])

– Requires the largest number of bits(instruction becomes long)

• Abbreviated Address LDA X (EFA=[R]+X; AC<-M[[R]+X]) – Fewer number of bits for an address(X), but uses a register– Usually, part of an address is in a register which is implied– Register includes Base Address, Page Address, Segment Address, ...

• Implied Address ADD X ( AC is implied)

– No space(bit) at all(instruction becomes short) when there is a unique operand register

– Accumulator in 1-address machines– Stack(top) in 0-address machines

• Immediate Address ADD X (AC<-X)

– No instruction bits for address, but for operand(instruction becomes long)– Large number of instruction bits


Method of Representing AddressMethod of Representing AddressProperties of address:Properties of address:

Method of Representing AddressMethod of Representing Address


Abbreviating/Implying AddressAbbreviating/Implying AddressAbbreviating/Implying AddressAbbreviating/Implying Address

• Implying Address– When the desired operand is stored in a unique special register

» AC, Stack

• Abbreviating Address– When the desired operand is stored in the adjacent to the

address stored in the special address registers

– Address in the instruction needs to be specified only a few least significant bits, remainder of address is stored in a special address register;

» PC

» Base Address Register

» Index Register

» Page/Segment Address Register

register 1236

+24 1260 operand

address24 is shorter than 1260


Page/SegmentPage/Segment- Page -- Page -

Page/SegmentPage/Segment- Page -- Page -

Page– Page is a hardware concept, nothing to do with the program

– A page is a fixed length contiguous block of words

– In a Paged Memory, entire memory is partitioned into pages which are equal size, and there is a unique Page Address Register that stores the address of the starting location of the page

– In a paged memory, a stored object is addressed in relative location to the address stored in PAR(Page Address Register)

» Effective address = PAR + displacement within the page(specified addr)


Segment– Segment is a software concept

– A segment is a variable length contiguous block of words

» A program consists of several procedures may be partitioned such that each procedure becomes a segment

– A stored object is addressed in relative to the address stored in SAR(Segment Address Register)

» Effective address=SAR+displacement within the segment(specified addr)

Page/SegmentPage/Segment- Segment -- Segment -

Page/SegmentPage/Segment- Segment -- Segment -


Paged/Segmented MemoryPaged/Segmented MemoryPaged/Segmented MemoryPaged/Segmented Memory

...

Paged System

Segmented System

...

Paged Segment System

Fragmentation


• Absolute Address ADD X (EFA=X )

• Relative Address ADD X (EFA=[BAR] + X)

– Address should be related to Statically or Dynamically assigned Base Address Register(BAR)

– Base Address may be implied(CDC 600: Dynamic Relocation) or specified(IBM S/360: Static Relocation) using a GPR

– Displacement(X) must be specified, but can be abbreviated

• Capability Address ADD X (EFA=[S]+X)

– A pass to use an object stored in memory– A unique code(S) for each segment created and never used again even

if the segment disappears– For a given code, hardware finds the base-address and size of the

segment in the memory


Method of Mapping Address Space Method of Mapping Address Space to the Memory Spaceto the Memory Space


Method of Mapping Address Space Method of Mapping Address Space to the Memory Spaceto the Memory Space

Relocation : Possible by both relative and capability addressesProtection and Sharing: Capability is stronger


Relocation with Relocation with Relative AddressingRelative Addressing

Relocation with Relocation with Relative AddressingRelative Addressing

100101102103104

…100+X .

148149

A0

A1

A2

A3

A4

AX

A148

A149

ADD X(BAR)

Base + Displacementaddressing makesrelocation very easy

Relocation operation 1. Change content of BAR 2. Instruction does not change

ADD X(BAR)

+X

[BAR]

Relocation

500501502503504

…500+X .

548549

A0

A1

A2

A3

A4

AX

A148

A149

BAR100500

BAR100


Protection with Protection with Segment AddressingSegment Addressing

Protection with Protection with Segment AddressingSegment Addressing

FL

Memory

BAR

Memory

Limit

Sharing - 2 sets of BAR/FL or Limit - 1 set for individual user and 1 set for shared area


• Manual by programmer• Self Modifying program codes

– Program modifies the address part of an instruction– Sometimes unpredictable– Reentrant procedure is not possible


Method of Modifying AddressMethod of Modifying AddressProperties of address:Properties of address:

Method of Modifying AddressMethod of Modifying Address

Y ADD X [X] [X]+1JMP Y

Y ADD $X [R] [R]+1 JMP Y

Y ADD $X JMP Y

• Modification not of program but of registers by program– Flexible for programming– Powerful– Permit pure reentrant code

• Automatic modification by system– Automatic indexing and loop control– Hardware and Software triggered table updates– Base Address Register in CDC 6000 series


Automatic Mapping Automatic Mapping and Automatic Indexingand Automatic Indexing

Automatic Mapping Automatic Mapping and Automatic Indexingand Automatic Indexing

• Automatic Mapping– Relieves programmers of device dependent details

– Implement some level of protection and relocatability

– Global optimization of space usage and portability

• Automatic Indexing– Efficient operations on vectors, arrays

– Loop control by controlled sequencing and branch(BXH, BXL, BCT, …)


• Resolution of address– Bit, Byte, Word, Page– Hierarchy of address resolutions– Greater resolution implies more bits for specification for greater

flexibility

• Length of the addressed operands– Implicit(fixed to one word)– Variable length

» Specified explicitly in each instruction» Specified by a register» Specified by delimiter marks associated with the data

> reserved-bit delimiter(field or word mark)> reserved-bit configuration(record or group mark)

» Direction of processing> right to left for arithmetic> Left to right(or right to left) for moving


Resolution of AddressResolution of AddressProperties of address:Properties of address:

Resolution of AddressResolution of Address


Addressing Patterns of Programs(1):Addressing Patterns of Programs(1):

Locality of ReferenceLocality of ReferenceAddressing Patterns of Programs(1):Addressing Patterns of Programs(1):

Locality of ReferenceLocality of Reference

Locality of ReferenceDuring an interval of execution, a program favors a relatively small subset of Pages, and this set of favored pages changes membership slowly.

ReasonsContext: A program executes within a particular contextLooping: Programs tend to loop within a small set of pages

Spatial Locality:There is a high probability that a set of data, whose address differences are small, will be accessed in small time difference.

Temporal Locality:There is a high probability that the recently referenced data will be referenced in near future.


The number of written addresses in a program is much less than the number of executed effective addresses

Calculated addresses: Many different executed addresses are generated from a given written address

in the program– Automatic Indexing– Relocation– Temporary Registers


Generation of Multiple EFA from Generation of Multiple EFA from One Written AddressOne Written Address


Generation of Multiple EFA from Generation of Multiple EFA from One Written AddressOne Written Address



Reference Patterns of Reference Patterns of Instruction and DataInstruction and Data


Reference Patterns of Reference Patterns of Instruction and DataInstruction and Data

References to data tend to be more random than references to instructions, which tend to sequential except for branches, procedure calls and returns, interrupts

Run-length = Number of sequential addresses in an addressing pattern

Expected instruction stream run-length:14.4 words7~8 words(Stanford)

Expected data stream run-length:1 word


Improving Addressing Mechanism Improving Addressing Mechanism Using Properties of AddressUsing Properties of Address

Improving Addressing Mechanism Improving Addressing Mechanism Using Properties of AddressUsing Properties of Address

Improve address specification– Locality

» Use residual control to reduce the number of bits required for an address(abbreviated address)

– Number of effective addresses >> written addresses» Existence of temporaries, array processing

> Use registers, stacks to imply address to reduce instruction length

> Use auto-indexing for array processing– Based on Run-length

» Use of separate memory for instructions and data and use of different algorithms to optimize access

cs311-computer organizationmemory systemlecture 5 -1 lecture 5 storage system

Documents

memory systemin

memory accessfor

memory data registera

storage systemlecture

storage capacityif

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large capacity main

large storage capacity