Features

• Complete Stereo DAC System8× Interpolation Filter64× Delta-Sigma DACAnalog Post Filter

• Adjustable System Sampling Ratesincluding 32kHz, 44.1kHz & 48kHz

• 120 dB Signal-to-Noise Ratio

• Low Clock Jitter Sensitivity

• Completely Filtered Line-Level OutputsLinear Phase FilteringZero Phase Error Between ChannelsNo External Components Needed

• Flexible Serial Interface for Either 16or 18 bit Input Data

General DescriptionThe CS4328 is a complete stereo digital-to-analog out-put system. In addition to the traditional D/A function,the CS4328 includes an 8× digital interpolation filter fol-lowed by a 64× oversampled delta-sigma modulator.The modulator output controls the reference voltage in-put to an ultra-linear analog low-pass filter. Thisarchitecture allows for infinite adjustment of samplerate between 1 kHz and 50 kHz while maintaining lin-ear phase response simply by changing the masterclock frequency.

The CS4328 also includes an extremely flexible serialport utilizing two select pins to support four differentinterface modes.

The master clock can be either 256 or 384 times theinput word rate, supporting various audio environ-ments.

ORDERING INFORMATION:CS4328-KP 0 to 70 °C 28-pin Plastic DIPCS4328-KS 0 to 70 °C 28-pin Plastic SOICCS4328-BP -40 to +85 °C 28-pin Plastic DIPCS4328-BS -40 to +85 °C 28-pin Plastic SOICCDB4328 CS4328 Evaluation Board

Crystal Semiconductor CorporationP.O. Box 17847, Austin, TX 78760(512) 445-7222 FAX: (512) 445-7581http://www.crystal.com

OCT ’93DS62F3

1

18-Bit, Stereo D/A Converter for Digital Audio

-VREF

AOUTL

20

SDATAI

TST

2

DIF1

12

DIF0

13

ACKI

24

LRCK 28

BICKVoltage Reference

3

VA+VA-

5

AGND1

1

1918

AOUTR26

CMPOCALI

27

CALO

821

CMPI

22

ACKO

VD+ DGND

Clock Osc/Divider

11

16

AGND2

AGND3

4

25

14 15

XTI XTO CKS

RST

10

9

17

Interpolator

6

8xInterpolator

Delta-SigmaModulatorDelta-SigmaModulator

Delta-SigmaModulatorDelta-SigmaModulator

SRAM

AnalogLow-Pass

Filter

AnalogLow-Pass

FilterDAC

DAC

CalibrationMicrocontroller

MOSFETOutputStage

MOSFETOutputStage

Serial InputInterface

8xInterpolator

CS4328

Copyright Crystal Semiconductor Corporation 1993(All Rights Reserved)

* Definitions are at the end of this data sheet. Specifications are subject to change without notice.

ANALOG CHARACTERISTICS (TA = 25°C for K grade, TA = -40 to +85 °C for B grade; VA+,VD+= 5V; VA- = -5V; Logic "1" = VD+; Logic "0" = DGND; Full-Scale Output Sinewave, 991 Hz; Input Word Rate =48 kHz; Input Data = 18 Bits; BICK = 3.072 MHz; RL = 10kΩ; Measurement Bandwidth is 10 Hz to 20 kHz, un-weighted; unless otherwise specified.)

Parameter* CS4328-K CS4328-B

Symbol Min Typ Max Min Typ Max Units

Specified Temperature Range TA 0 +70 -40 +85 °C

Resolution 16 - - 16 - - Bits

Dynamic Performance

Signal-to-Noise Ratio (A-weighted) (Note 1) SNR 120 - - 120 - - dB

Total Harmonic Distortion + Noise (A-Weighted) THD+N0 dB Output, - -93 -90 - -88 -85 dB-20 dB Output, - -77 -73 - -75 -70 dB-60 dB Output, - -37 -33 - -35 -30 dB

Deviation From Linear Phase (Note 2) - - ± 0.5 - - ± 0.5 - deg

Passband: to -3 dB corner (Notes 3, 4) - 0 to 23.5 0 to 23.5 kHz

to 0.00025 dB corner (Notes 3, 4) 0 to 21.6 0 to 21.6 kHz

Frequency Response 10 Hz to 20 kHz (Note 2) - -0.05 +0.1 +0.2 -0.05 +0.1 +0.2 dB

Passband Ripple (Note 4) - - - 0.00025 - - 0.00025 dB

StopBand (Note 3) - 26.4 - - 26.4 - - kHz

StopBand Attenuation (Note 2) - 90 - - 90 - - dB

Group Delay (IWR = Input Word Rate) tgd - 33/IWR - - 33/IWR - s

Interchannel Isolation (1 kHz) - -100 -110 - -95 -105 - dB

dc Accuracy

Interchannel Gain Mismatch - - 0.1 - - 0.1 - dB

Gain Error - - - ± 5 - - ± 5 %

Gain Drift - - 150 - - 150 - ppm/°C

Offset Error (after calibration) - - - ± 1 - - ± 1 mV

Analog Output

Full Scale Output Voltage VOUT 3.8 4.0 4.2 3.8 4.0 4.2 Vpp

Power Supplies

Power Supply Current: VA+ IA+ - 40 55 - 40 55 mAVA- IA- - -40 -55 - -40 -55 mAVD+ ID+ - 50 60 - 50 60 mA

Power Dissipation - - 650 850 - 650 850 mW

Power Supply Rejection Ratio (1 kHz) PSRR - 50 - - 50 - dB

Notes: 1. Idle channel, digital input all zeros.2. Combined digital and analog filter characteristics.3. The passband and stopband edges scale with frequency. For input word rates, IWR, other than

48 kHz, the 0.00025 dB passband edge is 0.45×IWR and the stopband edge is 0.55×IWR.4. Digital filter characteristics.

CS4328

2 DS62F3

DIGITAL CHARACTERISTICS(TA = 25 °C; VA+ ,VD+ = 5V ± 5%; VA- = -5V ± 5%)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage VIH 70%VD+ - - V

Low-Level Input Voltage VIL - - 30%VD+ V

High-Level Output Voltage at Io = -20µA VOH 4.4 - - V

Low-Level Output Voltage at Io = 20µA VOL - - 0.1 V

Input Leakage Current (Note 5) Iin - - 1.0 µA

Note: 5. TST, DIF0 & DIF1 have internal pull-down devices, nominally 90kΩ.

ABSOLUTE MAXIMUM RATINGS (AGND1-3, DGND = 0V, all voltages with respect to ground.)

Parameter Symbol Min Max Units

DC Power Supplies: Positive Digital VD+ -0.3 6.0 V

Positive Analog VA+ -0.3 6.0 V

Negative Analog VA- 0.3 -6.0 V

|VA+ - VD+| - 0.4 V

Input Current, Any Pin Except Supplies Iin - ±10 mA

Digital Input Voltage VIND -0.3 (VD+)+0.4 V

Ambient Operating Temperature (power applied) TA -55 125 °C

Storage Temperature Tstg -65 150 °C

WARNING: Operation at or beyond these limits may result in permanent damage to the deviceNormal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS(AGND1, AGND2, AGND3, DGND = 0V; all voltages with respect to ground)

Parameter Symbol Min Typ Max Units

DC Power Supplies: Positive Digital VD+ 4.75 5.0 5.25 V

Positive Analog VA+ 4.75 5.0 5.25 V

Negative Analog VA- -4.75 -5.0 -5.25 V

|VA+ - VD+| - - 0.4 V

CS4328

DS62F3 3

SWITCHING CHARACTERISTICS(TA = 25 °C; VA+, VD+ = 5V ± 5%; VA- = -5V ± 5%; Inputs: Logic 0 = 0V, Logic 1 = VD+, CL = 20 pF)

Parameter Symbol Min Typ Max Units

Master Clock Frequency using Internal Oscillator:

CKS=H XTI/XTO 10.7 - 19.2 MHz

CKS=L - 7.1 - 13.9 MHz

Master Clock Frequency using External Clock:

CKS=H XTI/XTO 0.384 - 19.2 MHz

CKS=L - 0.256 - 13.9 MHz

XTI/XTO Pulse Width Low - 21 - - ns

XTI/XTO Pulse Width High - 21 - - ns

BICK Pulse Width Low tbickl 30 - - ns

BICK Pulse Width High tbickh 30 - - ns

BICK Period tbickw 80 - - ns

BICK rising to LRCK edge delay (Note 6) tblrd 35 - - ns

BICK rising to LRCK edge setup time (Note 6) tblrs 35 - - ns

SDATAI valid to BICK rising setup time (Note 6) tsbs 35 - - ns

BICK rising to SDATAI hold time (Note 6) tbsh 35 - - ns

RST Minimum Pulse Width Low 2 periods of XTI/XTO

Note: 6. "BICK rising" refers to modes 0, 1, and 3. For mode 2, replace "BICK rising" with "BICK falling."

bickhtblrst

blrdt

sbst bsht

bicklt

SDATAI

BICK

LRCK

bickhtblrst

blrdt

sbst bsht

bicklt

SDATAI

BICK

LRCK

MSB MSB-1

Serial Input Timing (Modes 0, 1, &3) Serial Input Timing (Mode 2)

CS4328

4 DS62F3

Figure 1. Typical Connection Diagram

CS4328D/A CONVERTER

CKS

TST

VD+ VA+

AGND1DGND

11

10 17 25 4 1

16 3

+5V Digital+5V

Analog

AGND2AGND3

0.1 µF

DIF0

DIF1

13

12

ModeSelect

ACKI

22ACKO

24

XTI

15XTO

14

20LRCK

AudioData

ProcessorBICK

SDATAI

19

18

0.1 µF

7NC

23NC

RST9Power Up/

Cal. Control

15 pF

1.2 M

10 pF

External Clock

74HCdevice

optional crystal oscillator

10 µF+

10 µF+

VA-

0.1 µF

5 -5VAnalog

10 µF+

VREF-28

0.1 µF 10 µF+

21CALO

CALI27

6

CMPI8

CMPO

AOUTL

AOUTR

2

26

10 nFNPO

10 nFNPO

51Ω

51Ω

0.1 µF

CS4328

DS62F3 5

GENERAL DESCRIPTION

The CS4328 is a complete stereo digital-to-ana-log system designed for digital audio. Thesystem accepts data at standard audio frequen-cies, such as 48 kHz, 44.1 kHz, and 32 kHz; andproduces line-level outputs.

The architecture includes an 8× oversampling fil-ter followed by a 64× oversampled one-bitdelta-sigma modulator. The output from the onebit modulator controls the polarity of a referencevoltage which is then passed through an ultra-linear analog low-pass filter. The result isline-level outputs with no need for further filter-ing.

SYSTEM DESIGN

Very few external components are required tosupport the DAC. Normal power supply decou-pling components and voltage reference bypasscapacitors are all that’s required.

System Clock Input

The master clock (XTI/XTO) input to the DACis used to operate the digital interpolation filterand the delta-sigma modulator. The master clockcan be either a crystal placed across the XTI andXTO pins, or an external clock input to the XTIpin with the XTO pin left floating.

The frequency of XTI/XTO is determined by thedesired Input Word Rate, IWR, and the setting ofthe Clock Select pin, CKS. IWR is the frequencyat which words for each channel are input to theDAC and is equal to LRCK frequency. SettingCKS low selects an XTI/XTO frequency of256× IWR while setting CKS high selects384× IWR. The ACKO pin will always be128× IWR and is used by the analog low-passsmoothing filter. Table 1 illustrates various audioword rates and corresponding frequencies usedin the DAC.

The remaining system clocks, LRCK and BICK,must be synchronously derived from XTI/XTO.If the CS4328 internal oscillator is used, the cir-cuit must be configured and XTO buffered asshown in Figure 1. XTI/XTO can be divided toproduce LRCK and BICK using a synchronouscounter such as 74HC590. Notice that the valueof the capacitor on XTO is 10 pF and the XTIcapacitor is 15 pF, which allows for 5 pF of gateand stray capacitance.

It is also possible to divide ACKO, 128× IWR,to derive BICK and LRCK. However, externalcircuitry must be used to apply a "kick-start"pulse to LRCK in order to activate ACKO. Thesequence for the cancellation of RESET, begin-ning of calibration and activation of ACKO isshown in Figure 2 with the required transitionsindicated by arrows. A momentary loss ofXTI/XTO or power will require a "kick-start"pulse to resume operation.

Serial Data Interface

Data is input to the CS4328 via three serial inputpins; SDATAI is the serial data input, BICK isthe serial data clock and LRCK defines the chan-nel and delineation of data. The DAC supportsfour serial data formats which are selected viathe digital input format pins DIF0 and DIF1. Thedifferent formats control the relationship ofLRCK to SDATAI and the edge of BICK used to

LRCK CKS XTI/XTO ACKO(kHz) (MHz) (MHz)

32 low 8.192 4.096

32 high 12.288 4.096

44.1 low 11.2896 5.6448

44.1 high 16.9344 5.6448

48 low 12.288 6.144

48 high 18.432 6.144

Table 1. Common Clock Frequencies

CS4328

6 DS62F3

latch data. Table 2 lists the four formats, alongwith the associated figure number. Format 0 iscompatible with existing 16-bit D/A convertersand digital filters. Format 1 is an 18-bit versionof format 0. Format 2 is similar to Crystal ADCsand many DSP serial ports. Format 3 is compat-ible with the I2S serial data protocol. Formats 2and 3 support 18-bit input or 16-bit followed bytwo zeros. In all four serial input modes, the se-rial data is MSB-first and 2’s-complementformat.

Formats 0, 2 and 3 will operate with 16-bit dataand 16 BICK pulses as well. See Figure 6 for16-bit t iming. However, the use ofBICK = 64× IWR is recommended to minimizethe possibility of performance degradation result-ing from BICK coupling into VREF-.

Reset and Offset Calibration

RST is an active low signal that resets the digitalfilter and the delta-sigma modulator, synchro-nizes LRCK with internal control signals andstarts an offset calibration cycle upon exiting re-set. When RST goes low, CALO goes high andstays high until the end of an offset calibrationcycle. An offset calibration cycle takes 1024IWR cycles to complete. CALO must be con-nected to CALI and CMPO must be connectedto CMPI for offset calibration. During an offsetcalibration the analog output is forced to zero.

Power-Up Considerations

Upon initial application of power to the DAC,offset calibration and digital filter registers willbe indeterminate. RST should be low duringpower-up to activate an internal mute and pre-vent this erroneous information from beingoutput from the DAC. Bringing RST high willbegin a calibration cycle and initialize these reg-isters.

Muting

There are two types of mutes that can be imple-mented with the CS4328. The first is a -50 dB

DIF1 DIF0 Mode Figure0 0 0 3

0 1 1 3

1 0 2 4

1 1 3 5

Table 2. Digital Input Formats

XTI/XTO

Reset Status

40 nsminimum

40 nsminimum

Exit Reset

LRCK"Kickstart"

ACK0

RST

Figure 2. RESET Cancellation Timing

CS4328

DS62F3 7

LRCK

BICK

Left Channel Right Channel

SDATAI 6 5 4 3 2 1 09 8 715 14 13 12 11 10 6 5 4 3 2 1 09 8 715 14 13 12 11 1016 Bit

SDATAI18 Bit

6 5 4 3 2 1 09 8 715 14 13 12 11 1017 16 6 5 4 3 2 1 09 8 715 14 13 12 11 1017 16

15

17

LRCK

BICK

Left Channel Right Channel

SDATAI 6 5 4 3 2 1 09 8 715 14 13 12 11 10 6 5 4 3 2 1 09 8 715 14 13 12 11 1016 Bit

SDATAI18 Bit

6 5 4 3 2 1 09 8 715 14 13 12 11 1017 16 6 5 4 3 2 1 09 8 715 14 13 12 11 1017 16

Figure 5. Digital Input Format 3

Figure 4. Digital Input Format 2

LRCK

BICK

Left Channel Right Channel

SDATAI 6 5 4 3 2 1 09 8 715 14 13 12 11 101 0 6 5 4 3 2 1 09 8 715 14 13 12 11 10Mode 0

SDATAI 6 5 4 3 2 1 09 8 715 14 13 12 11 101 0 6 5 4 3 2 1 09 8 715 14 13 12 11 10Mode 1

17 16 17 16

Figure 3. Digital Input Formats 0 & 1

LRCK Left Channel Right Channel

6 5 4 3 2 1 09 8 715 14 13 12 11 10 6 5 4 3 2 1 09 8 715 14 13 12 11 10

BICK

BICK

6 5 4 3 2 1 09 8 715 14 13 12 11 10 6 5 4 3 2 1 09 8 715 14 13 12 11 10

6 5 4 3 2 1 09 8 715 14 13 12 11 10 6 5 4 3 2 1 09 8 715 14 13 12 11 10

SDATAIMode 2

SDATAIMode 0

SDATAIMode 3

* LRCK must be inverted.

*

Figure 6. Digital Input Formats 0, 2 and 3 with 16 BICK Periods

CS4328

8 DS62F3

mute which can be activated by forcing theCALI pin high. Figure 7 shows how to imple-ment a -50 dB mute using an OR gate. Thepropagation of the gate will be the only delay inmoving the CS4328 to a muted state.

The second mute option is a two stage operationwhich involves forcing SDATAI to 0 using anAND gate as shown in Figure 8. The first muteoccurs following 33 LRCK cycles when the 0 in-put data propagates to the output of the DAC.The rms noise present at the output will typicallybe 93 dB below fullscale. Following a total of4096 LRCK cycles with 0 input data the outputof the CS4328 will mute and lower the outputrms noise to a minimum of 120 dB belowfullscale. Upon release of the MUTE commandand non-zero input data the CS4328 output mutewill immediately release. However, 33 LRCKcycles are required for input data to propagate tothe output of the CS4328.

Grounding and Power Supply Decoupling

As with any high resolution converter, theCS4328 requires careful attention to power sup-ply and grounding arrangements to optimizeperformance. Figure 1 shows the recommendedpower arrangements with VA+ connected to aclean +5 volt supply and VA- connected to a

clean -5 volt supply. VD+, which powers thedigital interpolation filter and delta-sigma modu-lator, may be powered from the system +5 voltlogic supply. Decoupling capacitors should belocated as near to the CS4328 as possible.

The printed circuit board layout should haveseparate analog and digital regions with individ-ual ground planes. The CS4328 should straddlethe ground plane break as shown on theCDB4328 Evaluation board. Optional jumpersfor connecting these planes should be includednear the DAC, where power is brought on to theboard and near the regulators. All signals, espe-cially clocks, should be kept away from theVREF- pin to avoid unwanted coupling into theCS4328. The VREF- decoupling capacitors, par-ticularly the 0.1 µF, must be positioned tominimize the electrical path from VREF- toPin 1 AGND and to minimize the path betweenVREF- and the capacitors. Extensive use ofground plane fill on both the analog and digitalsections of the circuit board will yield large re-ductions in radiated noise effects. An applicationnote "Layout and Design Rules for Data Con-verters" is printed in the Application Notesection of this book.

Analog Output and Filtering

Full scale analog output for each channel is typi-cally 4V peak-to-peak. The analog outputs candrive load impedances as low as 600Ω and areshort-circuit protected to 20mA.

The CS4328 analog fil ter is a 5th orderswitched-capacitor filter followed by a second-order continuous-time fi lter. Theswitched-capacitor filter is clock dependent andwill scale with the IWR frequency. The continu-ous-time filter is fixed and not related to IWR. Alow-pass filter consisting of a 51Ω resistor and a.01 µF NPO capacitor is recommended on theanalog outputs.

21

27MUTE

CALO

CALI

CS4328

Figure 7. -50dB Muting

18MUTESDATAI

CS4328

DATA

_____

Figure 8. -120 dB Muting

CS4328

DS62F3 9

Performance Plots

The following collection of CS4328 measure-ment plots (IWR = 48 kHz) were taken with anAudio Precision Dual Domain System One. AllFFT plots are 16,384 point.

Figure 9 shows the frequency response with a48 kHz input word rate. The response is very flatout to half the input word rate.

Figure 10 shows the muted noise with all zerosdata into the CS4328. This plot is dominated bythe noise floor of the System One.

Figure 11 shows the unmuted noise. This datawas taken by feeding the CS4328 continuous ze-ros, but pulling CALI low. This unmutes theoutput stage of the CS4328. This plot shows thenoise shaping characteristics of the delta-sigmamodulator combined with the analog filter.

Figure 12 shows the A-weighted THD+N vs sig-nal amplitude for a dithered 1kHz input signal.Notice that there is no increase in distortion asthe signal level decreases. This indicates verygood low-level linearity, one of the key benefitsof the delta-sigma technique.

Figure 13 shows the fade-to-noise linearity testresult using track 20 of the CBS CD-1. The in-put test signal is a dithered 500 Hz sine wavewhich gradually fades from -60 dB level to -120dB. During the fading, the output level from theCS4328 is measured and compared to the ideallevel. Notice the very close tracking of the out-put level to the ideal, even at low level inputs of-90 dB. The gradual shift of the plot away fromzero at signal levels < -100 dB is caused by thebackground noise starting to dominate the meas-urement.

Figure 14 shows the impulse response, takenfrom the single positive full scale value on track17 of the CD-1 test disk. Notice the high degreeof symmetry, indicating good phase linearity.

Figure 15 shows a 16K FFT plot result, with a1 kHz -90 dB dithered input. Notice the com-plete lack of distortion components and tones.

Figure 16 shows a bandlimited, 10 Hz to22 kHz, time domain plot of the CS4328 outputwith a 1 kHz, -90 dB dithered input. Notice theclear residual sine wave shape, in the presence ofnoise.

Figure 17 shows the monotonicity test resultplot. The input data to the CS4328 is +1 LSB, -1LSB four times, then +2 LSB, -2 LSB four timesand so on, until +10 LSB, -10 LSB. This datapattern is taken from track 21 of the CD-1 testdisk. Notice the increasing staircase envelope,with no decreasing elements. Notice also theclear resolution of the LSB. For this test, oneLSB is a 16-bit LSB.

The following tests were done by filtering theanalog output of the CS4328 with the SystemOne analyzer 1 kHz notch filter to reduce thepeak signal level. The resulting signal was thenamplified and applied to the DSP module, avoid-ing distortion in the System One A/D converter.

Figure 18 shows a 16K FFT Plot with a 1 kHz,0 dB input. Notice the low order harmonic dis-tortion at < -100 dB.

Figure 19 shows a 16K FFT Plot with a 1 kHz,-10 dB input. Notice the almost complete ab-sence of distortion, with a small residual 2ndharmonic at -110 dB.

CS4328

10 DS62F3

vs

-100

-98

-96

-94

-92

-90

-88

-86

-84

-82

-80THD+N(dBr)

-100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0

GENAMP(dBFS)CRYSTAL THDAM18A

Figure 12. THD+N vs 18-bit Input Signal Level

CRYSTAL TR20R vs

-10

-8

-6

-4

-2

0

2

4

6

8

10BANDPASS(dBr)

-120 -110 -100 -90 -80 -70 -60

LEVEL(dBr)

Figure 13. Fade-to-Noise Linearity

CRYSTAL IMPULSE vs

-0.500

-0.083

0.333

0.750

1.167

1.583

2.000AMP1(V)

0.0 95.8 192 287 383 479 575 670 766 862

TIME(usec)

Figure 14. Impulse Response

CRYSTAL FRQRSP48 vs

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0AMPL(dBr)

10 100 1k 10k 30k

GENFRQ(Hz)

Figure 9. Frequency Response (48 kHz word rate)

CRYSTAL NOISE & vs

-160

-140

-120

-100

-80

-60

-40

-20

0AMP1(dBr) AMP1(dBr)

0.02 9.82 19.6 29.4 39.2 49.0 58.8 68.6 78.4 88.2 98.0

FREQ(kHz)

Figure 10. Muted Idle Channel Noise

CRYSTAL NOISEUNM vs

-160

-140

-120

-100

-80

-60

-40

-20

0AMP1(dBr)

0.02 9.82 19.6 29.4 39.2 49.0 58.8 68.6 78.4 88.2 98.0

FREQ(kHz)

Figure 11. Unmuted Idle Noise

CS4328

DS62F3 11

CRYSTAL 1k 0dBFFT vs

-140

-120

-100

-80

-60

-40

-20

0AMP1(dBr)

20 100 1k 10k 20k

FREQ(Hz)

Figure 18. 1 kHz, 0 dB Input FFT Plot

CRYSTAL 1KM10DB vs

-140

-120

-100

-80

-60

-40

-20

0AMP1(dBr)

20 100 1k 10k 20k

FREQ(Hz)

Figure 19. 1 kHz, -10 dB Input FFT Plot

CRYSTAL M90DB1K vs

-140

-120

-100

-80

-60

-40

-20

0AMP1(dBr)

20 100 1k 10k 20k

FREQ(kHz)

Figure 15. 1 kHz, -90 dB Input FFT Plot

CRYSTAL M90TIME vs

-250

-200

-150

-100

-50

0

50

100

150

200

250AMP1(uV)

0.0 0.50 1.00 1.50 2.00 2.50 3.00

TIME(msec)

Figure 16. 1 kHz, -90 dB Input Time Domain Plot

CRYSTAL MONOTON vs

-800

-640

-480

-320

-160

0

160

320

480

640

800AMP1(uV)

0 5 10 15 20 25 30 35 40 45 50

TIME(msec)

Figure 17. Monotonicity Test (16-bit data)

CS4328

12 DS62F3

THEORY OF OPERATION

The CS4328 architecture can be considered infive blocks: Interpolation, sample/hold, delta-sigma modulation, D/A conversion, and analogfiltering.

Audio data is input to the CS4328 digital inter-polation filter which removes images of the inputsignal that are present at multiples of the inputsample frequency, Fs (Figure 21). Following theinterpolation stage, the resulting frequency spec-trum has images of the input signal at multiplesof eight times the input sample frequency, 8× Fs(Figure 22). Eliminating the images between Fsand 8× Fs greatly relaxes the requirements of theanalog filtering, allowing the suppression of im-ages while leaving the audio band of interestunaltered.

The CS4328 interpolation stage is followed by asample-and-hold function where the data pointsfrom the interpolator are held for eight (64× Fs)clock cycles. The resulting frequency responseis a sinx/x characteristic with zeros at 8× Fs mul-

tiples. The sinx/x zeros completely attenuatesignals at 8× Fs and largely suppress the remain-ing energy of the images (Figure 23). The 8×interpolation followed by the 8× sample-and-

hold results in data at a rate of 64× Fs.

The delta-sigma modulator takes in the 64× Fsdata (3.072 MHz for 48kHz sampled systems)and performs fifth-order noise shaping. In thedigital modulator of the CS4328, 18-bit audiodata is modulated to a 1-bit, 64× Fs signal. The5th-order noise shaper allows 1-bit quantizationto support 18-bit audio processing by suppress-ing quantization noise in the bandwidth of

interest. Figure 24 shows the frequency spec-trum of the modulator output.

The CS4328’s digital modulator is followed by aD-to-A converter that translates the 1-bit signalinto a series of charge packets. The magnitudeof the charge in each packet is determined bysampling of a voltage reference onto a switched

AudioData

AnalogOutput

ContinuousTimeFilter

DAC8 X S/H

8xInterpolator

DeltaSigma

Modulator

Digital SwitchedCapLPF

Analog Filter

Figure 20. CS4328 Architecture

f (kHz)8Fs 16Fs24

(dB)

Figure 23. Spectrum After S/H

f (kHz)8Fs 16Fs24

(dB)

Figure 22. 8X Interpolated Data Spectrum

f(kHz)24

(dB)

Figure 24. Modulator Output Spectrum

f (kHz)Fs 2Fs24

(dB)

Figure 21. Input Data Spectrum

CS4328

DS62F3 13

capacitor, where the polarity of each packet iscontrolled by the 1-bit signal. The result is a1-bit D/A conversion process that is very insensi-tive to clock jitter. This is a major improvementover previous generations of 1-Bit D/A convert-ers where the magnitude of charge in the D/Aprocess is determined by switching a current ref-erence for a period of time defined by periods ofthe master clock.

The final stage of the CS4328 is made up of a5th order switched-capacitor low pass filter and a2nd order continuous time filter. The switched-capacitor filter eliminates out-of-band energy re-sult ing from the noise shaping process(Figure 25). The switched-capacitor stage scaleswith the master clock signal being applied to the

CS4328. The final stage is a 2nd order continu-ous time filter that eliminates high frequencyenergy that appears at multiples of the 64× Fssample rate (Figure 26).

Figures 27-30 are computer simulations of thecombined response of the CS4328 digital andanalog filters with an input word rate of 48 kHz.

Figure 27 shows the individual and combinedphase response of the CS4328 filters. Notice thedigital filter equalization of the analog filter toproduce a linear phase response.

Figures 28-30 are plots of the CS4328 magni-tude response.

0 2 4 6 8 10 12 14 16 18 20Frequency (kHz)

-20

-16

-12

-8

-4

0

4

8

12

16

20

Ph

ase

(deg

rees

) Analog Filter

Digital Filter

Total Phase

Figure 27. Deviation From Linear Phase

f (kHz) 24 64Fs

(dB)

Figure 25. Spectrum After Switched-Capacitor Filter

f (kHz) 24

(dB)

Figure 26. Spectrum After Continuous Time Filter

CS4328

14 DS62F3

20 21 22 23 24 25Input Frequency (kHz)

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

1

Mag

nitu

de (

dB)

Figure 29. Combined Digital and Analog Filter Frequency Response

22 23 24 25 26 27 28 29 30Input Frequency (kHz)

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Mag

nitu

de (

dB)

Figure 30. Combined Digital and Analog Filter Transition Band

0 8 16 24 32 40 48Input Frequency (kHz)

-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0

10

Mag

nitu

de (

dB)

Figure 28. Combined Digital and Analog Filter Frequency Response

CS4328

DS62F3 15

PIN DESCRIPTIONS

Power Supply Connections

VA+ - Positive Analog Power, PIN 3.Positive analog supply. Nominally +5 volts.

VA- - Negative Analog Power, PIN 5.Negative analog supply. Nominally -5 volts.

AGND1, AGND2, AGND3 - Analog Grounds, PINS 1, 4, 25.Analog ground reference.

VD+ - Positive Digital Power, PIN 16.Positive supply for the digital section. Nominally +5 volts.

DGND - Digital Ground, PIN 17.Digital ground for the digital section.

Analog Outputs

VREF- - Voltage Reference Output, PIN 28.Nominally -3.68 volts. Normally connected to a 0.1µF ceramic capacitor in parallel with a10µF or larger electrolytic capacitor. Note the negative output polarity.

AOUTL - Analog Left Channel Output, PIN 2.Analog output for the left channel. Typically 4V peak-to-peak for a full-scale input signal.

AOUTR - Analog Right Channel Output, PIN 26.Analog output for the right channel. Typically 4V peak-to-peak for a full-scale input signal.

ANALOG GROUND AGND1 VREF- VOLTAGE REFERENCE OUTPUTANALOG LEFT CHANNEL OUTPUT AOUTL CALI CALIBRATION INPUT

ANALOG POWER VA+ AOUTR ANALOG RIGHT CHANNEL OUTPUTANALOG GROUND AGND2 AGND3 ANALOG GROUND

NEGATIVE ANALOG POWER VA- ACKI ANALOG CLOCK INPUTCOMPARATOR OUTPUT CMPO NC NO CONNECT

NO CONNECT NC ACKO ANALOG CLOCK OUTPUTCOMPARATOR INPUT CMPI CALO CALIBRATION OUTPUT

RESET RST LRCK LEFT/RIGHT CLOCK INPUTTEST TST BICK SERIAL BIT CLOCK INPUT

CLOCK SELECT CKS SDATAI SERIAL DATA INPUTDIGITAL INPUT FORMAT 1 DIF1 DGND DIGITAL GROUNDDIGITAL INPUT FORMAT 0 DIF0 VD+ DIGITAL POWER

CRYSTAL OR CLOCK INPUT XTI XTO CRYSTAL OSCILLATOR OUTPUT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CS4328

16 DS62F3

Digital Inputs

XTI - Crystal or Clock Input, PIN 14.A crystal oscillator can be connected between this pin and XTO, or an external CMOS clockcan be input on XTI. The frequency must be either 256× or 384× the input word rate based onthe clock select pin, CKS.

ACKI - Analog Clock Input, PIN 24.This is the master clock input for the analog section of the chip and must be 128× the inputword rate. ACKI is typically connected to the Analog Clock Ouput pin, ACKO.

CALI - Calibration Input, PIN 27.Input to the analog section that is used during offset calibration. Normally connected to theCalibration Output pin, CALO.

CMPI - Comparator Input, PIN 8Input to the digital section that is used during offset calibration. Normally connected to theComparator Output pin, CMPO.

LRCK - Left/Right Clock, PIN 20.This input determines which channel is currently being input on the Serial Data Input pin,SDATAI. The format of LRCK is controlled by DIF0 and DIF1.

BICK - Serial Bit Input Clock, PIN19.Clocks the individual bits of the serial data in from the SDATAI pin. The edge used to latchSDATAI is controlled by DIF0 and DIF1.

SDATAI - Serial Data Input, PIN 18.Two’s complement MSB-first serial data of either 16 or 18 bits is input on this pin. The data isclocked into the CS4328 via the BICK clock and the channel is determined by the LRCK clock.The format for the previous two clocks is determined by the Digital Input Format pins, DIF0and DIF1

DIF0,DIF1 - Digital Input Format, PINS 13, 12These two pins select one of four formats for the incoming serial data stream. These pins setthe format of the BICK and LRCK clocks with respect to SDATAI. The formats are listed inTable 2.

CKS - Clock Speed Select, PIN 11.Selects the clock frequency input on the XTI pin. CKS low selects 256× the input word rate(LRCK frequency) while CKS high selects 384×.

RST - Reset and Calibrate, PIN 9.When reset is low the filters and modulators are held in reset. When reset goes high, an offsetcalibration is initiated.

CS4328

DS62F3 17

Digital Outputs

XTO - Crystal Oscillator Output, PIN 15.When a crystal oscillator is used, it is tied between this pin and XTI. When an external clock isinput, this pin should be left floating.

ACKO - Analog Clock Output, PIN 22.This output is 128× the input word rate (LRCK frequency). Normally connected to the AnalogClock Input pin, ACKI.

CALO - Calibration Output, PIN 21.Used during offset calibration. Must be connected to the Calibration Input pin, CALI.

CMPO - Comparator Output, PIN 6.Used during offset calibration. Must be connected to the Comparator Input pin, CMPI.

Miscellaneous

NC - No Connection, PINS 7, 23.These two pins are bonded out to test outputs. They must not be connected to any externalcomponent or any length of PC trace.

TST -Test Input, PIN 10.Allows access to the CS4328 test modes, which are reserved for factory use. Must be tied toDGND.

CS4328

18 DS62F3

PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise - The ratio of the rms value of the signal to the rms sum of allother spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), includingdistortion components. Expressed in decibels.

Signal-to-Noise Ratio - The ratio of the full scale rms value of the signal to the rms sum of all otherspectral components over the specified bandwidth with an input of all zeros.

Frequency Response - A measure of the amplitude response variation from 10 Hz to 20 kHz relativeto the amplitude response at 1 kHz. Units in decibels.

Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured foreach channel at the converter’s output with all zeros to the input under test and a full-scalesignal applied to the other channel. Units in decibels.

Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels.

Gain Error - The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift - The change in gain value with temperature. Units in ppm/°C.

Offset Error - The deviation of the mid-scale transition (111...111 to 000...000) from the ideal(AGND). Units in mV.

CS4328

DS62F3 19

28 pinPlastic DIP1

28 15

14

MILLIMETERS INCHESDIM MIN MAX MIN MAX

D

B

A

L∝

C

13.72 14.22 0.540 0.56036.45

1.020.360.513.94

3.18

0.20

0°

15.24

37.21

1.650.561.025.08

3.81

0.38

15°

1.435

0.0400.0140.0200.155

0.1250.600

0.008

0°

1.465

0.0650.0220.0400.200

0.150

0.015

15°

15.87 0.6252.41 2.67 0.095 0.105

CeA

E1

D

B

SEATINGPLANE

A

B1 e1

A1 L

∝

NOTES:1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER.2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.

NOM

13.9736.83

1.270.460.764.32

-

0.25

-

-2.54

NOM

0.5501.450

0.0500.0180.0300.170

--

0.010

-

0.100

A1

B1

E1e1eA

SOIC

MILLIMETERS INCHESMIN MAX MAXMIN

0.095 0.1052.41 2.67

0.008 0.0150.203 0.381

0.398 0.42010.11 10.67

0.0200.0130.510.33

0.016 0.0350.41 0.89

8°0°0° 8°

MILLIMETERS INCHESMIN MAX MAXMINpins

0.4100.3909.91 10.4116

0.5100.49012.45 12.9520

0.6100.59014.99 15.5024

0.7100.69017.53 18.0328

0.0120.0050.127 0.300

1.14 0.040

DIM

EE

b

L

D

e

AA

c

0.292 0.2987.42 7.57

D

EE1

e

A

Ab 1

A2c

L

µ

1

µ

11.40 0.055

A 2

see table above

NOM

2.54

0.280

10.41

0.46

-

-

NOM

10.16

12.70

15.24

17.78

-

7.49

1.27

2.29 2.542.41

NOM

0.100

0.011

0.410

0.018

-

-

NOM

0.400

0.500

0.600

0.700

-

0.295

0.050

0.1000.090 0.095

Features

• Demonstrates recommended layoutand grounding arrangements

• CS4328 Supports multiple input formats

• CS8412 Receives AES/EBU, S/PDIF,& EIAJ-340 Compatible Digital Audio

• Digital and Analog Patch Areas

• Operation with on-board CS8412 orexternally supplied system timing

General DescriptionThe CDB4328 evaluation board allows fast evaluationof the CS4328 18-bit, stereo D/A converter. The boardprovides an analog output interface via BNC connec-tors for both channels. Evaluation requires an analogsignal analyzer, a digital signal source, and a powersupply.

Also included is a CS8412 digital audio receiver I.C.,which will accept AES/EBU, S/PDIF, and EIAJ-340compatible audio data. The CS8412 can provide thesystem timing necessary to operate the CS4328.

The evaluation board may also be configured to acceptexternal timing signals for operation in a user applica-tion during system development.

ORDERING INFORMATION: CDB4328

Crystal Semiconductor CorporationP.O. Box 17847, Austin, TX 78760(512) 445 7222 Fax: (512) 445 7581http://www.crystal.com

AUG ’93DS62DB2

21

CS4328 Evaluation Board

CDB4328

Error Info/ChannelStatus

-15V GND +15V GND +5V

L/R SCLK SDATA MCLK

Power SupplyRegulation and Conditioning

AOUTR

AOUTL

AnalogPatchArea

DigitalPatchArea

CS4328D/A Converter

OffsetCalibration

Network

Digital Audio Input

TimingSignal

Selector

CS8412DigitalAudio

Receiver

6

Block Diagram

Power Supply Circuitry

Figure 1 shows the evaluation board power sup-ply circuitry. Power is supplied to the evaluationboard by five binding posts. The +5 V analogpower supply inputs of the converter are derivedfrom + 15 V using the voltage regulators U5 andU6. The +5 V digital supply for the converterand the discrete logic on the board is providedby the +5 V and DGND binding posts. D1, D2,and D3 are transient suppressors which also pro-vide protection from incorrectly connectedpower supply leads. C1-C8 provide generalpower supply filtering for the analog supplies.As shown in Figure 2, C20-C24 provide local-ized decoupling for the converter VA+ and VA-pins. Note that C22 is connected between VA-and VA+ and not VA- and AGND. The evalu-ation board uses both an analog and a digitalground plane which are connected at J1. Thisground plane arrangement isolates the board’sdigital logic from the analog circuitry.

Offset Calibration & Reset Circuitry

Figure 1, shows the offset calibration circuit pro-vided on the evaluation board. Upon power-up,this circuit provides a pulse on the Digital toAnalog Converter’s RST pin initiating an offsetcalibration cycle. Pressing and releasing S2 alsoinitiates an offset calibration cycle.

Serial Data Interface

Figure 1 shows that there are two options for in-puting serial data into the CS4328. Serial datacan be provided via the SDATA BNC connectoron the evaluation board. BNC connectors forSCLK, the serial data input clock, and L/R, theclock that defines the channel and delineates thedata, are also provided on the evaluation board.This information can also be provided by the on-board CS8412. JP3 selects the source ofSDATA, SCLK, and L/R that will be provided tothe converter. JP3 selections are shown in Ta-ble 1.

C6 C7

C5 C8

0.22 uF

0.47 uF J1

+ C3

47 uF

C4+

47 uF

0.22 uF

OUTCOM

U578L05IN

D3

D2

0.47 uF

C2+ C1

47 uF 0.1 uFD1

+15V

-15V

+5V

79L05U6

COMIN OUT

DGNDAGND

VA+

VA-

VD+

D1 = P6KE-6V8P from ThomsonD2 = D3 = 1N6276A 1.5KE

AGND

DGND

VD+

10kΩ

C150.1uF

D131N148

S2CAL

R4

43

U7B74HC14

65

U7C

RSTCS4328

Figure 1. Power Supply and Reset Circuitry

CDB4328

22 DS62DB2

The CS4328 supports four serial data input for-mats. The selection of which is made via thedigital input format pins DIF0 and DIF1. Thedifferent formats control the relationship of L/Rto SDATA and the edge of SCLK used to latchthe data. Consult the CS4328 data sheet for anexplanation of the different formats.

System Timing

The master clock input to the CS4328 can beprovided by several sources. JP3 selects thesource of the master clock that is to be suppliedto the XTI pin of the converter. When EXTCLK is selected, the master clock is provided byone of two sources. The 12.288 MHz clock sig-nal provided by U8 can be used as the masterclock for both the CS4328 and the external sys-tem that provides the serial data to the board.The other option is for a master clock that issynchronized to the external serial data cominginto the board, be used as the master clock forthe CS4328 as well. However, if an external

NC

NC

LRCK

BICK

SDATAI

XTI

XTO

RST

CKS DIFO DIFI

VREF

AOUTR

AOUTL

CALICALO

CMPICMPO

AGND3

AGND2

AGND1VA+ACKIACKOVD+

VD+

11 13

VD+

12

R1147kΩ

10 17TST DGND

28

26

C1910 nF NPO

C160.1 uF

C1710 uF

51Ω

R6

2

C1810 nF NPO

51Ω

R5

VA- -5V Analog,VA-

+5V Analog,VA+

+

C241.0 uF

C230.1 uF

C220.1 uF

AOUTL

AOUTR

VD+1 uFC26

0.1 uFC25

U3, Pin 3

U3, Pin 6

U3, Pin 8

U3, Pin 11

L/R SCLK SDATA MCLK

15

14

18

19

20

723

9FromResetCircuit

+

16 22 241

5

4

25

68

2127

3

U1CS4328

C201.0 uF

C210.1 uFTP

TP

TP

TP

+

+

TP

TP

JP2

Figure 2. CS4328 DAC Connections

Position Input Option Selected

EXT CLK SDATA,SCLK, L/R provided by an external source.

8412 SDATA,SCLK, L/R provided by the CS8412

Table 1. JP3 Selectable Options

CDB4328

DS62DB2 23

master clock is to be used, U8 must be removedfrom it’s socket to prevent the two clock signalsfrom interfering with one another. When 8412 isselected by JP3, the master clock for the CS4328is provided by the MCK output of the CS8412.The CKS pin of the CS4328 can be pulled eitherhigh or low via JP2. This determines whetherthe master clock frequency has to be 384X or256X the input word rate. Consult the CS4328data sheet for the common master clock frequen-cies table.

Analog Outputs

The analog outputs are available at 2 BNC con-nectors labeled AOUTL and AOUTR. R5 andC18 remove the remaining very high frequencycomponents from the left channel output signalwhile R6 and C19 do so for the right channeloutput signal.

Digital Audio Standard Interface

Included on the evaluation board is a CS8412Digital Audio Interface Receiver. This devicecan receive and decode data according to theAES/EBU, S/PDIF, and EIAJ-340 interfacestandard. Figure 3 shows the schematic for theCS8412. The input is coupled to the devicethrough a transformer that is included on theboard. The input to the device can be configuredto accept either professional or consumer inputmodes. Consult the CS8412 data sheet for anexplanation of the two input modes.

The LEDs, D4-D8, perform two functions.When S1 is in the Channel Status position, theLEDs display the channel status information forthe channel selected by JP1. When S1 is in theError Information position, the LEDs D4-D6,display encoded error information that can bedecoded by consulting the CS8412 data sheet.Encoded sample frequency information is dis-played on LEDs D7-D9 provided a proper clockis being applied to the FCK pin of JP1. Whenan LED is lit, this indicates a "1" on the corre-

sponding pin located on the CS8412. When anLED is off, this indicates a "0" on the corre-sponding pin. Neither the L or R option shouldbe selected if the FCK pin of JP1 is being drivenby a clock signal.

Serial Output Interface

The SDATA, SCLK, L/R, and MCLK BNCconnectors can also be used to provide a serialoutput interface for the CS8412. With JP3 in the8412 position, the outputs from the CS8412 canbe brought off the board to an external evalutionsystem. This data can be configured in one ofseven selectable formats. These formats are out-lined in the CS8412 data sheet.

CDB5336/7/8/9 Interface to CDB4328

Many users find it informative to evaluate acombined ADC and DAC system connected to-gether yielding analog input and analog output.This can be accomplished by interconnecting aCDB5326/7/8/9 or CDB5336/7/8/9 to aCDB4328 evaluation board. The following in-formation contains several techniques toaccomplish this goal. There are two generalpoints which need to be mentioned. An analoginput of ± 3.68 V will produce a full scale digitaloutput from the CS5336/7/8/9 and theCS5326/7/8/9. A full scale digital input to theCS4328 will produce a full scale output of ± 2 Vresulting in an overall loss of approximately5.2 dB from input to output. Also it is recom-mended that the power connections for eachboard are brought directly from the power sup-ply and not in a "daisy-chain" manner fromboard to board.

Connecting the CDB4328 to the CDB5336/7/8/9can be accomplished using one of two methods:

CDB4328

24 DS62DB2

7

DG

ND

M0

M1

M2

M3

23 24 18 17

VD

+

FIL

TR

10C

1220

VD

+V

A+

0.1

uFC

11722

R9

10

+5V

Ana

log

1.0

uFC

9

+0.

1 uF

C10

MC

K

SD

AT

A

SC

K

FS

YN

C47

kR

2

23

1

Pin

20,

U1

47 k

R1

56

Pin

19,

U1

47 k

R13

98

Pin

18,

U1

R12

1211

14

VD

+ C29

0.1

uF

4 10 1374

HC

126

U3

11 12 26 19

1 3 5 7

2 4 6 8

JP3

VD

+

12.

288

MH

z GN

DV

CC

NC

U6

C13

0.1

uFC

141.

0 uF

+14

18 7

R3

47k

Pin

14,

U1

SE

L

Cha

nnel

Sta

tus

S1

VD

+

Err

or In

form

atio

nU

7A

21

TP

TP

TP

TP

VE

RF

UC

ER

F28

141

1625

8A

GN

D 21

1:1

Dig

ital

Inpu

t

1 2

3 4

110

R8

Sch

ott 6

7125

450

Pul

se P

E65

612

C0/

E0

Ca/

E1

Cb/

E2

Cc/

F0

Cd/

F1

Ce/

F2

CS

LR/F

CK

RX

P

RX

N

VD

+ R7

L R

FC

K47

kT

PC

BL

15 9 1013

89

1011

1213

VD

+

VD

+

0.1

uFC

28

U7

D,E

,F

14 7

U2

CS

8412

841

2

EX

TC

LK

JP1

47 k

1k0.

047

uF

D4

89

560

D5

65

560

D6

1011

560

D7

43

560

D8

1213

560

D9

21

560

VD

+7

Pin

SIP

RP

1V

D+

C27

0.1

uF

7

6 5 4 3 2 27U

474

HC

04

Fig

ure

3.

CS8

412

Dig

ital

Aud

io R

ecei

ver

Con

nect

ions

CDB4328

DS62DB2 25

the trace at the SDATA BNC connector andplace a jumper between the SDATA BNC andU8 pin 11. CMODE is set LOW for a masterclock of 256 times the sample rate. P7 musthave both the internal and external jumpers in-stalled. This will route the master clock to theEXTCLKIN BNC for connection to theCDB4328 MCLK.

If a CS5336/8 is installed an additional modifi-cation is required to invert the SCLK prior totransmission to the CDB4328. This can be im-plemented as follows: cut the trace at the SCLKBNC and install a jumper between U7 pin 4 andthe SCLK BNC.

CDB5336/7/8/9 and CDB4328 Interconnectionfor Method 2

Shielded coaxial cables with BNC connectorsshould be used to make the following connec-tions: L/R to L/R, SCLK to SCLK, SDATA toSDATA, EXTCKIN to MCLK.

CDB4328 Interfacing to the CDB5326/7/8/9

A method of interfacing the CDB5326/7/8/9 andthe CDB4328 requires a direct interface throughthe EXTCLKIN, SCLK, SDATA, and L/R BNCconnectors. This technique requires modifica-tions to the CDB5326/7/8/9 to derive the properclock frequencies. This is done by utilizing a12.288 MHz clock and supplying a clock to theCDB5326/7/8/9 at 6.144 MHz.

CDB4328 Configuration

The CS4328 must be set to receive data in for-mat 2 (DIF1 high and DIF0 low). Modify thejumpers located near pins 12 and 13 of theCS4328. JP2 sets the clock to sample frequencyratio (CKS) on the CS4328 and is set low for a256 ratio.

JP3 selects the source of SDATA, SCLK and L/Rthat will be provided to the converter and should

be removed to access the multiple clocks fromthe CDB5326/7/8/9. Remove the 12.288 MHzoscillator (U8).

CDB5326/7/8/9 Configuration

Remove the clock source jumper (P2). Removethe 6.144 MHz oscillator (U2) and replace withthe 12.288 MHz oscillator from the CDB4328.

Install a divide by 2 function on theCDB5326/7/8/9 digital patch area. Use a74HC74 with the D input connected to the Qoutput. Connect the oscillator output to the74HC74 clock input. Connect the Q output toU1 pin 23.

Position P2 to connect the oscillator output tothe EXTCLKIN.

CDB5326/7/8/9 and CDB4328 Interconnection

Shielded coaxial cables with BNC connectorsshould be used to make the following connec-tions: L/R to L/R, SCLK to SCLK, SDATA toSDATA, EXTCLKIN to MCLK.

CDB4328

DS62DB2 27

Figure 4. Top Ground Plane Layer (NOT TO SCALE)

CDB4328

28 DS62DB2

Figure 5. Bottom Trace Layer (NOT TO SCALE)

CDB4328

DS62DB2 29

Figure 5. Silk Screen Layer (NOT TO SCALE)

CDB4328

30 DS62DB2

• Notes •

Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation