cse 205: digital logic design

CSE 205: Digital Logic Design

CSE 205: Digital Logic DesignPrepared By,Dr. Tanzima Hashem, Assistant Professor, CSE, BUETUpdated By, Fatema Tuz Zohora, Lecturer, CSE, BUETSequential CircuitsConsist of a combinational circuit to which storage elements are connected to form a feedback pathState: the state of the memory devices now, also called current stateNext states and outputs are functions of inputs and present states of storage elements

Alarm control systemSuppose we wish to construct an alarm circuit such that the output remains active (on) even after the sensor output that triggered the alarm goes offThe circuit requires a memory element to remember that the alarm has to be active until a reset signal arrives

Two Types of Sequential CircuitsAsynchronous sequential circuitDepends upon the input signals at any instant of time and their change orderMay have better performance but hard to design

Synchronous sequential circuitDefined from the knowledge of its signals at discrete instants of timeMuch easier to design (preferred design style)Synchronized by a periodic train of clock pulses

Synchronous Sequential CircuitsMemory elementsLatch - a level-sensitive memory elementSR latchesD latchesFlip-Flop - an edge-triggered memory element

Master-slave flip-flopEdge-triggered flip-flop

RAM and ROM a mass memory elementCCLKPositive EdgeCLKNegative EdgeLatchesA latch is binary storage elementCan store a 0 or 1The most basic memoryEasy to build Built with gates (NORs, NANDs, NOT)Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh7Latches

S R Q0QQ0 0 0010001Q = Q0Initial ValueSR Latch

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh8Latches

S R Q0QQ0 0 0010 0 1100010Q = Q0Q = Q0SR Latch


S R Q0QQ0 0 0010 0 1100 1 0001101Q = 0Q = Q0SR Latch


S R Q0QQ0 0 0010 0 1100 1 0010 1 1101001Q = 0Q = Q0Q = 0SR Latch


S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0010110Q = 0Q = Q0Q = 1SR Latch


S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0101 0 1100110Q = 0Q = Q0Q = 1Q = 1SR Latch


S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0101 0 1101 1 0011100Q = 0Q = Q0Q = 1Q = Q0SR Latch


S R Q0QQ0 0 0010 0 1100 1 0010 1 1011 0 0101 0 1101 1 0001 1 1101100Q = 0Q = Q0Q = 1Q = Q0Q = QSR Latch

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh15SR Latch

S RQ0 0Q00 101 011 1Q=Q=0No changeResetSetInvalid

S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo changePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh16SR Latch

S RQ0 0Q00 101 011 1Q=Q=0No changeResetSetInvalid S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo change

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh17Controlled LatchesC S RQ0 x xQ01 0 0Q01 0 101 1 011 1 1Q=QNo changeNo changeResetSetInvalid

SR Latch with Control Input

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh18Controlled LatchesC DQ0 xQ01 001 11No changeResetSet

CTiming DiagramDQtOutput may changeD Latch (D = Data)

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh19Controlled LatchesC DQ0 xQ01 001 11No changeResetSetCTiming DiagramDQOutput may change

D Latch (D = Data)

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh20Controlled LatchesJK Latch

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh21Controlled LatchesT - Latch

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh22Graphic symbols for latches

Level versus edge sensitivitySince the output of the D latch is controlled by the level (0 or 1) of the clock input, thelatch is said to be level sensitiveAll of the latches we have seen have been level sensitive

It is possible to design a storage element for which the output only changes a the point in time when the clock changes from one value to anotherSuch circuits are said to be edge triggeredControlled latches are level-triggered

Flip-Flops are edge-triggered

Flip-FlopsCCLKPositive EdgeCLKNegative EdgePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh25Flip-Flops

DQQDQQPositive EdgeNegative EdgeEdge-Triggered D Flip-Flop (positive edge triggered)

Three SR LatchPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh26Edge-Triggered D Flip-Flop

Flip-Flops

011No change in output0 S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo changePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh27Edge-Triggered D Flip-Flop

Flip-Flops

0111 S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo changeNo change in outputPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh28Edge-Triggered D Flip-Flop

Flip-Flops

111011100 S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo changeReset StateIf D = 0 when CLK turns from 0 to 1, R 0, Q = 01Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh29Edge-Triggered D Flip-Flop

Flip-Flops

11011100 S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo changeReset StateAfter reaching Reset State, while CLK = 1, what happens if D changes to 1?Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh30Edge-Triggered D Flip-Flop

Flip-Flops

11110001 S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo changeSet StateIf D = 1 when CLK turns from 0 to 1, R 0, Q = 000Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh31Edge-Triggered D Flip-Flop

Flip-Flops

10110001 S RQ0 0Q=Q=10 111 001 1Q0InvalidSetResetNo changeSet StateAfter reaching Set State, while CLK = 1, what happens if D changes to 0?Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh32Flip-Flops: Edge-Triggered D Flip-Flop

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh33Flip-FlopsIf D = 0 when CLK turns from 0 to 1, R 0, Q = 0: reset stateIf D changes while CLK is high flip-flop will not respond to the change.When CLK turns from 1 to 0, Q = 0: , R 1, flip-flop will be in the same state (no change in output).If D = 1 when CLK from 0 to 1, S 0, Q = 1: set state34

JK Flip-Flop

Flip-FlopsD = JQ + KQJQQKPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh35JK Flip-Flop

When J = 1 and K = 0, D = 1 next clock edge sets output to 1.

Flip-FlopsD = JQ + KQ

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh36JK Flip-Flop

When J = 0 and K = 1, D = 0 next clock edge resets output to 0.


Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh37JK Flip-Flop

When J = 1 and K = 1, D= Q next clock edge complements output.


Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh38T Flip-Flop

Flip-FlopsD = TQ + TQ = T QJQQKTDQQ

TD = JQ + KQTQQPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh39Master-Slave Flip-FlopsD Latch(Master)D

CQD Latch(Slave)D

CQQDCLK

CLKDQMasterQSlaveLooks like it is negative edge-triggeredMasterSlaveMaster-Slave D Flip-Flop (negative edge triggered)

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh40Master-Slave Flip-FlopsThe circuit samples the D input and changes its output at the negative edge of the clock, CLK.When the clock is 0, the output of the inverter is 1. The slave latch is enabled and its output Q is equal to the master output Y. The master latch is disabled (CLK = 0).When the CLK changes to high, D input is transferred to the master latch. The slave remains disabled as long as CLK is low. Any change in the input changes Y,but not Q.The output of the flip-flop can change when CLK makes a transition 1 0Master Slave SR Flip-Flop (negative edge triggered)

Master-Slave Flip-Flops

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh42Master Slave JK Flip-Flop (negative edge triggered)

Master-Slave Flip-Flops

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh43Flip-Flop Characteristic TablesDQQDQ(t+1)0011ResetSetJKQ(t+1)00Q(t)01010111Q(t)No changeResetSetToggleJQQKTQQTQ(t+1)0Q(t)1Q(t)No changeTogglePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh44Flip-Flop Characteristic EquationsDQQDQ(t+1)0011Q(t+1) = DJKQ(t+1)00Q(t)01010111Q(t)Q(t+1) = JQ + KQJQQKTQQTQ(t+1)0Q(t)1Q(t)Q(t+1) = T QPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh45Asynchronous Reset

Flip-Flops with Direct InputsDQQRResetRDCLKQ(t+1)0xx0100111Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh46Asynchronous Reset

Connect the Reset Input such that Reset=0 willimmediately makeQ=0 (Reset state)

Flip-Flops with Direct Inputs

011011000Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh47Asynchronous Preset and Clear

Flip-Flops with Direct InputsPRCLRDCLKQ(t+1)10xx001xx111001111DQQCLRResetPRPresetPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh48Analysis of Clocked Sequential Circuits: The State

State = Values of all Flip-Flops

Example A B = 0 0

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh49Analysis of Clocked Sequential Circuits: TerminologyState Equation: A state equation (transition equation) specifies the next state as a function of the present state and inputs.State Table: A state table (transition table) consists of: present state, input, next state and output.State Diagram: The information in a state table can be represented graphically in a state diagram. The state is represented by a circle and the transitions between states are indicated by directed lines connecting the circles. Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh50Input Equation:DA = A(t)x(t) + B(t)x(t)DB = A(t)x(t)

Output Equation:y(t) = [A(t)+ B(t)] x(t) = (A + B) x

State Equation:A(t+1) = DA = A(t) x(t)+B(t) x(t) = A x + B xB(t+1) = DB = A(t) x(t) = A x

Analysis of Clocked Sequential Circuits: State/Transition Equations

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh51Analysis of Clocked Sequential Circuits: State /Transition Table

A(t+1) = A x + B xB(t+1) = A x y(t) = (A + B) xPresent StateInputNext StateOutputABxABy000001010011100101110111t+1tt0 0 00 1 00 0 11 1 00 0 11 0 00 0 11 0 0Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh52Analysis of Clocked Sequential Circuits: State/Transition Table

A(t+1) = A x + B xB(t+1) = A x y(t) = (A + B) xPresent StateNext StateOutputx = 0x = 1x = 0x = 1ABABAByy00000100010011101000101011001010t+1ttPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh5354

0 01 00 11 10/00/11/01/01/01/00/10/1ABinput/outputPresent StateNext StateOutputx = 0x = 1x = 0x = 1ABABAByy00000100010011101000101011001010Analysis of Clocked Sequential Circuits: State DiagramPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh54Example:

Analysis of Clocked Sequential Circuits: D Flip-FlopsDQQ

x

CLKyAPresent StateInputNext StateAxyA000001010011100101110111011010010100,1100,1101,1001,10State Equation: A(t+1) = DA = A x yInput Equation: DA = A x yNo Output column / Output Equation(Output = Next State) Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh55Example:

Analysis of Clocked Sequential Circuits: JK Flip-Flops

JA = BKA = B xJB = xKB = A xA(t+1) = JA QA + KA QA = AB + AB + AxB(t+1) = JB QB + KB QB = Bx + ABx + ABxPresent StateI/PNext StateFlip-FlopInputsABxABJAKAJBKB0000010100111001011101110 0 1 00 0 0 11 1 1 01 0 0 10 0 1 10 0 0 01 1 1 11 0 0 00 10 01 11 01 11 00 01 1Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh56Analysis of Clocked Sequential Circuits: JK Flip-Flops

Present StateI/PNext StateFlip-FlopInputsABxABJAKAJBKB0000010100111001011101110 0 1 00 0 0 11 1 1 01 0 0 10 0 1 10 0 0 01 1 1 11 0 0 00 10 01 11 01 11 00 01 10 01 10 11 010101001Example:

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh57Example:

Analysis of Clocked Sequential Circuits: T Flip-FlopsTA = B xTB = xy = A BA(t+1) = TA QA + TA QA = AB + Ax + ABxB(t+1) = TB QB + TB QB = x B

Present StateI/PNext StateF.FInputsO/PABxABTATBy0000010100111001011101110 00 10 01 10 00 10 01 10 00 10 11 01 01 11 10 000000011Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh58Analysis of Clocked Sequential Circuits: T Flip-Flops

Present StateI/PNext StateF.FInputsO/PABxABTATBy0000010100111001011101110 00 10 01 10 00 10 01 10 00 10 11 01 01 11 10 0000000110 00 11 11 00/01/00/01/01/01/10/00/1Example:

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh59PracticeA sequential circuit with two D flip-flops A and B. two inputs x and y, and one output z is specified by the following next-state and output equationsA(t + 1) = x y + x BB(t + 1 ) = x A + x Bz = B

Draw the logic diagram of the circuit.List the stale table for the sequential circuit.Draw the corresponding state diagram.Practice

Practice

Practice

Mealy and Moore ModelsThe Mealy model: the outputs are functions of both the present state and inputsThe outputs may change if the inputs change during the clock pulse period.The outputs may have momentary false values unless the inputs are synchronized with the clocks.The Moore model: the outputs are functions of the present state onlyThe outputs are synchronous with the clocks.

Mealy and Moore Models

Block diagram of Mealy and Moore state machinePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh65Mealy and Moore ModelsPresent StateI/PNext StateO/PABxABy000000001010010001011110100001101100110001111100MealyFor the same state,the output changes with the inputPresent StateI/PNext StateO/PABxABy000000001010010010011100100100101110110111111001MooreFor the same state,the output does not change with the inputPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh66Moore State DiagramState / Output0 0 / 00 1 / 01 1 / 11 0 / 001110001Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh67State reductionSequential circuit analysisCircuit diagram state table (or state diagram)Sequential circuit designState diagram (state table) circuit diagramRedundant state may exist in a state diagram (or table)By eliminating them reduce the # of logic gates and flip-flopsPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh68Eastern Mediterranean University

State ReductionOnly the input-output sequences are important.Initial state is aIn state a, for input=0, output is 1, and next state is aIn state a, for input=1, output is 0, and next state is b..and so on.

State diagramState:aabcdeffgfgaInput:01010110100Output:00000110100Initial State is aPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh69Eastern Mediterranean University

State ReductionTwo circuits are equivalentHave identical outputs for all input sequences;The number of states is not important.

State diagramState:aabcdeffgfgaInput:01010110100Output:00000110100Initial State is aPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh70

State ReductionEquivalent statesTwo states are said to be equivalentFor each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state.One of them can be removed.

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh71

State Reduction

1. e = g (remove g);2. Replace all g by ePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh72

State ReductionReducing the state tabled = f (remove f);


State ReductionThe reduced finite state machine

State:aabcdeddedeaInput:01010110100Output:00000110100Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh74

State Reduction: Implication TableThe state-reduction procedure for completely specified state tables is based on the algorithm that two states in a state table can be combined into one if they can be shown to be equivalent. There are occasions when a pair of states do not have the same next states, but, nonetheless, go to equivalent next states

The checking of each pair of states for possible equivalence in a table with a large number of states can be done systematically by means of an implication table.Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh75(a, b) imply (c, d) and (c, d) imply (a, b). Both pairs of states are equivalent; i.e., a and b are equivalent as well as c and d.76

State Reduction: Implication Table


State Reduction:Implication Table


bcdefgabcdef On the left side along the vertical are listed all the states defined in the state table except the firstacross the bottom horizontally are listed all the states expect the lastPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh78

bcdefgabcdefd-ed-ewe place a cross in any square corresponding to a pair of states whose outputs are not equal for every input. Otherwise, we enter the pairs of states that are implied by the pair of states representing the squares.0we place a tick in any square corresponding to a pair of states whose outputs and next states are equal for every input. Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh79

d-ca-bc-ea-bbcdefgabcdefd-ed-ePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh80




d-e


d-e

d-ca-bc-ea-bbcdefgabcdefd-ed-e The next step is to make successive passes through the table to determine whether any additional squares should be marked with a cross or tick A square in the table is crossed out if it contains at least one implied pair that is not equivalentPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh85

State Reduction: Implication TableFinally, all the squares that have no crosses are recorded with check marks. The equivalent states are: (a, b), (d, e), (d, g), (e, g).

We now combine pairs of states into larger groups of equivalent states. The last three pairs can be combined into a set of three equivalent states (d, e, g) because each one of the states in the group is equivalent to the other two. Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh86

d-e


State Reduction: Implication TableThe final partition of these states consists of the equivalent states found from the implication table, together with all the remaining states in the state table that are not equivalent to any other state: (a, b) (c) (d, e, g) (f)


State AssignmentAssign coded binary values to the states for physical implementationFor a circuit with m states, the codes must contain n bits where 2n >= mUnused states are treated as dont care conditions during the designDont cares can help to obtain a simpler circuitThere are many possible state assignmentsHave large impacts on the final circuit sizePrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh89

Popular State Assignment


State Assignment

Any binary number assignment is satisfactory as long as each state is assigned a unique numberUse binary assignment 1


Design ProcedureDerive a state diagram for the circuit from specificationsReduce the number of states if necessaryAssign binary values to the statesObtain the binary-coded state tableChoose the type of flip-flop to be usedDerive the simplified flip-flop input equations and output equationsDraw the logic diagramPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh92

Design ProcedureDerive a state diagram for the circuit from specificationsReduce the number of states if necessaryAssign binary values to the statesObtain the binary-coded state tableChoose the type of flip-flop to be usedDerive the simplified flip-flop input equations and output equationsDraw the logic diagramPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh93Design of Clocked Sequential CircuitsS0 / 0S1 / 0S3 / 1S2 / 001100101StateA BS00 0S10 1S21 0S31 1Example:Detect 3 or more consecutive 1s

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh94Design of Clocked Sequential CircuitsPresent StateInputNext StateOutputABxABy0000010100111001011101110 0 00 1 00 0 01 0 00 0 01 1 00 0 11 1 1S0 / 0S1 / 0S3 / 1S2 / 001100101Example:Detect 3 or more consecutive 1s

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh95Example:Detect 3 or more consecutive 1s

Design of Clocked Sequential CircuitsPresent StateInputNext StateOutputABxABy0000010100111001011101110 0 00 1 00 0 01 0 00 0 01 1 00 0 11 1 1A(t+1) = DA (A, B, x) = (3, 5, 7)B(t+1) = DB (A, B, x) = (1, 5, 7)y (A, B, x) = (6, 7)Synthesis using D Flip-FlopsPrincess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh96Design of Clocked Sequential Circuits with D F.F.DA (A, B, x) = (3, 5, 7) = A x + B xDB (A, B, x) = (1, 5, 7) = A x + B xy (A, B, x) = (6, 7) = A BSynthesis using D Flip-FlopsB0010A0110xB0100A0110xB0000A0011xExample:Detect 3 or more consecutive 1s


Design of Clocked Sequential Circuits with D F.F.DA = A(t+1) = A x + B xDB = B(t+1) = A x + B x y = A BSynthesis using D Flip-Flops

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh9899Flip-Flop Excitation TablesPresent StateNext StateF.F.InputQ(t)Q(t+1)JK000110110 x1 xx 1x 0

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh99100Flip-Flop Excitation TablesPresent StateNext StateF.F.InputQ(t)Q(t+1)D00011011Present StateNext StateF.F.InputQ(t)Q(t+1)JK000110110 0 (No change)0 1 (Reset)0 x1 xx 1x 001011 0 (Set)1 1 (Toggle)0 1 (Reset)1 1 (Toggle)0 0 (No change)1 0 (Set)Q(t)Q(t+1)T000110110110Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh100Design of Clocked Sequential Circuits with JK F.F.Present StateInputNext StateFlip-FlopInputsABxABJAKAJBKB00000001010100001110100001011111000111110 x0 x0 x1 xx 1x 0x 1x 0JA (A, B, x) = (3)dJA (A, B, x) = (4,5,6,7)KA (A, B, x) = (4, 6)dKA (A, B, x) = (0,1,2,3)JB (A, B, x) = (1, 5)dJB (A, B, x) = (2,3,6,7)KB (A, B, x) = (2, 3, 6)dKB (A, B, x) = (0,1,4,5)Synthesis using JK F.F.0 x1 xx 1x 10 x1 xx 1x 0Example:Detect 3 or more consecutive 1s


Design of Clocked Sequential Circuits with JK F.F.JA = B xKA = xJB = xKB = A + xSynthesis using JK Flip-FlopsB0010AxxxxxBxxxxA1001xB01xxA01xxxBxx11Axx01x


Design of Clocked Sequential Circuits with T F.F.Present StateInputNext StateF.F.InputABxABTA TB000000010101000011101000010111110001111100011010Synthesis using T Flip-Flops01110110TA (A, B, x) = (3, 4, 6)TB (A, B, x) = (1, 2, 3, 5, 6)Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh103Example:Detect 3 or more consecutive 1s

Design of Clocked Sequential Circuits with T F.F.TA = A x + A B xTB = A B + B xSynthesis using T Flip-FlopsB0010A1001xB0111A0101x

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh104Example:3-bit binary counter

Design of Clocked Sequential Circuits with T F.F.

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh105Design of Clocked Sequential Circuits with T F.F.

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh106Design a one-input, one-output serial 2's complementer. The circuit accepts a string of bits from the input and generates the 2's complement at the output. The circuit can be reset asynchronously to start and end the operation.Design of Clocked Sequential Circuits with D F.F.Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh107Design of Clocked Sequential Circuits with D F.F.

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh108Design of Clocked Sequential Circuits with D F.F.

Princess Sumaya University4241 - Digital Logic DesignDr. Bassam Kahhaleh109R

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y

1

T

Q

Q

T

Q

Q

A

B

y

x

Clk

cse 205: digital logic design

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