CSE 464Homework 7, Solutions

Note: Please list at top of first sheet of homework submission anyone or anything from which you obtainedany help for this homework assignment other than the text and class notes/discussion. Please give a wordor two as to the nature of the help (e.g.: discussed problems, copied verbatim, whatever). Acknowledgingsource of help is a requirement for this assignment, and for all assignments in this course. It has no effecton your grade.

1. ("Classic" on-chip view of timing that we all know and love... I hope!) Assume thateach flip-flop has a setup time of 2 ns, a hold time of 3 ns and a clock-to-output delayof 5 ns. Further assume that each AND gate has a delay of 2 ns and each inverter hasa delay of 1 ns. How fast (in MHz) can clock the following circuits. Also discusswhat constraints are placed on any inputs (i.e. when they must be stable).

a.

r^--KNV

FO

D Q

PCLOCKQ?

tcy = tDcq + tDci + ts = 5 + 1 + 2 = 8 ns or 125 MHz

b.

AD—ClOCKQ

tcv = 5 + 2 + 2 = 9 ns or about 111 MHzicy

and A must be stable toci + ts = 5 ns before clock toclock.

i - toci = 1 ns after

c.

roD Q

PAM 02

FO

0 Q

>c

BD-

CLOCK|>

There are two paths to look at but from the first to second flip-flop isobviously the worst case as it has more logic delay. Here, tcy = 9 ns,again, for 111 MHz maximum clock frequency. B must be stable from5 ns before to 1 ns after clock, again.

d. Repeat part C assuming a worst-case clock skew of 1 ns between the flip-flops.

Here, we need to add the skew to the longest path to account for theworst case of the first flip-flop being clocked late and the second oneearly so now we have tcy=10 ns with a clock frequency of 100 MHz.

As for B, we need to ensure that it arrives in time for the clock at thesecond flip-flop. If this flip-flop was clocked 1 ns after the referenceclock, then we need to be sure the input was stable for an extra 1 nsafter the clock. Likewise, if it was clocked 1 ns before, we need B thereearlier. Hence, we need to add the skew to both sides and ensure B isstable 5 ns before to 2 ns after the clock.

2. EE462 uses Xilinx XC3S500E-5 FPGAs in their designs. Consider the question ofmaximum clock rate that can be used if two of these ICs communicate with eachother in a common clock domain. Assume the clocks for the two ICs are generated bya common clock buffer with (including oscillator that drives the buffer) skew betweenclock buffer outputs of+/-300ps, jitter of lOOps peak (200ps peak-to-peak), clockdistribution traces rratched within 0.2 inches, and loads at the clock receivers of 4pF+/-2pF. Clock distribution transmission line impedance is 50 Ohms, propagationvelocity is lft/2ns. ^Vliat is minimum delay allowed from clock to the output of oneFPGA? What is maximum clock frequency allowed? Use FPGA data for 12mALVCMOS25, standsrd I/O. The XC3S500E-5 data sheet is available at:http://www.xilinx.com/support/documentation/datasheets/ds312.pdf. You can findthe delay values in the section on switching characteristics starting on page 129 andmoving on from there. Yes, you need to think about what parameters are important,here, and find them.

From CLKA toskew and jittercapacitive loads:

CLKB where these are the clocks of the two FPGAs, we havefrom the clock buffer, plus trace skew and skew due to the

Buffer skew:trace skew (± 0.2")cap. Loads (2-6 pf)Total:

Jitter:

Tk = 533+200 = ±

There are two cases

Parametertdcq (Tickof)

± 300 ps0.2"*(2ns/12") = ±33ps4 pf* 50 Q = ± 200 ps± 533 ps

± 200 ps

733 ps

, really: one with DCM and one without.

with DCM without DCM

tk (from above)TOTAL:MAXF:

3.2.0.5;It

91ns25 ns733ns993ns7 MHz

4.98 ns4.00 ns0.733 ns9.713 ns103MHz

haveNow, the minimumto B too fast, wewith no DCM. Sineno way we canthe parts.

delay is that which would violate hold time. So, if A outputsa problem. The hold time is 0.07 ns or -0.77 ns for the case

we have a delay of at least 3 ns for tdcq, we are fine. There isviolalte hold time even if we consider the skew of 533 ps between

Problem 9.4 from text. Note that two flip-flops in series with the clock to one of theminverted could also be used. This allows use of conventional flip-flops which may bemore readily available (total of 4 latches, two for each flop), but is not as efficient asthe given implementation which uses three latches. This dual-flip-flop scheme is usedin some low speed applications (JTAG serial test bus and configuration load forFPGAs) where speed is not important, and where clock skew may be hard to control.Although requiring more flops than conventional clocking, the savings in designanalysis and clock skew control can be a very good tradeoff in some low performanceapplications.

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4. Problem 9.5 from the text.

5. If two MPC961 clocc drivers are used in parallel to drive multiple clock signals froma single oscillator, what is worst case skew and jitter at the clock receivers? Allinterconnections are series terminated transmission lines with length tolerance of+/0.1 inch, propagation velocity of 2 ns/ft, and inputs have capacitance tolerance of+1-2 pF. Note that with a circuit such as this, it's possible to generate an "early clock"by making the feedback connection longer than the clock distribution connections.http://www.idt.com4roducts/files/3776827/MPC961 C.pdf?CFID=631618&CFTOKE

6.

N=71643627

Problem 9-3 Dally &MHz ±A where A is :MHz where this circuit

Poulton. To clarify, assume that you won't run faster than 500some small range. Do find the ranges of frequency less than 500

may also work (hint, there are four ranges, total).

a.b.

7. A high-speed communication system with a 200Mhz clock and many asynchronousinputs exhibits occasional failures. An experiment is performed in which the systemis run continuously for 24 hours with clock period of 4.8ns, then 24 hours with clockperiod of 5ns, then 24 hours with clock period of 5.2ns. The number of failures forthe 24 hour periods are 27, 5, and 1 respectively.

Does this prove that metastability is the cause of the failures?Assuming metastability is the cause of the failures, estimate the value oftau_s (resolving time constant) for flip-flops in this system if all flip-flopsare identical. To simplify the calculation, you may take the clockfrequency, but not the waiting time, as approximately constant (a fewhundred ps difference in clock frequency makes very small difference incalculated probability of failure).If the allowed failure rate is to be less than one failure per 100 years, what

clock period would be required?Since increasing the clock period may not be acceptable, suggest design

changes other than increasing the clock period that might be used to obtainan acceptable failure rate.

d.

8. Problem 10-1 Dally & Poulton

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