cse140: components and design techniques for digital ...for digital systems sequential circuit...

Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques

for Digital Systems

Sequential Circuit Introduction

Latches and Flip-Flops

Instructor: Mohsen Imani


C1 C2

CLK

x(t)

y(t)

Mealy Machine

S(t)

C1 C2

CLK

x(t) y(t)

Moore Machine

S(t)

Mealy and Moore Machines

Output is the only function of current state

ONLY!

Output is the function of the present state

as well as the input!

yi(t) = fi(X(t), S(t))yi(t) = fi(S(t))


3

Design a FSM which detects pattern 101 using D-Flip Flop and combinational

logic

FSM Example


4

FSM Example


Wristwatch Display FSM

5

A wristwatch display can show one of four items:

time, alarm, stopwatch or date, controlled by two

signals s1 and s0:

• 00 for time, 01 for alarm, 10 for stopwatch and

11 for date.

• Assume s1 and s0 control an Nbit MUX that

passes through the appropriate register.

• Pressing a button B (which sets B = 1)

sequences the display to the next item.

• For example, if the presently displayed item is

the date, the next item is the current time.



• Create a state diagram for an FSM describing this

sequencing behavior, having an input bit B, and two outputs

bits s1 and s0. Use short but descriptive names for each

state. Displaying time should be the initial state.

6

• Is it a Moore

or a Mealy

machine?



7

• State table with assignments



8

• Excitation table



B \ Q1 Q0 00 01 11 10

0 0 0 1 1

1 0 1 0 1

9

B \ Q1 Q0 00 01 11 10

0 0 1 1 0

1 1 0 0 1

• D1 = B’Q1 + Q1Q0’ + BQ1’Q0

• D0 = B’Q0 + BQ0’



10

Q1

Q0

D1

D0

CLK

B


Flip Flops

11


Flip Flops

12


Q1Q0\x 0 1

00 01,0 00,0

01 10,0 00,0

10 10,0 11,0

11 01,1 00,1

Q1(t+1)Q0(t+1), y

ID Q1Q0x D1 D0 y

0 000 0 1 0

1 001 0 0 0

2 010 1 0 0

3 011 0 0 0

4 100 1 0 0

5 101 1 1 0

6 110 0 1 1

7 111 0 0 1

S(t)\x 0 1

S0 S1,0 S0,0

S1 S2,0 S0,0

S2 S2,0 S3,0

S3 S1,1 S0,1

Moore Mars Life Recognizer: Summary

S1

0

S0

0

0

1

0

1S2

0

0

1

S3

1

1 0


id Q1Q0x Q1+ Q0+ y

0 000 0 1 0

1 001 0 0 0

2 010 1 0 0

3 011 0 0 0

4 100 1 0 0

5 101 1 1 0

6 110 0 1 1

7 111 0 0 1

T-Flip Flop


15


Timing Constraints in Sequential Designs

16


• Our seemingly logically correct design can go wrong –

signals don’t travel in zero time

• We next look at timing constraints for combinational and

sequential logic.

Combinational

CLK

Timing Constraints in Sequential Circuit Designs


Combinational Logic Timing

18

I. Min delay of a gate, also called contamination delay: tcd

Minimum time from when an input changes until the output starts to change

II. Max delay of a gate, also called propagation delay: tpd

Maximum time from when an input changes until the output is guaranteed to reach

its final value (i.e., stop changing)


Combinational Logic: Output Timing Constraints

19

A

B

C

D

Y

Which path in the above circuit determines the contamination

delay of the circuit (assuming the delay of all the gates is the

same)?

A. Blue path

B. Red path

C. Both

D. Neither


Combinational Logic: Output Timing Constraints

20

A

B

C

D

Y

Which path in the above circuit determines the propagation

delay of the circuit (assuming the delay of all the gates is the

same)?

A. Blue path

B. Red path

C. Both

D. Neither


D-FF Input Constraints: Setup and Hold Times

21

CLK

tsetup

D

thold

ta

I. Setup time: tsetup

Time before the clock edge that data must be stable (i.e. not change)

II. Hold time: thold

Time after the clock edge that data must be stable

Aperture time: ta

Time around clock edge that data must be stable (ta = tsetup + thold)

D

Q

Q’

R

SD

C

D latch

Q

R

SD

C

D latch

Q


Output Timing Constraints

I. Min delay of FF, also called contamination delay or min CLK to Q delay: tccq

Time after clock edge that Q might be unstable (i.e., starts changing)

II. Max delay of FF, also called propagation delay or maximum CLK to Q delay: tpcq

Time after clock edge that the output Q is guaranteed to be stable (i.e. stops

changing)

CLK

tccq

tpcq

Q

22

D

Q

Q’


The timing of which of the following signals can cause a

setup-time violation ?

23

A. The input signal D(t)

B. The output signal Q(t)

C. Both of the above

D. None of the above

DQ

Q’

D(t)

CLK

Q(t)

Comb

Logic


Causes of Timing Issues in Sequential Circuits

• Input to a FF comes from the output of another FF through

a combinational circuit

• The FF and combinational circuit have a min & max delay

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Which of the following

violations occurs if max delay

of R1 is zero & max delay of

the combinational circuit is

equal to the clock period?

A. Hold time violation for R2

B. Setup violation for R2

C. Hold time violation for R1

D. Setup violation for R1

E. None of the above


Setup Time Constraint




CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Setup time constraint:

Tc ≥ tsetup+ max delay(FF) +

max delay(combinational)

Tc ≥ tpcq + tpd + tsetup


Causes of Timing Issues in Sequential Circuits




CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Which of the violations would

occur if the min delay of R1

was zero and the combinational

circuit was just a wire?

A. Hold time violation for R2

B. Setup violation for R2

C. Hold time violation for R1

D. Setup violation for R1

E. None of the above


Hold Time Constraint




CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2

(b)

Tc

Hold time constraint:

thold < min delay(FF) +

min delay(combinational)

thold < tccq + tcd


FF Timing Parameters

28

R1 Combinational

CLK

R2

CLK

D1 Q1 D2

Once a flip flop has been built, its timing characteristics

stay fixed: tsetup , thold, tccq, tpcq

What about the clock? Does the clock edge arrive at the

same time to all the D-FFs on the chip?


• The clock doesn’t arrive at all registers at the same time

• Skew: difference between the two clock edges

• Perform the worst case analysis

tskew

CLK1

CLK2

CL

CLK2CLK1

R1 R2

Q1 D2

CLKdelay

CLK

Clock Skew


• In the worst case, CLK2 is earlier than CLK1

• tpcq is max delay through FF, tpd is max delay through logic

CLK1

Q1

D2

Tc

tpcq

tpd

tsetup

tskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

Tc ≥ tpcq + tpd + tsetup + tskew

tpd ≤ Tc – (tpcq + tsetup + tskew)

Setup Time Constraint with Skew


• In the worst case, CLK2 is later than CLK1

• tccq is min delay through FF, tcd is min delay through logic

tccq

tcd

thold

Q1

D2

tskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

CLK1

tccq + tcd > thold + tskew

tcd > thold + tskew – tccq

Hold Time Constraint with Skew


CLK CLK

A

B

C

D

X'

Y'

X

Y

per

gate

Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 25 ps


Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz


tccq + tcd > thold ?

(30 + 25) ps > 70 ps ? No!

Timing Analysis Example


Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps


Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz


tccq + tcd > thold ?

(30 + 50) ps > 70 ps ? Yes!

Timing Analysis Example

CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:

per

gate


Sequential Circuit Design Summary

• SR Latch, D Latch, D-FF

• Design procedure for FSMs

1. Capture FSM

2. Create state table

3. Assign the states

4. Excitation table

5. Implement the combinational logic

• Mealy vs. Moore FSM

• Non-ideal properties of FFs

– Setup/hold time constraints

– Maximum operating frequency

– Clock skew34


15 cents for candy! Watch out – no change!

• Moore machine

– outputs associated with

state

35

0¢[0]

10¢[0]

5¢[0]

15¢[1]

N’ D’ + Reset

D

D

N

N+D

N

N’ D’

Reset’

N’ D’

N’ D’

Reset

0¢

10¢

5¢

15¢

(N’ D’ + Reset)/0

D/0

D/1

N/0

N+D/1

N/0

N’ D’/0

Reset’/1

N’ D’/0

N’ D’/0

Reset/0

• Mealy machine

– outputs associated with transitions


Example: Moore implementation

• Encode states and map to logic

36

0 0 1 1

0 1 1 1

X X 1 X

1 1 1 1

Q1D1

Q0

N

D

0 1 1 0

1 0 1 1

X X 1 X

0 1 1 1

Q1D0

Q0

N

D

0 0 1 0

0 0 1 0

X X 1 X

0 0 1 0

Q1Open

Q0

N

D

present state inputs next state outputQ1 Q0 D N D1 D0 open0 0 0 0 0 0 0

0 1 0 1 01 0 1 0 01 1 – – –

0 1 0 0 0 1 00 1 1 0 01 0 1 1 01 1 – – –

1 0 0 0 1 0 00 1 1 1 01 0 1 1 01 1 – – –

1 1 – – 1 1 1


Example: Mealy implementation

37

0¢

10¢

5¢

15¢

Reset/0

D/0

D/1

N/0

N+D/1

N/0

N’ D’/0

Reset’/1

N’ D’/0

N’ D’/0

Reset/0present state inputs next state output

Q1 Q0 D N D1 D0 open0 0 0 0 0 0 0

0 1 0 1 01 0 1 0 01 1 – – –

0 1 0 0 0 1 00 1 1 0 01 0 1 1 11 1 – – –

1 0 0 0 1 0 00 1 1 1 11 0 1 1 11 1 – – –

1 1 – – 1 1 1

0 0 1 0

0 0 1 1

X X 1 X

0 1 1 1

Q1Open

Q0

N

D


FSM design: Multiple input counter

• Given FSM of a multiple input counter, design the circuit

implementing its functionality

00

State

01 11 10

Inputs

00

01

11

10

00

State

01 11 10

Input

00 00 00 01 01

01 01 11 00 11

11 11 11 11 00

10 10 01 00 10

38

present next state output

state 00 01 10 11

S0 S0 S1 S2 S3 1

S1 S0 S3 S1 S3 0

S3 S1 S0 S0 S3 0S2 S1 S3 S2 S0 1

S0 S1

S2 S3

00

00

01

10 11

10

01,10

10

11

01

0011

00


Multiple input counter: Logic for D-FF

• Derive logic equations for inputs of

D-FF00

State

01 11 10

Input

00 00 00 01 01

01 01 11 00 11

11 11 11 11 00

10 10 01 00 10

D1 00 01 11 10

I1I0

00

01

11

10

39

D0 00 01 11 10

I1I0

00

01

11

10

cse140: components and design techniques for digital ...for digital systems sequential circuit...

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