CSE351 Course Project Tutorial

By Dongyuan Zhan

dzhan@cse.unl.edu

Objectives

• The three projects will lead you to eventually create your own prototype OS on a bare-system FPGA board.

• Gain genuine understanding of the OS kernel principles from hands-on experience.

• Practice efficient teamwork and effective project management skills that make your work splendid.

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Overview

• One Lab + Three Projects (on a team basis, accounting for 40% of your final grade)– Pre-project Lab (0%, by 09/21) : to prepare

you for the projects

– Project I (5%, by 10/05): to design a timer interrupt handler

– Project II (20%, by 11/13): to devise multithreading and scheduling mechanisms

– Project III (15%, by 12/07): to provide a synchronization mechanism for the coordination among multiple threads

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Tasks

• 18 teams have been formed, with 2-3 members in each group– http://www.flickr.com/photos/66755201@N04/

sets/72157627524789258/detail/

• Each group should have a team leader who schedules and coordinates group events and submits your work to the hand-in system.

• Each team will be provided ≥2 FPGA boards. You can use your personal computer or a Lab machine to manipulate the boards, as long as the required software is installed.

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Teams

• Hardware– the Altera DE-2/DE-1 board

• Software– Quartus-II Web Edition 11.0sp1

» It also includes the Nios-II v11.0 Software Build Tools for Eclipse

» https://www.altera.com/download/software/quartus-ii-we/11.0sp1 (download registration required)

– Virtualbox (only for Mac users)» http://www.virtualbox.org/wiki/Mac%20OS%20X

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Infrastructure

• Software– USB Blaster Driver

» It enables DE-2 to communicate with your computer

» How to install it can be found at

• WINXP: http://www.altera.com/download/drivers/usb-blaster/dri-usb-blaster-xp.html

• WIN7/VISTA: http://www.altera.com/download/drivers/usb-blaster/dri-usb-blaster-vista.html

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Infrastructure

• Software– Nios-II Soft-Core CPU

» It is essentially a VHDL/Verilog design that configures the FPGA to function as a CPU.

» DE2 Version: http://cse.unl.edu/~dzhan/wiki/images/DE2_NIOS-II.zip

» DE1 Version: http://cse.unl.edu/~dzhan/wiki/images/DE1_NIOS-II.zip

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Infrastructure

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FPGA

Power Button

USB Blaster Port Altera DE-2 Board

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FPGA

Power Button

USB Blaster Port

Altera DE-1 Board

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• Download the Nios-II Soft CPU to the FPGA Platform

– http://cse.unl.edu/~dzhan/wiki/index.php5/Cse351:Fall_2011:Pre_Project_Lab#Download_the_Nios-II_Soft_CPU_to_the_FPGA_Platform

• Create a Nios-II C Project – http://cse.unl.edu/~dzhan/wiki/index.php5/Cse351:Fall

_2011:Pre_Project_Lab#Create_a_Nios-II_C_Project

• Build the Project – http://cse.unl.edu/~dzhan/wiki/index.php5/Cse351:Fall

_2011:Pre_Project_Lab#Build_the_Project

Steps

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• Observe the FPGA Platform Output – http://cse.unl.edu/~dzhan/wiki/index.php5/Cse351:Fall

_2011:Pre_Project_Lab#Observe_the_FPGA_Platform_Output

• Debug the Project – http://cse.unl.edu/~dzhan/wiki/index.php5/Cse351:Fall

_2011:Pre_Project_Lab#Debug_the_Project

Steps

• Pre-Lab (by Sep. 21)– No submission is required

• Project I (by Oct. 5)– The design and report need to be submitted

• Project II (by Nov. 13)– The design and report need to be submitted

• Project III (by Dec. 7)– The design and report need to be submitted

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Milestones

• Following is the grading criteria with a total of 100 points for any projects. But different projects may carry different weights in your final grade.

– Project report: 50%

– Correctness of the program: 40%

– Detailed source code comments and README: 10%

• Typically, all members in a team will get the same grade for a project, unless the team leader or other members report to the lab TA that someone contributes little to the project and he/she should get only a certain percentage (e.g., 90%) of the team’s grade.

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Grading Criteria

• Start as early as you can!

• Do good project management (e.g., risk anticipation)

– http://en.wikipedia.org/wiki/Project_management

• Do efficient teamwork

• Use version control system to manage your source code

– SVN/Mecurial/Git (on Windows/Unix)

– http://code.google.com/hosting/createProject

• Be active in discussing with the TAs

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Some Suggestions for Your Success

• Nios-II Software Developer's Handbook– http://cse.unl.edu/~dzhan/wiki/images/Nios-II_Handbo

ok.pdf

• Instruction Set Reference for Nios-II Soft CPUs– http://cse.unl.edu/~dzhan/wiki/images/Instruction_Set_

Reference_for_Nios-II_Soft_CPUs.pdf

• Hardware Abstraction Layer API Reference– http://cse.unl.edu/~dzhan/wiki/images/

Hardware_Abstraction_Layer_API_Reference.pdf

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Resources

• Using Assembly in the C Source– http://cse.unl.edu/~dzhan/wiki/images/

Using_Assembly_in_the_C_Source.pdf

• C & ASM in Nios-II– http://cse.unl.edu/~dzhan/wiki/images/C

%26ASM_in_Nios-II.pdf

• Altera Document Center– http://www.altera.com/literature/lit-index.html

• Altera Development Forum– http://www.alteraforum.com/

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Resources

Enjoy Your Course Projects!

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Q & A