cset 4650 field programmable logic devices

CSET 4650 CSET 4650 Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Introduction to HDLsIntroduction to HDLsHardware Description LanguagesHardware Description Languages

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Hardware Description LanguagesHardware Description Languages

HHardware ardware DDescription escription LLanguages, or anguages, or HDLHDLs, are s, are languages used to design hardware.languages used to design hardware.

Similar to procedural programming languages (e.g., C)Similar to procedural programming languages (e.g., C)

Digital hardware onlyDigital hardware only

An HDL can also be used to describe the functionality An HDL can also be used to describe the functionality of hardware as well as its implementation. of hardware as well as its implementation.

Leads to simulationLeads to simulation

Allows functional verificationAllows functional verification

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In electronics, a hardware description language or In electronics, a hardware description language or HDL is any language from a class of computer HDL is any language from a class of computer languages for formal description of digital languages for formal description of digital electronic circuits. electronic circuits.

An HDL can describe digital circuit's An HDL can describe digital circuit's operation operation

its design its design

and tests to verify its operation and tests to verify its operation

by means of simulation by means of simulation

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Describe hardware modules at varying Describe hardware modules at varying levels of levels of abstractionabstraction (more later …) (more later …)Structural descriptionStructural description

Textual replacement for schematicTextual replacement for schematicHierarchical composition of modules from primitivesHierarchical composition of modules from primitives

Behavioral/functional descriptionBehavioral/functional descriptionDescribe what module does, not howDescribe what module does, not howSynthesis step generates circuit for moduleSynthesis step generates circuit for module

Simulation semantics are includedSimulation semantics are included

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Levels of Design AbstractionLevels of Design Abstraction

Levels of abstraction for VLSI circuit design. Levels of abstraction for VLSI circuit design. Adapted from Michael D. Ciletti.Adapted from Michael D. Ciletti.

HDLsHDLs

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Why HDLs ?Why HDLs ?

The complexity of logic circuits has increased The complexity of logic circuits has increased dramatically in the past few decadesdramatically in the past few decades

Other forms of EDAs are no longer effectiveOther forms of EDAs are no longer effective

HDLs offer a consistent and efficient method for HDLs offer a consistent and efficient method for both design and synthesisboth design and synthesis

HDLs are relatively easy to learnHDLs are relatively easy to learn

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The principal feature of a hardware description The principal feature of a hardware description language is that it contains the capability to describe language is that it contains the capability to describe the function (behavior) of hardware the function (behavior) of hardware independentindependent of of implementation. implementation.

The great advance with modern HDLs was the The great advance with modern HDLs was the recognition that a single language could be used to recognition that a single language could be used to describe the function of the design and also to describe the function of the design and also to describe the implementation. describe the implementation.

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History of HDLsHistory of HDLs

The first HDL was ISP*, The first HDL was ISP*, invented by C. Gordon invented by C. Gordon Bell and Alan Newell at Bell and Alan Newell at Carnegie Mellon Carnegie Mellon University (CMU) and University (CMU) and described in their book described in their book Computer StructuresComputer Structures published in 1972. published in 1972.

Gordon BellGordon Bell

Alan NewellAlan Newell * Instruction-set Processor language* Instruction-set Processor language

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ISP was the first HDL to use ISP was the first HDL to use the term register-transfer level the term register-transfer level (RTL). (RTL). This term came from the use This term came from the use of ISP in describing the of ISP in describing the behavior of the PDP-8 behavior of the PDP-8 computer as a set of registers computer as a set of registers and logical functions and logical functions describing the transfer of data describing the transfer of data from source register to from source register to destination register. destination register.

DEC PDP-8DEC PDP-8

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Subsequent HDLs included Subsequent HDLs included VVHSIC HSIC HDLHDL (VHDL) which was begun in 1979 (VHDL) which was begun in 1979

VerilogVerilog

ABELABEL

UDLI which was developed by NTTUDLI which was developed by NTT

HiLo, which was the predecessor to VerilogHiLo, which was the predecessor to Verilog

ISP', which was a successor to ISP (implemented by the ISP', which was a successor to ISP (implemented by the N-dot simulator). N-dot simulator).

and more …and more …

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HDLsHDLsISP (circa 1971) - research project at CMUISP (circa 1971) - research project at CMU

Written by Bell and NewellWritten by Bell and NewellSimulation, but no synthesisSimulation, but no synthesis

ABEL (circa 1983) - developed by Data-I/OABEL (circa 1983) - developed by Data-I/OTargeted to programmable logic devicesTargeted to programmable logic devicesNot good for much more than state machinesNot good for much more than state machines

Verilog (circa 1985) - developed by Gateway (absorbed by Verilog (circa 1985) - developed by Gateway (absorbed by Cadence)Cadence)

Similar to Pascal and CSimilar to Pascal and CDelays is only interaction with simulatorDelays is only interaction with simulatorFairly efficient and easy to writeFairly efficient and easy to writeIEEE standardIEEE standard

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HDLsHDLsVHDL (circa 1987) - DoD sponsored standardVHDL (circa 1987) - DoD sponsored standard

Similar to Ada (emphasis on re-use and maintainability)Similar to Ada (emphasis on re-use and maintainability)Simulation semantics visibleSimulation semantics visibleVery general but can get verboseVery general but can get verboseIEEE standardIEEE standardUpdated in 1993Updated in 1993

The current trend is to move away from proprietary The current trend is to move away from proprietary HDLs and towards the two leading standards, HDLs and towards the two leading standards, VHDL and Verilog HDL. VHDL and Verilog HDL.

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HDLs vs. Programming LanguagesHDLs vs. Programming Languages

An HDL is a standard text-based expression of the An HDL is a standard text-based expression of the temporal behavior (timing) and/or (spatial) circuit temporal behavior (timing) and/or (spatial) circuit structure of an electronic system. structure of an electronic system.

In contrast to a software programming language, In contrast to a software programming language, an HDL's syntax and semantics include explicit an HDL's syntax and semantics include explicit notations for expressing time and concurrency notations for expressing time and concurrency which are the primary attributes of hardware.which are the primary attributes of hardware.

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HDLs vs. Programming LanguagesHDLs vs. Programming Languages

An HDL is analogous to a software programming An HDL is analogous to a software programming language, but with subtle differences. language, but with subtle differences.

Both types of language are processed by a compiler. Both types of language are processed by a compiler. An HDL compiler often works in several stages, first An HDL compiler often works in several stages, first producing a logic description file in a proprietary format, producing a logic description file in a proprietary format, then converting that to a logic description file in the then converting that to a logic description file in the industry-standard EDIF format, then converting that to a industry-standard EDIF format, then converting that to a JEDEC-format file. JEDEC-format file.

The JEDEC file contains instructions to a PLD The JEDEC file contains instructions to a PLD programmer for building logic.programmer for building logic.

JJoint oint EElectron lectron DDevice evice EEngineering ngineering CCouncil ouncil

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HDLs vs. Programming LanguagesHDLs vs. Programming LanguagesProgram StructureProgram Structure

Instantiation of multiple components of the same typeInstantiation of multiple components of the same typeSpecify interconnections between modules via schematicSpecify interconnections between modules via schematic

Hierarchy of modulesHierarchy of modules AssignmentAssignment

Continuous assignment (logic always produces an output Continuous assignment (logic always produces an output signal)signal)Propagation delay (signals take time)Propagation delay (signals take time)Timing of signals is important (when does a specific Timing of signals is important (when does a specific signal or set of signals have an effect on the circuit)signal or set of signals have an effect on the circuit)

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HDLs vs. Programming LanguagesHDLs vs. Programming LanguagesData structuresData structures

Size explicitly spelled out - no dynamic structures Size explicitly spelled out - no dynamic structures No pointersNo pointers

ParallelismParallelismHardware is naturally parallel (must support multiple Hardware is naturally parallel (must support multiple threads)threads)Assignments can occur in parallel (not just sequentially)Assignments can occur in parallel (not just sequentially)

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HDLS and Combinational LogicHDLS and Combinational Logic

Modules: specification of inputs, outputs, bidirectional, and Modules: specification of inputs, outputs, bidirectional, and internal signalsinternal signalsContinuous assignment: a gate's output is a function of its Continuous assignment: a gate's output is a function of its inputs at all times (doesn't need to wait to be "called")inputs at all times (doesn't need to wait to be "called")Propagation delay: concept of time and delay in input Propagation delay: concept of time and delay in input affecting gate outputaffecting gate outputComposition: connecting modules together with wiresComposition: connecting modules together with wiresHierarchy: modules encapsulate functional blocksHierarchy: modules encapsulate functional blocksSpecification of don't care conditions (accomplished by setting Specification of don't care conditions (accomplished by setting output to “x”)output to “x”)

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HDLs and Sequential LogicHDLs and Sequential LogicFlip-FlopsFlip-Flops

Representation of clocks - timing of state changesRepresentation of clocks - timing of state changesAsynchronous vs. synchronousAsynchronous vs. synchronous

FSMsFSMsStructural view (FFs separate from combinational logic)Structural view (FFs separate from combinational logic)Behavioral view (synthesis of sequencers)Behavioral view (synthesis of sequencers)

Data-paths = ALUs + registersData-paths = ALUs + registersUse of arithmetic/logical operatorsUse of arithmetic/logical operatorsControl of storage elementsControl of storage elements

ParallelismParallelismMultiple state machines running in parallelMultiple state machines running in parallel

Sequential don't caresSequential don't cares

cset 4650 field programmable logic devices

Documents

functionality of hardware

cdigital hardware onlyan

modern hdls

history of hdlssubsequent

class of computer languages

processor language

single language

vlsi circuit design