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Dicing 101: LEDS, Laser, MEMS

Trends Driving WLP and 3D

Direct Copper Bonding for High Density Applications

Electroless Plating for Improved Test

Solder in the Age of 3D

International Directory of Solder and Flux Suppliers







The International Magazine for the Semiconductor Packaging Industry

Volume 15, Number 6 November December 2011Volume 15, Number 6 November December 2011



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Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com] 1

November December 2011

Volume 15, Number 6

The International Magazine for Device and Wafer-level Test, Assembly, and Packaging

Addressing High-density Interconnection of Microelectronic IC's including 3D packages, MEMS,

MOEMS, RF/Wireless, Optoelectronic and Other Wafer-fabricated Devices for the 21st Century.

In the midst of tremendous technological changesin manufacturing methods, semiconductor

assembly and test houses are still relying on

known and reliable processes. Solders and

uxes have evolved into new forms, but the

principle of forming electrical interconnects

from a self-leveling, molten solder joint

cleaned by an appropriate semiconductor

grade ux remains a core element of the

assembly process. Front cover image

courtesy of Indium Corporation.

FEATURE ARTICLES

Innovation Trends Driving WLP and 3D PackagingSteve Anderson, STATS ChipPAC

Direct Copper Bonding Of High-Density 3D AssembliesGilbert Lecarpentier, SET, Marc Legros and Mayerling Martinez, CEMES-CNRS,

Alexis Farcy and Brigitte Descouts, STMicroelectronics, Emmanuel Augendre andThomas Signamarcheix, CEA-LETI, and Vincent Lelivre and Aziz Ouerd,ALES

Laser Processing: A Robust Solution for Dicing Ultra-Thin SubstratesKip Pettigrew, Matt Knowles and Michael Smith,ESI

Solder in the Age of 3D Semiconductor AssemblyDr. Andy C. Mackie, Global Product Manager and Tae-Hyun Park, CountrySales Manager,Indium Corporation

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CONTENTS














Volume 15, Number 6 November December 2011Volume 15, Number 6 November December 2011


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Chip Scale Review Nov/Dec 2011 [ChipScaleReview.com]2
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CONTENTS

FEATURE ARTICLES

Test Improvement via Electroless PlatingTerence Collier, CVinc

How to Dice Fragile MEMS DevicesAlissa M. Fitzgerald, Ph.D. and Brent M. Huigens, AMFitzgerald & Associates

Dispensing Advantages for MEMS Wafer CappingAkira Morita, Nordson ASYMTEK

LED Dicing: The Sapphire Blaze IndeedJeffrey Albelo, Quantum-Group Consulting, Ltd.

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DEPARTMENTS

From the Publisher 2011 in RetrospectKim Newman, Chip Scale Review

Patents Changes to Patent LegislationJason Mirabito,Mintz, Levin, Cohn, Ferris, Glovsky and Popeo, P.C.

Guest Editorial Backside Illumination Highlights Direct Bonding TechnologyKathy Cook, Ziptronix

Industry News

Chip Scale Review staffInternational Directory of Solder and Flux SuppliersRon Molnar,Az Tech Direct LLC

Product Showcase

Editors OutlookACT IV.Ron Edgar, Chip Scale Review Contributing Editor

Advertiser Index, Advertising Sales

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FROM THE PUBLISHERThe International Magazine for Device and Wafer-level

Test, Assembly, and Packaging AddressingHigh-density Interconnection of Microelectronic IC's

including 3D packages, MEMS, MOEMS,RF/Wireless, Optoelectronic and Other

Wafer-fabricated Devices for the 21st Century.

STAFF

Kim Newman Publisher

[email protected] Edgar Technical [email protected] von Trapp Senior Technical [email protected] Winkler Contributing [email protected]

Dr. Thomas Di Stefano Contributing [email protected]

Paul M. Sakamoto Contributing Editor [email protected]

Jason Mirabito Contributing Legal [email protected]

Chip Scale ReviewT 408-429-8585F 408-429-8605

Carrie Stalker

[email protected]

Advertising Production Inquiries:Kim Newman

[email protected]

EDITORIAL ADVISORS

Dr. Thomas Di Stefano Centipede SystemsAndy Mackie Indium Corporation

Guna Selvaduray San Jose State University

C.P. Wong Georgia Inst of Technology

Ephraim Suhir ERS Company

Nick Leonardi Premier Semiconductor Services

John Lau Industrial Tech Research Inst (ITRI)Alissa Fitzgerald A.M. Fitzgerald & AssociatesJoseph Fjelstad Verdant ElectronicsVenky Sundaram 3D (PRC) Georgia Inst of TechnologyRolf Aschenbrenner Fraunhofer InstituteFred Taber BiTS Workshop

Scott Jewler Powertech Technology Inc.

Copyright 2011 Haley Publishing Inc.

Chip Scale Review(ISSN 1526-1344) is a registered trademark of

Haley Publishing Inc. All rights reserved.

Subscriptions in the U.S. are available without charge to qualified

individuals in the electronics industry. Subscriptions outside of the

U.S. (6 issues) by airmail are $100 per year to Canada or $115 per

year to other countries. In the U.S. subscriptions by first class mail

are $95 per year.

Chip Scale Review, (ISSN 1526-1344), is published six times a

year with issues in January-February, March-April, May-June, July-

August, September-October and November-December. Periodical

postage paid at Los Angeles, Calif., and additional offices.

POSTMASTER: Send address changes to Chip Scale Review

magazine, P.O. Box 9522, San Jose, CA 95157-0522

Printed in the United States

Kim NewmanPublisher

T2011 in Retrospect

he past 12 months have been a busy time for everyone at Chip ScaleReview. As this is our last issue of 2011, it seems to be a good time to

reect on our progress and look forward to what 2012 will bring for us and for the

industry at large.2011 brought many things to the table for us all. Once again, we successfully

published six spectacular issues ofChip Scale Review in both print and digitalcovering technology advancements in established semiconductor packagingprocesses and technologies, as well as a myriad of innovations being pursued byresearch institutes all over the world (SEMATECH, Ga Tech, ITRI, and CEA Leti).Additionally, our eNL CSR Tech Monthly, still in its infancy, has gained momentumas a supporting media buy to the print for CSRs advertisers. 12 issues of the CSRTech Monthly were broadcast in 2011 with another 12 on the way in 2012. Imhappy to report that the 2012 media kit is hot off the press and available online.

Chip Scale Review supported three major trade events in 2011 as the OfficialMedia Sponsor for both the BiTS Workshop and the Electronic ComponentsTechnology Conference (ECTC); as well as our very own co-sponsored event withSMTA the International Wafer-Level Packaging Conference (IWLPC ). You can

read up on this years IWLPC in the Industry News section of this issue (pp. 12-13)or check out the video clips on the CSR website.

Also vital to the success ofChip Scale Review our editorial advisors, who helpnavigate the editorial direction and scope of the magazine and assist in recruitingexclusive technical features throughout the year. On behalf of everyone at CSR, wecontinue to appreciate those members who have been long standing advisors overthe years including: Tom Di Stefano of Centipede Systems; Andy Mackie of IndiumCorporation; CP Wong, Regents Professor at Georgia Institute of Technology; GunaSelvaduray, Professor Materials Engineering at San Jose State University; EphraimSuhir of ERS Company; and Nick Leonardi of Premier Semiconductor. Newcomersto this distinguished list include: Rolf Aschenbrenner, Deputy Head at FraunhoferInstitute; Alissa Fitzgerald of AM Fitzgerald & Associates; Joseph Fjelstad, Verdant

Electronics; Scott Jewler of Powertech Technology Inc; John Lau of ITRI; VenkySundaram of 3D PRC, Georgia Institute of Technology; and Fred Taber Chairmanof the BiTS Workshop.

Chip Scale Reviews past and future success can be attributed to the editors andcontributors of the columns, the guest editorials and of course the technical features.I would like to personally thank and acknowledge each and every columnist andauthor who contributed their article to CSR. A special thank you to Technical EditorRon Edgar who supported CSR throughout the year and has provided his finalcolumn in this edition entitled Act IV. After deliberation Ron has decided to focuson his career at hand. We wish him well and the very best ahead.


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PATENTS

Changes to Patent LegislationBy Jason Mirabito, [Mintz, Levin, Cohn, Ferris, Glovsky and Popeo, P.C.]

O n S ep t em b er 1 6 , 2 0 1 1 ,President Obama signedthe Leahy-Smith America Invents Act,

probably the most comprehensive patentreform legislation in the last 40 years.This article focuses on two changesthat have great impact. The first is afundamental change to the U.S. patentapplication ling system and the second

is a fundamental change to the ability ofthird parties to challenge patents.

First-to-File System EnactedFor many years under U.S. Patent

Law, the U.S .has been under a first

to invent system. According to thissystem, even if there are two (ormore) persons file for a patent at theUnited States Patent Office (USPTO),the earliest of those two inventorsis not necessarily considered to bethe inventor. In what is called aninterference proceeding, the USPTOdetermines the f i rs t inventor bylooking at invention records, etc. Theseinterference proceedings are long andhave been traditionally very expensive.

The U.S. has now gone to a first- to-le system.This means simply, whoevergets to the USPTO first and files theirapplication first is the first inventor.Period. It is believed that this changeputs the U.S. in the same position asevery other country in the world, whichall have rst-to-le systems. During the

pendency of this portion of legislation,there was much criticism of this shift toa rst-to-le system by small inventors

and some small companies, who argue

that this change would benefit largercompanies that have the money and

wherewithal to file applications early.Time will only tell whether this becomesan impediment for small companies to

le patent applications.

Enacting Post Grant ProceduresThere have been allegations that

the USPTO allowed patents to issuethat should not have issued in the firstplace. Therefore, Congress decided thatthere were not sufficient safeguardsbuilt into the USPTO system to catchbad patents. Since at least 1980,parties have been able to file requestsfor reexamination. This part of the pre-

existing patent statute allows thirdparties (even the patent owner) topresent the Patent Office with priorart consisting of printed publicationsand allege that the claims as issued inthe patent are not valid on the basis ofthis same prior art. Up until recently,the only type of reexamination thatwas permitted was a so called ExParte Reexamination, where the partyrequesting the reexamination (therequestor) had very limited participation.

Circa 1999, the so called interpartesreexamination system came into beingthat allowed requestors relatively fullparticipation in the reexaminationprocess, including the ability to appealthrough to the U.S. Court of Appeals forthe Federal Circuit.

The just enacted law now providesfour avenues by which requestors canchallenge the validity of the claims ofa patent. The rst is the so-called Post

Grant Review, which will allow third

parties to challenge the validity of apatent within nine months of the patent

issue date. It is permissible to bringany ground or grounds for invalidityto the attention of the USPTO, not just

limited to prior printed applications. TheEuropean Patent Office has a similarpost-grant review and the change in theU.S. law makes U.S. law conform to thatof the European Patent Ofce.

Under the second procedure, InterPartes Review, any time after the ninemonth post-grant period expires, arequestor can request a reexamination ofthe patent; but here the request is limitedto prior printed publications. While theentire provision does not come into

effect immediately, the part that relatesto the standard under which the USPTOwill grant a request for a review comesinto effect immediately. The old test wasthat of raising a substantial question ofpatentability. The new test is whetherthere is a reasonable likelihood thatthe petitioner will prevail with respectto at least one challenged claim. Thiswill raise the bar and the level of proofneeded before the Patent Office willgrant such a petition.

A third addition is called SupplementalExamination, which can be requestedby the patent owner only and allowsthe patent owner to have the USPTOconsider information related to thepatent.

Fourth, and nally, the old ex parte

reexamination law will still continue toexist and, in fact, coexist with the otherprovisions that have been enacted.

It is expected that the new andexpanded post grant procedures will

keep the USPTO very busy in thecoming years.
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turn produces higher yields and lower costper die.

The growth of the BSI market hasoutpaced original market expectations,and according to Yole Dveloppment, itis expected to exceed $16B cumulativelyover the next four years (Figure 3.)

Implication of Commerical Licensingwithin the Image Sensor Market

One proprietary direct bondingtechnology has been in existence forseveral years, and the technology isnow gaining momentum in the market.BSI image sensors are the first real

ith backside illuminated(BSI) sensors in high-

volume production and interposersseemingly ready to take off, the time

for 3D integration has finally come.Direct bonding has played a keyrole in enabling BSI image sensormanufacturing and will continue to doso in other 3D applications.With thetechnology now licensed commercially,there are fewer questions about thefeasibility of direct bonding technologythan in the recent past.

BSI image sensors have bet terperformance than their FSI counterparts.The improved performance is due to the

fact that the metal interconnect layers arepositioned below the photodiode layer asopposed to above it (Figures 1a and b).

W i t h i n t h e B S I i m ag e - s en s o rmanufacturing space, direct bondingtechnology enables device manufacturersto achieve lower distortion than othertechnologies (Figures 2a, b and c). Theresult is that pixels can be scaled smaller,resulting in more die per wafer. This in

mainstream semiconductor applicationin the consumer electronic market spaceto move into the third dimension involume production.

The fact that direct bonding technologyhas been licensed commercially andis in high volume production servesas confirmation of the strength of thepatents covering the technology. IPcompanies have no choice but to protecttheir own intellectual property in order tosurvive, but when large, well-respectedcompanies take a license, people tend topay attention.

Other types of bonding technologies donot offer the same benets in the area of

3D integration. The closest competitionincludes bonding technologies such asadhesive bonding or thermo-compressionbonding. Because there is not a thick laterof additional material required, directbonding technology results in lowerdistortion than other technologies a keymetric for image sensor manufacturers.

The TechnologyDirect bonding technology stems from

more than 20 years of material research

resulting in an elegant, but simple andhighly efficient solution for volumemanufacturing involving two or moreseparate substrates or devices. Theseprocesses are designed to use standardsemiconductor wafer fab equipmentand do not require expensive custom orspecialty wafer processing equipment.Wafer bonding equipment optionsrequired for direct bonding are variedand range from relatively simple andinexpensive to much more complex.Some of the factors to consider includealignment accuracy requirements

Backside Illumination Highlights Direct Bonding

TechnologyBy Kathy Cook, [Ziptronix]

W

Figure 1. (Top) Front side illuminator technology vs.(Bottom) BSI using front-side processes.

Figure 2. a) Direct bond technology b) Assembly is flipped and thinned c) Final BSI

GUEST EDITORIAL
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a n d l e v e l o f a u t o m a t i o nrequired.

As mentioned,direct bondingtechnology isenjoying wideadoption. Thepatents involvedare broad andi n v o l v e l o w -

temperature bonding of insulators, silicon, III-V and other dissimilarmaterials. The technology involves planar, homogeneous bondingsurfaces, and is currently being used in high-volume manufacturing

applications. Bonding can occur at relatively low temperaturesdue in part to a surface activation/termination step that is onecomponent of the technology.

A second area of signicant activity is direct bond interconnect

and is based on the same principles as the direct bond technology,but includes conductive interconnects, so therefore involves

planar, heterogeneousb o n d i n g s u r f a c e s .This technology givescustomers a high-density,scalable interconnectmethod that leverages

h igh-volume foundryprocesses. Figure 4 isan SEM image showingthe bond interface of aconnection made betweena pixel wafer and a logic

wafer at a pitch less than 2m. Direct bond interconnect has notyet been licensed in the consumer electronics space, so there stillare opportunities for exclusivity within these markets.

Beyond the image sensor space, there are several applicationsfor direct bonding technology both with and without interconnects.Other applications include pico projectors, various types of

stacked devices, RF front-end applications, MEMS and otherheterogeneous applications.

SummaryBSI image sensors have paved the way for many 3D integration

applications, some of which are already being geared up for volumeproduction. Direct bonding is a key enabler within the 3D technologyarena and is garnering much attention, both with and withoutinterconnect, in new, advanced image sensors and a variety of otherapplications. Wafer stacking made possible by direct bonding isallowing chips to move out of the x-y plane and into the z-direction.

Kathy Cook, Director of Business Development, Ziptronix, may becontacted at [email protected].

Figure 3. BSI image sensor projections presented at the Image

Sensors Europe Conference in March of 2011

Figure 4. SEM of logic and pixel wafers bond

interface using the direct bond interconnect process
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INDUSTRY NEWS

ointly hosted by SMTA and ChipScale Review, the InternationalWafer Level Packaging Conference

(IWLPC) held October 3 6, 2011 inSanta Clara, CA validated the growingdemand for more IC functionality insmaller IC packages by exploiting the3rd dimension.

The SMTAwas very pleased tosee a 20% increasein a t t endancea t I W L P C . N o t e d S M T AAdministrator,JoAnn Stromberg,In conjunctionwith Chip ScaleReview we wereable to organize

another strongtechnical program focused on leading-edgetopics such as 3D, wafer level, and MEMS.With a sold out exhibit floor, outstandingspeakers, and enthusiastic attendees we lookforward to 2012 and another strong IWLPC.

This years event, organized by ConferenceChair, Andy Strandjord of PacTech USA,and Technical Chair, Luu Nguyen of TexasInstruments, consisted of 29 technicalpresentations organized in three paralleltracks, two panel discussions, six half-day

tutorials, a poster session, two morningplenary sessions, and it was highlightedby an entertaining dinner keynote speechfrom Raj Master of Microsoft.

Exhibit Hall Sold OutThe exhibit hall was sold out this

year with booths from 44 companies (upfrom 38 exhibitors in 2010) promptingthe hosts to move the event to a largervenue in 2012. There were 20 newexhibitors this year.

Steady supporters that have exhibitedthe last three years in a row include:

Aehr Test, Boschman, EV Group,Kyzen, NEXX Systems, Owens Design,Pac Tech USA, Promex, Quik-Pak/Gel-Pak, Silex Microsystems, TechSearchInternational and Tessera.

Generous SponsorsHelping to make IWLPC the best

industry conference on wafer level

packaging were seven generous corporatesponsors. They were led by the Platinum-level sponsors, Amkor Technology, EVGroup, and NEXX Systems. Gold levelsponsors included Nanium, PacTech,STATS ChipPAC, and SUSS MicroTec.

Amkor Technology, Inc. is one of theworlds largest providers of advancedsemiconductor assembly and testservices. They offer a suite of services,including electroplated wafer bumping,probe, assembly and final test. Amkor is a

IWLPC 2011 Exploiting the 3rd DimensionBy Ron Molnar[AZ TECH DIRECT]

J leader in advanced copper pillar bump andpackaging technologies which enablesnext generation ip chip interconnect.

EV Group, Inc. provides leading-edge wafer processing equipment forMEMS and Microfluidics, advancedpackaging, compound semiconductor/MOEMS, SOI, power devices and nano-

technology applications. EVGs productportfolio features double sided mask/bondaligners, wafer bonders for anodic siliconfusion, thermocompression and low tempplasma bonding, wafer/mask cleaningsystems, photoresist spin/spray coatersand developers, hot embossing and nano-imprinting systems, and defect and particleinspection systems.

NEXX Sys t ems has p ioneeredeconomical and flexible solutionsaddressed specifically to wafer levelpackaging (WLP). NEXX has become

Figure 1. SMTA reported a

20% increase in attendanceat IWLPC 2011

Figure 2. John Crane of Boschman has a captive

audience from Agilent

Figure 3. At the STATS ChipPAC exhibit, Steve

Wofford, Sr. director of worldwide marketingcommunications explains the companys latest WLP

offering to an interested attendee

Figure 4. Curtis Zwenger, Amkor, discusses the

companys latest TSV and copper pillar flip chiptechnologies

Figure 5. Garret Oakes, director of technology, EV

Group, talks about the companys recent expansionat its world headquarters in Schaerding, Austria


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a global leader in the design andmanufacture of advanced packaging

processing systems that enable smaller andfaster consumer electronics.

Attendance Grows Nearly 25%Interest and activity in the area of wafer

level packaging (WLP) continues to grow.This years conference drew 460 attendees up nearly 25% over the 370 registrantsfor the 2010 event. Participation from theinternational community also continues togrow. IWLPC 2011 drew attendees from15 countries led by the United States,Germany, Japan, Korea, China and theUnited Kingdom.

Popular TutorialsThe organizers were proud to offer

six half-day tutorials to 92 students bya number of well-known and respectedindustry leaders as a means of educatingthose unfamiliar with wafer level andadvanced packaging technologies.

The two most popular tutorials wereWafer Level Packaging by Luu Nguyen,Ph.D. of National Semiconductor andTSV and Key Enabling Technologies

for 3D IC/Si Integration and WLP byJohn Lau, Ph.D. of Industrial TechnologyResearch Institute (ITRI).

Talking TechnicalThree parallel tracks of technical

presentations were offered again this yearcovering WLP, 3D and MEMS topics.In total, there were 29 presentations.

Judging by attendance figures, the mostpopular session was definitely Session

1 Advanced Wafer Level PackagingTechnologies, followed closely by

Figure 6. At Nexx Systems - John Bowers VP

worldwide sales meets with Michael Schneider of ECI

Figure 7. Keith Cooper, SET North America, delivers

an interesting talk on updated processes collectivehybrid bonding for C2W processes

(continued on Page 42)
http://www.pactech-usa.com/


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The market for portable andmobile data access devices

connected to a virtual cloud accesspoint is exploding and driving bothincreased functional convergence aswell as increased packaging complexityand sophistication. This is driving anunprecedented demand to increase thevariety of wafer level, thin POP, andTSV/interposer packaging solutions.If flip chip is the current workhorse,

then we can expect to see more excitinginterconnect technologies such as TSV,2.5D interposers, FO WLP and 2ndgeneration FO WLP to meet these needs.

3D and Advanced Packaging EvolutionConnectivity is the key to both

business and consumer electronicsgrowth as huge investments in wirelessand 3G/4G ne tworks acce l e ra t ed ev e l o p m en t o f n ew p ack ag i n gtechnology. Particularly important in this

next generation of wafer level packaging(WLP) is the need for higher bandwidth,improved thermal dissipation andmaterials, and the capability for highercurrent per bump without creatingelectro migration (EM) failures.

Mobile Computing ConvergenceDriven by the need for higher levels

of integration, improved electricalperformance, or reduction of timingdelays, the need for shorter vertical

interconnects is forcing a shift from 2Dto 2.5D and 3D package designs. 3Dintegration is proceeding on three fronts,moving from the package level (dieand package stacking) to wafer level,especially fan-out wafer level packaging(FO WLP), and more recently at thesilicon (Si) level for through silicon va(TSV) and interposers.

Co-design between the silicon andthe packaging is required to achievean optimized cost and system solution.When co-design can be done withintegrated passives, a new level of WLP

Innovation Trends Driving WLP and 3D PackagingBy Steve Anderson [STATS ChipPAC]

can be provided that reducescosts, package thickness, andintegrates more functions ina single package.

3D vs. HeterogeneousApproaches

While the need to combinemore mobile functions inan efficient , low-profi lesolution is fueling the shift

towards 3D packaging, challenges stillremain in the areas of design, testing,mass production, cost effectiveness,and materials compatibility. Given thatsystem-in-package (SiP), package-on-package (POP), and 2.5D interposertechnologies have become more matureand widespread, the further deploymentof embedded wafer level technologiesand TSV will continue to drive themigration from 40nm to 28nm. Theheterogeneous integration capabilities

of these technologies is enabling a moreholistic design approach by combiningmultiple die with memory, integratedpassives, and mixed technology nodesto provide lower cost, thin proles and

more reliable, packaging solutions.Driving forces behind wafer-level and

silicon-based technologies include smallerfootprint, increased functional integration,increased I/O density, improved electricaland thermal performance, and lowercost due to batch processing (Figure 1).

Examples include: Fan-in wafer level bumping withtighter pitches for shorter signallengths

Embedded fan-out wafer levelsolutions

High-speed memory and processorapplications with high bandwidthinterconnect that move beyondtodays POP technology solutions

Full implementation of TSV 3Dpackaging technology for mobileproducts

3D TSV technology is slated to

appear in late 2013 or 2014. TSVshelp enable the increased density bypacking a great deal of functionalityinto small form factors with multipleheterogeneous functions such as logic,analog, RF, memory and MEMs. Thistechnology provides an alternativeto expensive system-on-chip (SOC)development and allows technologyfrom different nodes to be combined ina single package.

Fan-Out Wafer Level GrowthMuch of the initial industry work

to develop and deploy fan-out WLP,(FOWLP) led by embedded waferlevel ball grid array (eWLB), has beenon 200mm wafers (Figure 2). Thefocus is now on 300mm formats thatenable this technology to be more costcompetitive and scale more efficiently.FOWLP panel sizes larger than 300mmimprove the cost structure, increaseproduction efciencies as well as enable

Figure 1. Driving Forces Increasing Wafer Level Packaging Growth

Figure 2. eWLB Fan-Out package


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a wider range of single die and multi-die congurations. The proliferation of

FOWLP configurations is expandingas the demand for increased packagingdensi ty grows, especial ly in 3Dapplications.

2nd Generation FOWLP

While f i rst-generat ion FOWLPen ab l ed v e r y d en s e s i n g l e an dmultilayer packages, new performancerequ i remen t s a re push ing thesepackaging l imi ts toward secondg en e r a t i o n F O W LP . A ch i ev i n gm a i n s t r e a m s t a t u s f o r F O W L Ptechnology status requires a broadapproach with flexible, cost-effectivesolutions ranging from single die

to multi-chip solutions in one-layerrouting, to more complex multiplelayers, IPD integration, POP versionsand ultimately, SiP, SoP, and complete3D solutions utilizing TSV. Table 1highlights some next generation eWLB

packages and specifications. All ofthese configurations are well withinthe uniquely robust capabilities ofthis technology as a solid integrationplatform. The ability to route finerlines and spaces enables a wider rangeof packages ideal for the growingsmartphone and tablet markets.

eWLB with Integrated PassiveseWLB is available in both large

and small body sizes, allowing for a

wide range of integration capabilitiesenabled by multiple layers of routingas well as vertical stacking and passiveintegration. (Figure 3). Essentially, thisenables very thin side-by-side deviceand passive integration for powerfulcost-effective systems. When verticallystacked, eWLB enables very highbandwidth and reliable high density2.5D package solutions.

Multiple die FOWLP (horizontal)The integration of one to four die

along with passive functions providessignicant performance, size reduction,

Table 1. Key focus of next-generation FOWLP

packaging development efforts(a)

(b)

Figure 3a. Embedded inductor and (b) SEM

micrograph of cross-section of 2-layer RDL eWLB
http://www.h-pins.com/


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and device integration critical to 2.5 to3D system requirements of high yieldsand affordable price points (Figure 4).

A s c l o u d c o m p u t i n g g a i n sprominence, new designs are emergingthat require much larger FOWLP bodysizes than in production today. This largedie FOWLP will again push material

and manufacturing requirements tohave efficient panel sizes and goodmanufacturing process control.

eWLB POP driving 2.5D systemL o w - p o w e r m o b i l e d e v i c e

applications are driven by the needfor increased bandwidth and speed.Pu t t i ng th i s l eve l o f comput ingperformance and networking capabilityinto consumer and lower cost businesssystems that were once considered high-

end is driving a more aggressive pushtowards advanced WLP solutions and3D packaging, given the limited formfactors and space required for increasedbattery life (Figure 5).

Super Thin FOWLP POPFurther integration and form factor

reduction can be achieved by using avertical FOWLP package where thedie and redistribution layer serve as theinterposer, eliminating costly laminate

build-up substrates and providing cycle

time reduction. This redistributionstructure reduces the stack height whereby

a 12x12mm package can have a totalstacked die height of less than 1.0mm(Figure 6). The reduced interconnectlengths will also provide better electricalperformance and lower parasitic values.

Beyond Wafer Level PackagingIncreased interconnect density is drivingsmaller bond pad pitches, stacked die,mixed interconnect, and advancedinterconnect technologies such asinterposers and TSVs. Footprints

are shrinking driven by reducinglithography nodes while maintaining orincreasing the I/O count and driving theexternal ball pitch below 0.4mm downto 0.35 or 0.30mm. This trend is drivingcustomer ball patterns to manage theescape routing and costs for systemboards. Overall package performanceis heavily influenced by electrical andthermal performance. The modeling andmanagement of these functions is muchmore critical as more functionality is

absorbed in fewer packages within theseheterogeneous 3Dpackaging structures.System performancecan be increased andimproved if proper 3Dpackaging elementscan be implemented.

FO WLP Package asTSV Interposer

W a f e r l e v e l

technologies such aseWLB are leading the

way to the next level of thin packagingcapability. They provide a robustpackaging platform supporting verydense interconnection and routing ofmultiple die in very reliable, low-warpage2.5D and 3D solutions. The use of these

embedded FO WLP packages in a side-by-side conguration to replace a stacked

package conguration, or to utilize as the

base for a 3D TSV conguration, is critical

to enable a more cost effective mobilemarket capability. A cross-section of thistype of package is shown in Figure 6.Combining wide I/O interfaces with theTSV packaging capability can provide anoptimum solution for achieving the bestperformance in thin multiple-die stacksaimed at high-volume manufacturing.

High-Dens i t y So lu t ions in aHeterogeneous Conguration

The business and consumer drive forgreater portability and data on demandis forcing increased packaging densityand more cost-effective 3D solutions.While POP technologies are effectivefor integrating functions in a smallpackage, they lack the high bandwidthand low-prole increasingly needed by

the new generation of thin tablets and

more powerful mobile processors.Technical and manufacturing issuesare key challenges for 3D stacks. Theseinclude testability and yield, scalability,thermal and standardized IC interfacechallenges. 3D TSV packages are beingdeveloped to provide heterogeneousintegration of memory, logic, graphics, andpower functions that cannot be integratedinto single die; and to provide improvedelectrical performance below 28nm fromvery short and high density interconnects

between the stacked ICs. Figure 7 showsan example of the transition from 2D to2.5D and nally to 3D.

TSV TechnologyTSV technology is driven particularly

by the need in smartphones and tabletsfor much faster processing speeds andmemory bandwidth in order to manageall of the advanced functions requiredof these products. For successfulmarket penetration, the TSV ecosystem

compr i s ing IDM, OEM, OSAT,foundries, design houses, and PCBFigure 5. Progression of next generation eWLB technology from 2D to 3D forhighly integrated packaging solutions

(a)

(b)

Figure 6a. Super thin FOWLP POP adoption of

FOWLP technology for 2.5D applications

Figure 4. 12x12mm eWLB packages with two dieand double layer RDL with 0.4mm pitch


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Figure 7. Transition from 2D packaging to thin 3D TSV

suppliers must be properly enabled.The advantages of the TSV packaging approach over SOC are

many including higher bandwidth due to the shorter interconnects,power reduction, lower cost, greater miniaturization and greatermodularity and exibility.

TSV Challenges and Design RequirementsExtensive retooling for design is not required to create TSV

packaging. There appears to be no major roadblocks in processtechnology. However, new capabilities are required to route andconnect ne pitch microbumps .

Package co-design and integrated process control is key forsuccessful implementation of widespread TSV usage. While thinwafer backgrinding is available, backside TSV reveal, stealthdicing, and ne pitch thermal compression bump bonding are still

under development and testing.

Conclusion

Building the 3D packaging infrastructure requires a goodsystem to manage the IC, packaging, and the board designwhile trying to establish common standards for at least thememory interfaces. An ecosystem consisting of IP suppliers,foundries, OSATS, IDMS, OEMS, and design houses is beingdeveloped with co-design and standards collaboration. Costeffectiveness depends on the proper co-design of the chip,package, and board.

As the demand for mobile and portable electronicsg rows , t he demand fo r smal l e r , l i gh t er , and h igherbandwidth packaging will grow evolving from todays POPconfigurations to more complex embedded WLP and vertical

3D TSV technology. Differentiation and even productsuccess is being driven by the ever-expanding feature sets,functionality, convergence and adoption of more computingrich gesturing and graphic applications. The additionalincrease in cloud computing access points requiring improvedpackaging for the mobile networking market will only further2.5D and 3D packaging variation adoption.

Next -generat ion packaging such as TSV and next -generation FOWLP is enabling these advances and proves toprovide more exciting developments in the future.

Steve Anderson, Senior Director, Product and Technology

Marketing Advanced Technology, STATS ChipPAC, may becontacted at [email protected].
http://www.indium.com/


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M uch of todays activityto develop cost-effectivemultilayer 3D assemblies in volumeproduction focuses on the near-termproblems and tradeoffs of verticallyinterconnecting stacked layers ofdevices and sub-systems either withthrough-silicon-vias (TSV) or siliconinterposers. However, in 2009 theFrench Government took a longer-term

view by funding PROCEED, a 2-yearresearch project to increase the densityof vertical connections through the useof direct copper-to-copper bonding.

The goal of the PROCEED projectis to demonstrate higher densi tyin t e rconnec t s wi th a p l acemen taccuracy of less than 1m for chip-to-wafer (C2W) interconnections linkedby direct metallic copper-to-copperbonding. Higher connection densitieswill be an advantage in assembling

high-performance circuits with 3Dinterconnections. Higher connectiondensities will enable a wide range ofapplications in microelectronics as wellas in optoelectronics and in MEMS.

Direct copper-to-copper bondingrequires good planarity and excellentsurface quality. The controlled bondingenvironment has to maintain a low levelof contamination from metallic particlesand other sources. Both the smoothfinish of the copper pillars and pads

as well as the topography between thecopper and oxide areas are critical toachieving good bond strength.

Direct Bonding AdvantagesThe C2W direct bonding process has

several advantages over conventionaleutectic solder bonding and thermo-compression bonding processes oftenconsidered today for 3D integration.

A major advantage of the directbonding processes advanced by thisprogram is very high density of thevertical interconnects it supports.

Direct Copper Bonding Of High-Density 3D AssembliesBy Gilbert Lecarpentier[SET], Marc Legros and Mayerling Martinez [CEMES-CNRS], Alexis Farcy and Brigitte Descouts

[STMicroelectronics], Emmanuel Augendre and Thomas Signamarcheix [CEA-LETI], and Vincent Lelivre and Aziz Ouerd[ALES]

Contact density may reach tens ofthousands of connections per squaremillimeter. This is made possibleb o t h b y t h e h i g h e r p l a c e m e n taccuracy in direct bonding, and by themonometallic connections eliminatingthe potent ial thermal expansionmismatch s t r ess t ha t may occurbetween different metals.

Better electrical performance is

attained, with lower ohmic valuesper unit area than older bondingapproaches . The d i r ec t bond ingapproach provides high mechanicaland electrical integrity. Unlike eutecticsolder assembly, the bonding interfaceis void-free, resulting in lower electricalresistance, higher strength, and betterreliability. The process provides robustself-sealing for C2W stacking withoutrequiring any adhesive or underfill.C2W stacking results in higher yields

than wafer-to-wafer (W2W) stacking.T h e l o w - c o m p l e x i t y p r o c e s sd e s c r i b e d h e r e a l l o w s r o o mtemperature assembly with ambientair at atmospheric pressure. Bondingr eq u i r e s o n l y l o w f o r ce s . Th a tcombina t ion i s an advan tage inreducing line throughput time, which isessential for high-volume production.

Team Members and TasksThe suite of skills essential for

this task required the collaborativeefforts of ve groups, each with expertskills in some aspect of the problem:handling and bonding equipment(SET), bonding surface preparation( A L E S ) , b o n d i n g ( C E A - L e t i ) ,developing semiconductor solutionsacross the spectrum of electronicsapplications (STMicroelectronics), andassessing and comparing the resultsthrough an industrial test vehicle(CEMES-CNRS). Each par tnerscontributions are described here infurther detail.

Equipment DevelopmentS E T c r e a t e d a n e w d e s i g n

conf igurat ion of p ick-and-placeequipment by modifying the provenFC300 platform to operate in a Class10 envi ronment and to meet theprecision placement requirements ofdirect copper-to-copper bonding. Thishigh-placement-accuracy platform hasbeen developed as the base of the new

system, designed for the special needsof the PROCEED project.

The design changes for accuracyhave mainly focused on the optics andbond head stages, which move over thewafer during its population. To meetthe direct metallic bonding cleanlinessrequirements, the system was modied to

provide a low particulate contaminationdesign that meets Class 10 environmentalstandards. The primary areas needingmodication to achieve the required level

of cleanliness were the cable channels,the mechanical housing, and the aircirculation through the machine.

The main features of the modied pick-

and-place equipment are its suitabilityto direct bonding and its alignmentcapability (Figure 1). These were assessedindependently through particulatecontamination measurements, transmissionelectron microscopy (TEM) imaging ofthe bonding interface, and post-bondingalignment evaluation by infrared (IR) and

acoustic microscopy (SAM).

Figure 1. An inside view of the SET FC300 Bonderwith direct metallic bonding configuration


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Surface PreparationAir Liquide Electronic Systems

(ALES) is supplying technology toprovide the required surface preparation.The approach is based on a wideknowledge of chemical-mechanical

polishing (CMP) and cleaning solutionsdesign. In this program, new chemistrieswere developed to meet very stringent

requirements of the direct bondingsurfaces (Figures 2a and 2b).

In addition, development within thePROCEED project included a specificand easily adjustable dilution and

distribution unit that is capable of bothapplying andc o n t r o l l i n gt h e s u r f a c ep r e p a r a t i o nc h e m i s t r i e s( F i g u r e 3 ) .D e p e n d i n go n t h e f i n a li n t e g r a t i o nscheme, t h i sunit could be

installed in theequipment ina c c o r d a n c ewith clean roomspecificationsand mechanicalrequirements ofthe alignmentprocess.

B o n d i n gDevelopment

In this project,C E A / L E T I

is fulfilling its usual role of being aninterface between industry and academicresearch and between equipmentsuppliers and an integrated devicemanufacturer (IDM). The PROCEEDproject extends this activity to include

3D integrated system technologies usingD2W direct bonding

A driving force for 3D integration is the

need for an economically viable approachto achieve innovative multifunctionalsystems through the assembly ofheterogeneous existing sub-parts. Throughsuch repartitioning, sub-parts can be kept

small in size, requiring few mask levelsand yielding shorter interconnects, therebyimproving yield, cost, performance andenergy efciency. Although 3D integration

can be achieved through W2W stacking,performing C2W assembly conveysfurther benefits in terms of flexibility(namely in sub-part size, technology orsupplier) and yield (relying on knowngood die (KGD) and avoiding long-rangeoverlay issues).

Direct bonding has emerged as a

powerful technique in the eld of substrateengineering. When the two mirror-polished surfaces are put in contact,they are initially held together at roomtemperature by adhesion forces (Van derWaals forces or hydrogen bonds), withoutany additional materials. At that point,their adhesion is weak and the bondingis reversible. To strengthen and completethe bonding, the bonded pair is usuallygiven a thermal treatment right after directbonding, which causes covalent bond

formation, thereby closing the interface.Direct bonding is even more attractive

for semiconductor C2W assembly.Bonding at room temperature with ambientair at atmospheric pressure avoids the timeand complexity of vacuum chambers.Eliminating adhesive materials avoidshandling, dispensing, and controlling

liquids. Consequently, direct bonding isalready in use at an industrial scale for themass production of silicon-on-insulator(SOI) substrates. Direct bonding was alsorecently demonstrated with conventionaldamascene surfaces. These are mixedplanarized surfaces that include low-pitchcopper interconnects in an oxide matrix,creating conductive paths across thebonding interface. Applying damascenedirect bonding to 3D integration in a C2Wscheme brings in several key benefits

compared to current approaches.Copper-to-copper direct bonding

enhances bonding accuracy for high-density interconnections by avoiding thepotential thermal expansion mismatchof bonding different materials. To ensurevoid-free bonding, the alignment andbonding steps must be carried out ina particle-free environment. This isaccomplished by using special materialsand by careful management of thebonding environment to protect the wafer

surface while it is being fully populatedwith dice. Because the bonding processtakes place at low force and roomtemperature, line throughput is increased,adding capacity and reducing costs.Low-force bonding process is key to thehigh throughput required for widespreadadoption of 3D IC integration.

The trend towards 3D integrationo r i g i n a t e d i n t h e n e e d f o r a neconomically viable scheme to achieveinnovative multifunction systems through

the assembly of heterogeneous existingsub-parts. Through repartitioning, sub-parts can be kept small in size, requiringfew mask levels and yielding shorterinterconnects to improve yield, cost,performance and energy efciency.

Applications DevelopmentSTMicroelectronics is driving the

application of this technology for high-density 3D integration and participatingin the elaboration of the specification

for future high-volume machines. Thisrole within PROCEED exists in the 3D

Figure 2a. AFM image of a copper surface after a one minute post CMP cleaning with chemical solutions.

(b) SEM image of a 2 X 5 m through-silicon via (TSV) filled with ECD copper using electroplating chemistry

Figure 3. 3D drawings of an

example of on-board surfacetreatment equipment


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test chip integration for technologicaldemonstrations of the direct bondingprocess. First, wafers with multiple back-end of line (BEOL) interconnect levelswere provided to validate the surfacepreparation treatment compatibility with

CMOS technology, especially consideringthe topology due to the presence ofmultiple BEOL levels. Then, a 3Dtest chip, which embeds several activestructures, was integrated according to afull CMOS 65nm node process ow for

functional demonstration. The electricalresults are expected to validate boththe D2W stacking tool and the directbonding technology.

The availability of a high accuracy pick-and-place tool that meets the requirements

of a direct bonding process paves the waytowards a new generation of 3D integrationtechnology. Improved placement accuracyprovides higher contact density andbetter electrical performance comparedto traditional eutectic bonding for 3Dsystem-on-chips. Direct bonding is acore technology that provides robust self-sealing for D2W stacking. It eliminates theneed for any underll material. As shown

in Figure 4, it enables stacking more thantwo die.

C o m b i n i n g t h e t e c h n o l o g i e sdeveloped within PROCEED andthe results from a prior project calledVERDI, which was focused on high-density TSV integration (diameter2-5m) and ul t ra- th in Si wafersstacking (thickness 10-25m), will

allow development of a full processintegration ow for the next generation

of high-performance 3D system-

on-chips moving forward. This willenable a wider range of applications in

m i c r o e l ec t r o n i c s a s w e l l a s i noptoelectronics and in MEMS, includingapplications requiring high-density3D interconnects, such as photonics,multimedia and wireless.

However, the need to first explore thechallenges of providing low roughnessand zero-defect surface, as well as ultra-clean D2W stacking compatible with cleanroom specifications, makes a researchand development project like PROCEEDmandatory to develop commonality inboth tools and processes before rampingup this technology to industrialization.

Characterization and MetallurgyCEMES-CNRS fills the tasks of

characterizing the bonding quality andof analyzing previously unobservedchanges that occur in the coppermetallurgy during the annealing step.Compressive stresses or annealing stepsat intermediate temperatures are knownto facilitate the assembly of two wafers

covered with copper films. Thisis a key step in creating strongerbonds for a stack of various chipsin 3D. However, the mechanismsthat lead to the full bonding of

the copper-to-copper interfaceare not completely known.Investigating these mechanismswas an important part of thelaboratory program.

Various forms of TransmissionElectron Microscopy (TEM)were employed as the maintools in this investigation. After

having annealed copper-covered waferassemblies at temperatures of 100,200, 300 and 400C, cross-sections

were cut perpendicular to the bondinginterface. They were thinned down to

200m to form TEM-observable foils.The TEM observations clearly show

that as the annealing temperatureincreases, the initially flat copper-to-copper in ter face i s gradual ly

transformed into a zig-zag shape. Thischange in itself leads to a stronger bond.Figure 5 shows an example.

Directly annealing a sample insidethe TEM (in situ TEM) further showedthat this zig-zag shape is initiated bythe rapid diffusion of copper atomsalong the grain boundaries. Diffusioncones are formed at the intersection ofthese grain boundaries and the copper-to-copper interface, and spread untila thermodynamically stable zig-zag

structure is formed.The effect of grain orientation ondiffusion is being further investigatedu s i n g a n e w T E M A u t o m a t i cCrystallographic Orientation Mappings y s t em , p u r ch as ed t h r o u g h t h ePROCEED project. Figure 6 shows howthis system is able to capture the variousorientations present in the Cu-bondedinterface before and after the assembly.

Results

The pick-and-place equipmentdeveloped for this task was shownto meet the specifications andto perform well in particulatec o n t a m i n a t i o n c o n t r o l a n dalignment accuracy.

Significant progress was madein the die surface preparationprocess, with new and more effectivechemistries created. Additionally,a specific adjustable dilution anddistribution system was developedfor surface treatment, which could beintegrated into the nal equipment.

Figure 4. Three die stacking sample with copper to copper

bonding pads

a b c

Figure 5. TEM images of the copper to copper interface after direct bonding and annealing at various

temperatures. Note the decreasing flatness of the interface, especially at grain boundaries. a) RT to 100C;

b) RT to 300C; c) RT to 500C


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Bonding with the new equipment andnew surface treatments was successfulin producing functional daisy chainswith more than 10,000 contactsat a 7m pitch, demonstrating thecapability of this approach.

A dedicated 3D test chip with

embedded active structures wasintegrated following a full CMOS65nm node process ow.

Observations of metallurgicalchanges during annealing revealedpreviously unknown temperaturedependent changes in surfacestructure by the rapid diffusion

of copper atoms along the grainboundaries.

ConclusionProject PROCEED has more than met

its goals. New equipment, materials,skills and processes were combined to

demonstrate that high-density copper-to-copper direct bonding is achievableand practical for 3D assembly, andhas major advantages over olderapproaches. The demonstrations werea success and have opened the gates tofurther progress in high-density directcopper bonding of 3D assemblies.

Figure 6. TEM-ACOM maps of the bonded copper to copper interface before (up) and after (down) direct

bonding and annealing at 400C. The differing colors relate to the different crystallographic orientations of thegrains present on both sides of the interface

AcknowledgementsThe PROCEED Minalogic project is a

2.4 million Euros, 24 months undertakingsuppor ted by French FUI (FondInterministriel Unique) with the objectiveof demonstrating high placement accuracy

(< 1m) of chip to wafer structures bydirect metallic bonding.

Gilbert Lecarpentier, SET, may be

contacted at [email protected];

Marc Legros, and Mayerling Martinez,

CEMES-CNRS, may be contacted at

[email protected] and mayemartinez@

yahoo.com; Alexis Farcy and Brigitte

Descouts, STMicroelectronics, may be

contacted at [email protected] and

[email protected]; Emmanuel

Augendre and Thomas Signamarcheix,C E A - L E T I , m a y b e c o n t a c t e d

[email protected] and

[email protected]; Vincent

Lelivre, and Aziz Ouerd, ALES, may

be contacted at vincent.lelievre@

airliquide.com and Aziz.OUERD@

airliquide.com.
http://www.esi.com/


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T h e i n c o r p o r a t i o n o f increasingly thinner wafersis fundamental to the developmentof next-generation 3D packages andelectronic devices. Through siliconv i a s ( T S V s ) , s t a c k e d m e m o r y,2.5D and 3D interposers, MEMSdevices, system-in-package (SiP)and advanced thermal management

are requiring thinner substrates tomeet increased elect r ical needs,smaller packaging requirements, andincreasingly complex designs. Silicon,the tradi t ional base substrate forsemiconductor and micro-fabrication,becomes increasingly fragile as itsthickness decreases making mechanicaldicing more challenging. Besides thechallenge of working with thinnerdevices, there is a push to improve yield,develop increasingly complex stacks and

better utilize wafer real estate all whilemaintaining cost of ownership (CoO). Toaddress these challenges, developmentsfor laser processing techniques for laser-only dicing are underway.

Dicing ChallengesAs device wafer thickness decreases,

new challenges arise when dicing.Silicon, which is normally a rigidmaterial, becomes flexible. Below athickness of 50m, a silicon wafer

bends like a piece of paper rather thanthe rigid substrate most are accustomedto. Thinner wafers have a higherprobability of generating significantcracks and cleaving from the smallestof defects. Similarly, deections in the

substrate during dicing induces stressthat increases the likelihood of defectsand die failure.

W h i l e s u b s t r a t e t h i c k n e s s i sdecreasing, the associated electronicsand mechanical devices are becoming

increas ing ly complex . Dic ing asemiconductor product wafer requires

Laser Processing: A Robust Solution for DicingUltra-Thin SubstratesBy Kip Pettigrew, Matt Knowles and Michael Smith[ESI]

going through a myriad of materialstha t vary g rea t ly i n mechan ica lproperties. Brittle layers such as low-kmaterials and silicon nitride are easilychipped and damaged. Thick die-attach films (DAF), which are usedto package die during the assemblyprocess, can be viscous and tacky whencut mechanically. Changes in the base

substrates present an additional dicingchallenge. Glass, ceramics and galliumarsenide are examples of popularsubstrates that are replacing siliconfor many applications and presentunique mechanical challenges to diceand machine.

I m p r o v i n g w af e r u t i l i z a t i o n ,e l i m i n a t i n g p r o c e s s s t e p s a n dminimizing costs are crucial for anyelectronics manufacturer to staycompetitive. Any discarded part of

a wafer could have accommodatedan addit ional die and brought inrevenue. Not all devices have identicalfootprints and it becomes progressivelymore challenging to singulate everydie on a wafer while simultaneouslyminimizing waste.

Techniques for Laser ProcessingLaser processing involves using a

specific wavelength of coherent lightto ablate mater ial in a

controlled manner. Thistype of processing has beenwidely used for many yearsin macro-scale drilling,cutt ing, and engraving.As control systems andop t i cs have improved ,laser techniques have beenapp l i ed to sub-micronresolution machining suchas memory r epa i r fuseblowing, wafer & LED

scribing, and wafer scoring.Taking these processes a

step further, dicing techniques havebeen developed that cleanly cut throughvarious electronic stacks on a wafer,the base substrate, and underlyingfilms. Multiple wavelength types canbe used to hone a specic process but

for most applications described in thisarticle a 355nm laser was used.

Traditional laser processing moves a

pulsed laser beam across the substrate,ablating material as it goes. Thismanner of laser processing is similar tocutting a material with a saw. Slow laserprocessing generates heat affected zones(HAZ) that induce stress in the substrateand subsequent layers. Much like stressfrom mechanical processing, prolongedthermal stress can damage the electricalstack, change material properties, andjeopardize structural integrity.

To avoid these thermal effects,

a zero over l ap t echn ique wasdeveloped to remove material along adesired dicing path. This allows heatto dissipate and thereby minimizesthermal impact and induced stress. Thismethod precisely places individualpulses along a line at a high rate insuch a way that pulses are never laiddown adjacent to one another. Spacingthe pulses also prevents energy lossesfrom laser interaction with ablated

Figure 1. Laser Diced 50um, 75m and 100m silicon substrates


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material, and allows maximum powerdelivery to the target.

Precision galvo-control enables1-2m spot placement accuracy (relative

to other spots) at up to 4.5 m/sec. Laserdicing techniques have been perfectedfor wafers under 100m in thickness,while cutting through a wide varietyof devices and films. Figures 1 and2 show cross sections of laser diced50m blank substrates and a scribeddevice wafer respectively.

Material SelectivitySelective processing and integrating

new materials into electrical devices

i s e s s en t i a l t o n ew t ech n o l o g yd e v e l o p m e n t . H o w e v e r , w h i l ea m a t e r i a l m a y h a v e a d e s i r e dengineering property, this benet often

comes with additional processingchallenges. This is commonly seenwhen developing processes includingceramics, glass, low-k materials,organic f i lms, and rare materialssuch as diamond. Similarly, a devicecontaining differing materials withdrastically different properties creates

the dicing challenge of not damagingany single layer while still quicklycutting through the entire stack.

Dicing in stages has been the triedand true method of deal ing withmaterial complexity, but with thinnerwafers, thicker electrical stacks, and theaddition of viscous materials such asDAF, a more versatile solution for allthe layers simultaneously is necessary.

Laser-only d icing addresses adiverse material stack by shifting

the dicing parameters (power, speed,etc.) continuously throughout the

process. Parameters such as power,wavelength (355nm), speed, focusheight, pulse rate and spot size (8m1/e2) are adjustable. As each layerof the device is diced, laser dicingparameters can be tailored to address

the specific material requirements.For example, a three stage recipe

is the best approach to dice a stackconsisting of standard semiconductorfilms and layers, a silicon substrateand a DAF. The delicate electricalcomponents may be diced at lowerpower to better control the removalof thinner and fragile dielectrics andmetals. After the electrical stack, thepower is increased to cut through thesilicon with an adjusted pulse rate to

optimize throughput. Finally, when theDAF is reached, dicing parameters canbe adjusted again to meet the materialspecifics. One could go further to usemultiple lasers at different focus heightsor spot sizes. The selectivity of the laserrecipes parameters to different materialscould then be changed to protect somematerials and target others whileminimizing processing time. Figure 3shows a cross section of a diced waferwith device layer, silicon, and DAF.

Making the Most of Wafer Real EstateScribing and then cleaving silicon

along the natural lattice structureis a common way to dice wafers.While cleaving works when dicingpure silicon, it becomes increasinglydifficult with the addition of fragilee l ec t r i ca l s t ack s an d p a t t e r n edfeatures, and is limited to cross-waferdicing and rectilinear dicing patterns.Semiconductor substrates, however, are

traditionally circular. Square die resultin increased waste near the wafer edge.

Laser d i c ing methods a re no tconstrained to perpendicular dicinglanes. Hexagons, asymmetric deviceshapes, curved patterns, through holesand partial cuts are easily performedwithout cutting into adjacent devicesor having to sacrice wafer real estate.Examples of nontraditional dice shapeseasily produced with laser dicing areshown in Figure 4. Hexagons are aneasily repeatable pattern that betterconform to the rounded wafer edges.Similarly, using a mix of octagonsand squares allows for two die to beproduced at the same time and have aflexible wafer footprint. Asymmetricpatterns allow for a wider array oflayout options as well as the exibility

t o i nco rpora t e i n t eg ra l coo l ingtechnologies to battle the thermalchallenges inherent with 3D designs.

The width of a dicing line, or kerf,has historically been set by the width ofthe blades needed to dice the materialwithout excessively damaging thesubstrate. With laser dicing, the spotsize is limited by optics and the spaceneeded to effectively eject ablatedmaterial from the dicing lane. Dicingkerf widths of ~20-30m cut with

micron resolution precision are easilyachieved when using a 355nm laserto singulate 50m thick wafers. Thindicing lines also free up additional realestate to the wafer. As the number ofdie and required dicing lanes increase,minimizing the kerf width allows formore die to t on each wafer.

Working with Complex, SOI orFragile Substrates

MEMS dicing is challenging because

both electrical and mechanical design arecritical to producing the next generation

Figure 2. Laser diced device and substrate

Figure 3. Example of laser dicing through very

dissimilar layers: 50m silicon and organic die-attachfilm

Figure 4. Laser diced die patterns with 35m dicinglanes


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of devices. Many MEMS devices suchas gyroscopes and accelerometers havecomplex 3D structures that themselvesneed to be in tegrated in to a 3Dstack. Other devices, such as MEMSmicrophones, have fragile membranes

that are easily ruptured. The laserslack of mechanical contact enablesprocessing on fragile substrates withoutany signicant jarring to the wafer.

The concept of dicing should not belimited to through wafer processing.Silicon-on-insulator (SOI) wafers arecommonly used to build devices on aburied oxide layer. Traditionally, thefinished devices must be singulatedus ing deep r eac t ive i on e t ch ing(DRIE) before they are released from

the buried oxide. This requires anadditional masking process, involvingexpensive equipment on potentiallydelicate devices. Partial laser dicingthrough only the device layer of anSOI wafer is a fast and masklessprocess that permits the releasing ofdevices without additional lithography,vacuums, or post processing.

For complex MEMS devices, laserprocessing has the advantage of beingable to cut on any plane parallel to the

wafer surface. Material can be removedfrom the center of a recessed area byshifting the focus of the dicing beam,eliminating the need for a mask orcomplex 3D lithography. Holes canbe diced into the middle of a die at thesame time as the primary dicing lines,saving process steps and lead time. Stepetching and generating through holesin a device are common processes,especial ly in f luidic designs andintegrated cooling solutions.

Maintaining Die Break StrengthD i e b r e a k s t r e n g t h ( D B S ) i s

commonly characterized using a three-point bending test. Chips and defectsin the die result in faster fracture ofthe substrate and a lower DBS. Laserdicing, when running at high dicingspeeds, can produce small defectsin the substrate akin to mechanicaldicing at high velocities. These defectslower the DBS of the die and must

be addressed in post processing toeliminate this concern.

There are several ways currentlyused to address the DBS weakeningin thin substrates either by annealingthe die or by healing the areas wheredamage may have occurred. As part ofthe post laser dicing process, a short

XeF2 etch may be used to removethermally stressed HAZ material andimprove overall die performance. XeF2preferentially etches exposed siliconand stressed areas. A post-etch chamberwas integrated to the laser dicing tool tominimize processing time and maintainhigh throughput.

Laser-diced wafers without any postprocessing have minimal chipping andsomewhat lower DBS as compared tomechanical techniques, typically of

order 250MPa. With the added XeF 2post processing, DBS over 500MPa areeasily achieved.

Weighing the Pros and ConsThere are pros and cons to using

laser processing that largely dependon the devices being singulated. Thebiggest limitation is the thickness thatone can dice quickly with a laser. Aswafers get thinner, the speed at whicha traditional saw dices a wafer must

decrease to minimize damage to thesubstrate. Conversely, the thicker thewafer, the more passes it takes a laser todice completely through the substrate.Evaluating silicon wafers, the CoO,and potential for wafers diced per hour,laser vs. saw dicing are competitiveat a wafer thickness of 50m withrectangular die, all other things beingequal. The general trend of this CoO vs.wafer thickness is shown in Figure 5.

For wafers with a thickness greater than50m, specic device requirements such

as non-rectangular die or mixed useapplications may still drive customersto select laser processing over saws. Asmentioned throughout this article, there

are advantages to both and ultimatelythe requirements and materials of thedevice stack must be considered todetermine the best dicing option.

ConclusionAs devices become increasingly

complex and micro-fabrication becomesmore competitive, it is crucial tocontinually develop new tools andsolutions to allow innovative designsto come to fruition. Laser dicing is a

robust solution to the challenges ofthin-wafer dicing, working on fragilesubstrates, maximizing wafer realestate and permitting the inherentcreativity required to meet the needs ofa demanding electronics market.

AcknowledgementsSpecial thanks to Daragh Finn, Jim

Dumestre, Chi-Cheng Lin, Bong Cho,David Lord and Jim O Brien of ESIssemiconductor applications team for all

their work, help and experience.

Kenneth (Kip) Pet t igrew, senior

marketing engineer, semiconductor

products division, ESI, may be contacted

at [email protected]. Michael Smith.

applications engineer, ESI, may be

contacted at [email protected]. Matthew

Knowles, senior product marketing

manager, ESI, may be contacted at

[email protected].

Figure 5. Laser verses mechanical dicing Cost of ownership as a function of wafer thickness


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Th e c u t t i n g e d g e o f t h esemiconductor packaging

industry is seeing what is probably thelargest series of simultaneous changesin both its assembly methodologiesand basic infrastructure since the movefrom thermionic valves to silicon overfty years ago. The advent of 2.5D and

3D assembly processes is accompaniedby significant process complexitiescaused by through silicon vias (TSVs),

thinned die, 450mm wafers, ever morefragile interconnect-layer dielectrics,and the criticality of doing all this whilemaintaining acceptable yields. Therelentless driver is the price-elasticgrowth of the electronics industry 1, thebasic principle behind Moores Law 2.

One common factor underlies thesechanges: there must be reliable electricalinterconnects between the devices.It is becoming apparent that extantmaterials and processes are evolving

to meet the challenges; providingextensions of known quantities, ratherthan relying on the process engineerto implement yet one more changeamongst many. As has been pointedout, the essential process in [all] solderjoining is the chemical reaction between[substrate metallization] and tin toform intermetallic compounds having astrong metallic bonding 3.

The focus of this paper is solderand ux usage in these more advanced

t echnologies , wi th special focuson those processes where solder isimmediately adjacent to the die surface.As will be seen, despite competing gas-phase4 and solder-free5 processes, fluxand solder are denitely not going away

in the near term.

Flip-Chip BackgroundThe history of flip-chip assembly

goes back to the earliest days of tapeautomated bonding and the IBM C4process6. Market projections show thatflip-chip wafer starts for combined

Solder in the Age of 3D Semiconductor AssemblyBy Dr. Andy C. Mackie, Global Product Manager and Tae-Hyun Park, Country Sales Manager[Indium Corporation]

copper pillar and solder bump ip-chip

for the top 14 companies is showingan 18.6% annualized growth rate7 from2009-2012, with growth in copperpillar as the main market driver. Table1 shows several means of puttingsolder onto underbump metallization(UBM) pads.

O n e p r o c e s s o r m a n u f a c t u r e r

announced that for many of their

multicore die, the I/O pitch will seea modest reduction from 180m to165m pitch for the foreseeable future,and will continue using standard flip-chip assembly processes. Meanwhile,their portable products are already at the40m pitch node using copper pillars,and will presumably shrink in pitchfurther into the future.

Copper pillars on wafer surfacesa r e a l m o s t a l w ay s cap p ed w i t hmicrobump solder. Although there

are some instances in larger pitchapplications (80m and above) wherepure t in (Sn) has been used as amicrobump solder, the most commonsolder in this application is an off-eutectic tin/silver (Sn/Ag)alloy, which is most oftenapplied by plating since itis then just the final platedlayer in a sequence. Thealloy target ranges from 1.5to 2.5% Ag, depending onthe plating process controlcapability and the desired

metallurgy of the nal reowed joint.

The standard method of turning theoften misshapen solder deposits intocoplanar, hemispherical microbumps[Figure 1], is to use a semiconductor-grade wafer bumping ux after the nal

resist-strip step, followed by cleaning.The ux is applied to the wafer surface

l ike a photoresist by a spraying/ dispensing process,then spun down to

produce the desiredthickness. For somewafer bumping houses,the high-aspect ratio ofmicrobumps on copperpillars has necessitatedsome changes in theway wafer bumpingf luxes a re app l i ed ,making flux rheology

a much more criticalcontrol parameter.

Resin-based fluxes are essential forhigh-melting alloys and have beenthe traditional means of reflowing90Pb/10Sn and 95Pb/5Sn solderbumps. With these alloys, even atthe very low oxygen levels used forwafer bumping flux reflow (usuallyless than 10ppm O2) water-soluble uxchemistries remain difficult to clean.However, as eutectic (63Sn/37Pb)and tin/silver (Sn/Ag) bumps havebecome prevalent, water-soluble uxes

have become the standard.Note that although there are knowninstances where a reactive atmosphereapproach may be used to reow solder

bumps8, the l imited capabil i ty of

Figure 1. Wafer-Bumping flux turns the misshapen solder deposits intocoplanar, hemispherical microbumps (Courtesy of Amkor)

Solder Application Method Common Usage

Solder paste printing Wafer and substrate (SOP)(paste type 5,6,7,8) bumping down to 125m pitch

Flux print Wafer level CSP down to 0.3mmand solder ball-drop pitch, and some wafer bumping

down to 80m pitch

IBM / Suess C4-NP Wafer bumping down to 20m(liquid solder) pitch or less

Solder plating Wafer bumping down to 20mpitch or less

Table 1. Solder application methods


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the process to has led to significantresistance to adoption for finer-pitchwafer bumping applications. Just someof the technical issues reported are9:

Soccer ball sphere shape defects Oxides and o rgan ic / r es idua l

photoresist contamination Inability to remove wafer probe-

marksEach of these defects can, of course,

play a role in subsequent voiding duringip-chip assembly.

Flip-Chips and InterposersSo-called 2.5D (interposer-based

assembly) is an enabling technology forthe increasingly fragile ultra low-k (ULK)dielectric materials in the interconnect

layer on the chip surface. The interposeressentially replaces the use of capillaryunderlls as a primary stress reliever for

chips fabricated with sub-32nm devices.However, underfill will probably stillcontinue as an added reliability enhancerin the chip-interposer stack up. Theinterposer is usually either itself made ofsilicon, or a glass/ceramic material with aCTE close to that of silicon. By matchingCTEs, the interposer reduces the stresson the microbump interconnects. The

processes used for forming low-oxide,coplanar solder bumps on interposersare exactly the same as those used forforming solder bumps on wafers, withplating being predominant.

Standard Flip-Chip Attach ProcessesIn ip-chip die-attach processes, two

kinds of ux may be used (Figure 2):1. A low viscosity flux sprayed or

jetted onto the substrate is veryeffective for smaller die with high

I/O counts, as long as wettingonto the substrate is consistent.These fluxes typically have low

Figure 2 . In flip-chip die-attach processes, two typesof flux may be used

solids content and can be easilycleaned off, even with tighter pitchconstraints. By using a heatedspray nozzle, a higher solids-loading flux can be applied witha lower viscosity, yet on cooling

is viscous enough to prevent driftand skew of larger die.

2. Dipping the solder bumps onthe chip into a flat reservoir ofmore viscous flux of a controlleddepth is more suited to larger(multicore) die. Improvements inprocess control of doctor-bladingand dipping processes, alongwith specialized flux chemistries,mean that a stable dip depth downto as low as 10m can now be

consistently guaranteed for rotarysystems. The subsequent reflowprocess is carried out in a reflowoven at less than 50ppm oxygen.

By combining processes 1 and 2, itis possible to get a flip-chip assemblyprocess that avoids intermittent contactnon-wet (CNW) issues, has zero dieskew, and is insensitive to incompletespray f lux wet -out onto varyingsubstrate photoresist surfaces.

Although uncommon, one large

processor manufacturer even uses ahigh-viscosity flux: printing it directlyonto the substrate before ip-chip attach

and reow.

Copper-Pillar Flip-Chip and Die-Bonding

Die to die (D2D) is the preferredassembly process and is capable ofhigh-yield manufacturing. The processuses either standard flip-chip assemblyand reflow, or thermocompression

bonding (TCB). The term TCB asapplied to flip-chip bonding isrelatively new10, although thetooling has been available for anumber of years. As an exampleof the extensibility of currentprocesses, one Taiwanese OSAThas established a 40m pitchmicrobump D2D process usinga dipped flip-chip flux. Thekeys to the success of the fluxare the flux rheology and the

solubility of the post-reflowresidue in deionized water.

csr november december-2011 digital

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