Current Source & Bias Circuits Current Source & Bias Circuits

Insoo Kim, Kyusun ChoiMixed Signal CHIP Design Lab.Department of Computer Science & EngineeringThe Pennsylvania State University

CSE598A/EE597G Spring 2006

04/22/23 Insoo Kim

IntroductionIntroduction Required Features of Current Source

High Rout Wide Operation Range Constant Current Source Low PVT (Process, Voltage, Temperature) Sensitivity

Required Features of Bias Circuit Low Rout Low PVT Sensitivity

Current SourceCurrent Source

• Basic Current Source• Wilson Current Mirror• Cascode Current Mirror

04/22/23 Insoo Kim

Ideal vs. Actual Current SourceIdeal vs. Actual Current Source

04/22/23 Insoo Kim

Simple NMOS Current SourceSimple NMOS Current Source

What’s the bad feature of this?

04/22/23 Insoo Kim

Cascode Current SourceCascode Current Source

What’s the bad feature of this?

04/22/23 Insoo Kim

Basic Current MirrorBasic Current Mirror

What’s the bad feature of this?

04/22/23 Insoo Kim

Wilson Current MirrorWilson Current Mirror

What’s the drawback of this circuit?

2

1

2

1

)/()/(LWLWI

ggII refm

mrefout

04/22/23 Insoo Kim

Cascode Current MirrorCascode Current Mirror

But, it still has limited output swing problem.

04/22/23 Insoo Kim

Wide Swing Cascode Current MirrorWide Swing Cascode Current Mirror

Bias CircuitsBias Circuits

• Self Bias Circuits• PTAT Bias Circuits• Band gap Reference

04/22/23 Insoo Kim

Power Supply Dependency of Current SourcePower Supply Dependency of Current Source

Consideration Factors - VDD

- Channel Length Modulation

- Transistor Mismatch

How do we generate Iref independent of the supply voltage?

04/22/23 Insoo Kim

Self Biasing CircuitSelf Biasing Circuit

What’s the advantage of these circuits?

What’s the problem of these circuits?

What’s role of Rs?

04/22/23 Insoo Kim

Improved Self Biasing CircuitImproved Self Biasing Circuit

Improved Circuit eliminating Body Effect

Improved Circuit with Start-up Circuit

* This Circuit is practical only if

04/22/23 Insoo Kim

A Simple Temperature Compensation ConceptA Simple Temperature Compensation Concept

M1(Vgs)

M1(Ids)

0℃90℃

ZTC (Zero Temperature Coefficient)

Negative TC Positive TC

Self Bias Circuit

VDD VDD

v vr0

M1

R11. R1 is a conductor which has positive TC 2. M1 has negative TC below ZTC point (Semiconductor)3. If we control Vr0 below ZTC point, Vr0 become less sensitive to temperature due to opposite TC of M1 and R1

04/22/23 Insoo Kim

Case Study (I) – Self Bias Circuit in DRAMCase Study (I) – Self Bias Circuit in DRAM

ⓐ ⓑ

starter

For Temp. Compensation pmos diode

ⓑ

ⓐ

vref

Vext

What’s the drawback of these circuits?

04/22/23 Insoo Kim

Case Study (II) – Self Bias Circuit in DRAMCase Study (II) – Self Bias Circuit in DRAM

ⓐ

Voltage Buffer

starter For Temp. Compensation

ⓐvr1

Why does this circuit need the voltage buffer?

Why are PMOS current mirrors stacked in the reference bias circuit?

04/22/23 Insoo Kim

VBE Referenced CMOS Self-bias CircuitVBE Referenced CMOS Self-bias Circuit

How do we fabricate BJT in CMOS Process Technology? * Temperature Sensitivity ~ - 4000 ppm/C

04/22/23 Insoo Kim

Realization of pnp BJT in CMOS TechnologyRealization of pnp BJT in CMOS Technology

04/22/23 Insoo Kim

Vth Referenced CMOS Self-Bias CircuitVth Referenced CMOS Self-Bias Circuit

04/22/23 Insoo Kim

Thermal Voltage Referenced CMOS Self-Bias CircuitThermal Voltage Referenced CMOS Self-Bias Circuit

04/22/23 Insoo Kim

Thermal Voltage Referenced CMOS Self-Bias CircuitThermal Voltage Referenced CMOS Self-Bias Circuit

* Temp. Sensitivity ~ +3300 ppm/C

04/22/23 Insoo Kim

CMOS Band gap ReferenceCMOS Band gap Reference

What’s the problem?

04/22/23 Insoo Kim

(cont’d) CMOS Band gap Reference(cont’d) CMOS Band gap Reference

Actual Implementation of CMOS Band Gap Reference

04/22/23 Insoo Kim

Actual Implementation of CMOS Band gap ReferenceActual Implementation of CMOS Band gap Reference

04/22/23 Insoo Kim

Design Lab. – Self Bias Circuit with Temp. CompensationDesign Lab. – Self Bias Circuit with Temp. Compensation

(a) Basic Schematic (b) actual implementation

Schematics

* AMIS 0.5um Tech

04/22/23 Insoo Kim

Design Lab. – Self Bias Circuit with Temp. CompensationDesign Lab. – Self Bias Circuit with Temp. Compensation

Simulation Results

VDDVr0b

Vr0 (a)

Vr0 (b)

04/22/23 Insoo Kim

Design Lab. – Self Bias Circuit with Temp. CompensationDesign Lab. – Self Bias Circuit with Temp. Compensation

Simulation Results – Temp. Compensation

Vr0 Current

(b)

(a)

(b)

(a)

90C25C

-10C -10C

25C90C

04/22/23 Insoo Kim

Design Lab. – Self Bias Circuit with Temp. CompensationDesign Lab. – Self Bias Circuit with Temp. Compensation

Zero Temperature Coefficient Point

0.82V

90C

25C

-10C

04/22/23 Insoo Kim

ReferencesReferences Joongho Choi, “CMOS analog IC Design,” IDEC Lecture

Note, Mar. 1999. B. Razavi, “Design of Analog CMOS Integrated Circuits,”

McGraw-Hill, 2001. Hongjun Park, “CMOS Analog Integrated Circuits

Design,” Sigma Press, 1999.