・ ARM is the registered trademark of ARM Limited in the EU and other countries.・ AMBA, ARM1176JZF-S, ARM7TDMI-S, ARM926EJ-S, ARM946E-S, ETM11, Cortex are the trademarks of ARM Limited in the EU and

other countries.・ HDMI, HDMI logo and High-Definition Multimedia Interface are trademark or registered trademark of HDMI Licensing, LLC.

Socionext Inc.Nomura Shin-Yokohama Bldg.,2-10-23 Shin-Yokohama,Kohoku-ku, Yokohama, Kanagawa, 222-0033, JapanTel. +81-45-568-1015

http://socionext.com/

Copyright 2015 Socionext Inc.PG06-00115-1E June 2015Edited : Custom SoC Business Unit

All Rights Reserved.Socionext Inc., its subsidiaries and affiliates (collectively, "Socionext") reserves the right to make changes to the information contained in this document without notice. Please contact your Socionext sales representatives before order of Socionext device. Information contained in this document, such as descriptions of function and application circuit examples is presented solely for reference to examples of operations and uses of Socionext device. Socionext disclaims any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality, accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the Socionext device based on such information, you must assume any responsibility or liability arising out of or in connection with such information or any use thereof. Socionext assumes no responsibility or liability for any damages whatsoever arising out of or in connection with such information or any use thereof. Nothing contained in this document shall be construed as granting or conferring any right under any patents, copyrights, or any other intellectual property rights of Socionext or any third party by license or otherwise, express or implied. Socionext assumes no responsibility or liability for any infringement of any intellectual property rights or other rights of third parties resulting from or in connection with the information contained herein or use thereof. The products described in this document are designed, developed and manufactured as contemplated for general use including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured, could lead directly to death, personal injury, severe physical damage or other loss (including, without limitation, use in nuclear facility, aircraft flight control system, air traffic control system, mass transport control system, medical life support system and military application), or (2) for use requiring extremely high level of reliability (including, without limitation, submersible repeater and artificial satellite). Socionext shall not be liable for you and/or any third party for any claims or damages arising out of or in connection with above-mentioned uses of the products. Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners.

Custom SoC (ASIC)

Automotive DigitalAVIndustrials

Amusement

OANetwork

MobileCommuni-

cation System constructionsupport

High-end platformMid-range platform

IP macros

Interface macrosAnalog macros

ARM® core macros

Advanced processtechnology,

Advanced front and back ends technologies,

Quality and reliabilitymanagement

system SoC developmentsupport services

Upstream designPrototype board development

Logic verificationPCB co-design

SoftwarePlatform

Linux BSP, Driver Middleware

Subsystems

Power savingNetwork standby

response subsystemSecurity

Providing Custom SoC Solutions that Bring Out New Value in Next Generation Products

C O N T E N T S

• 1. Custom SoCs (ASICs) .................................................................. 1• 2. System construction support ......................................................... 4• 3. High-Performance Subsystems ................................................... 5• 4. IP Macros .................................................................................... 7 – ARM® Core Macros – Interface Macros – Analog Macros

• 5. SoC Development Support Services “DesignExpress®” ............ 14• 6. Advanced Process Technologies................................................ 15• 7. Advanced Front and Back Ends Technologies ........................... 16

With increasing functionality and performance of SoCs, it has become difficult to develop SoCs in a short

turn around time. In the Custom SoC BU, we have cultivated know-how and a performance record over the

past forty years, and by adding new technologies we can provide SoCs that meets the needs of our

customers in a very short turn around time.

Using techniques of system architecture design and development support service, software platform

subsystem, plentiful IP line up, and state of the art wafer processes, we develop SoCs of “One Step Ahead”

system Level. We believe our role is to propose and provide custom SoC solutions that create new value in

next generation products.

solu tionCusto m SoC

Custom SoCC

ustom S

oCs (A

SIC

s)

1 2

Custom SoCs (ASICs)

The development of System on Chip (SoC) design is advancing rapidly with the use of different CPU cores, as well as a variety of embedded high-performance buses, high-speed IP and OS to meet today’s performance requirements. At the same time, the selection of components is complicated by the large number of combinations, which also slows the development of SoC design.

To deal with this situation, Socionext has developed a custom SoC solution, which integrates our advanced device implementation and manufacturing techniques cultivated by our extensive experience with ASICs, design services, and development tool kits. With this solution, we can support the development of SoC to be mounted on our customers’ products and rapidly provide high-performance and high-quality SoCs.

1. Full Custom DevelopmentFollowing the standard custom SoC development flow, we provide development support services such as advance software development at ESL, architecture search, reference design around the CPU, various subsystems and logic design/verifi cation to support our customers’ hardware design. We also support our customers’ software development, by offering contracted development services for device drivers.

As the point of reinforcement In Fiscal 2013, we began developing and offering various subsystems that substitute some of the functions of the main CPU to allow effi cient coordinated operations. A subsystem can be used to disperse the load for the main CPU or to reduce energy consumption. For details, please see the chapter for subsystems.

2. Platform-based DevelopmentAs an alternative to fully customized development, platform-based development can be used for applications that handle documents, image-processing and so forth. The strongly integrated evaluation kit with advance software development, verifi cation of RTL design code and chip verifi cation reduces the risk of development by addressing high-quality design, early startup and high performance within a reduced development schedule.

Comprehensive relation

BSP for our system prototyping kit

Base platform evaluation(CA9 board)

Linux BSP, driver

Custom SoC verificationsoftware development

(semi-customized board)

Linux

USBDriver

GbEDriver

I2C/SPIDriver

µT-KernelOS

Driver GraphicsProcessorsSD UHS-I

USB3.0Function ARM

CPU

GbE1000/100base

PCI-expressGen2-4Lane

DDR3 Controllerx32

Flash / SRAMI/F

UserLogic

USB3.0Function

GraphicsProcessors

ARMCortex-XX

SATA2Gen2 Host

USB2.0Host/Function

GbE1000/100base

Touch PanelI/F

SD UHS-I

LCD I/F 2ch

PCI-expressGen2-4Lane

PCI-expressGen2-4Lane

DDR3 Controllerx32

Flash / SRAMI/F

Serial Flash

IPsec NetworkOff-road engine

x 2ch

SPIUART

I2SI2C

GPIO

(CA9 board)

PF customization+ user logic

Base platform(design)

Device manufacturing

IC package

Standard cell Macro embeddedtype Gate array

IP macro(ARM-IP, High-speed I/O, Analog macro)

Subsystem(Electric-power saving, Security)

Base platform(High-end and mid-range platform)

Software platform(Linux, μT-Kernel, Device driver)Architecture

exploration support

Development support service

Advanced process

Front-and back-endtechniques

High-reliability testing

Socionext’s “Custom SoC Solution”

Specification design

Hardware design

Software design

Hardwareverification

LSImanufacture

Specificationquality

Reference design/evaluation board

FPGA board SoC verification/software development

Chipverification

Prototype board development

ESL performanceevaluation

High-ordersynthesis

PCB coordination design

Blockverification

Provision of subsystem and various IPs

SoC implementation/manufacture

Software verification

Logic design service

Developmentflow

Systemexaminationsupport

Various IPs/subsystems

Device implementation/manufacture

Development support service DesignExpress®

Systemtest

Software development service

Custom SoC Solution

UDL

CPU

Sub System

IPIP

Cortex systemBase PF

(Customize)UDL

1. Full Custom Development 2. Platform-based Development

As the development using a custom SoC solution, we provide roughly two types of development menus depending on the customer’s application, development period, and budget.

Development Method using a Custom SoC Solution

Custom SoCC

ustom S

oCs (A

SIC

s) / System

construction support

3 4

Application for Image-Processing Products

Cortex-A9MPcore（2 cores）

Cortex-R4F Cortex-M3

Touch PanelI/F

2D/3DGraphics

Processors

LCD I/F 2ch

DDR3 Controllerx32

Serial Flash FLASH32/16MB

DDR32GB

Keypad

SD Card

For the external model, implement to FPGA

as a dummy

PC

Wi-Fi

UDL/JPEG/DSP（FPGA）

CCD/CMOS（Dummy）

Autofocus（Dummy）

SD UHS-I

I2SGPIO

Speaker Mic

Application for Printer Products

Cortex-A9MPcore（2 cores）

Cortex-R4F Cortex-M3

USB2.0Host/Function

GbE1000/100base

Touch PanelI/F

2D/3DGraphics

Processors

LCD I/F 2ch

DDR3 Controllerx32

Serial Flash FLASH32/16MB

DDR32GB

IPsec NetworkOff-road engine

x 2ch

Keypad

SD Slot

For the external model,implement to FPGA

as a dummy

PC

USB2.0Host/Function

UDL（FPGA）

Print Engine（FPGA?）

Motor（FPGA?）

SD UHS-I

I2S

I2CGPIO

ScanScan

Speaker

HDDSSDSATA2.0Host

I2C

USB2.0Host/Function

USB2.0Host/Function

SD UHS-I

LCDtouch panel

LCDtouch panel

LCDtouch panel

LCDtouch panel

As an example of application development, the product prototype can be constructed easily by allocating necessary functions to the IPs and applications on the evaluation chip. This makes advance development of device drivers, OS mounting, and application software possible.

When we adapted the platform-based development to our ASSP product, commercialization was achieved six months earlier than with the conventional design method. This rapid time-to-market was achieved by shortening the hardware design period for SoC development and by front-loading the software development period.

• Date of receipt of ES (Engineering Sample) : Six months ahead of schedule• Software advance development: Eight months ahead of schedule• Product shipping: Six months ahead of schedule

Applications

Benefi ts of Platform-based Development

Specification design

Specification | Logic design and verification | ES manufacturing

Specification | Advance evaluation and development Software development

Date of receipt of ES: Six months ahead ofthe schedule

Date of receipt of ES: Six months ahead ofthe schedule

Design and verification forperiphery of CPUCost reduction/period shortening

Design and verification forperiphery of CPUCost reduction/period shortening

HW

HW

SW

SW

Full custom development

Platform-based development

Specification design | Logic design and verification | ES manufacturing

Software development

Software advance development:Eight months ahead of the scheduleSoftware advance development:Eight months ahead of the schedule

System construction support

We provide high-end and mid-range platforms, depending on the performance requirement for the product.

1. High-end platformHigh-end platform includes Cortex A15/A7 big. LITTLE processing and various IPs. It combines high-performance A15 (big) and compact and low power A7 (LITTLE) cores to achieve high performance and low power consumption.

By cutting down unnecessary blocks from this platform and by combining with the user logic, we can rapidly develop high-end custom SoCs.

2. Mid-range PlatformMid-range platform includes a microcontroller (M3), a real-time processor (R4F), an application processor (A9 Dual) and various IPs that can address a wide range of applications.

By performing cut-down from this platform and combining with the user logic, mid-range custom SoCs can be developed quickly.

Socionext is providing an SoC evaluation environment in order to preliminarily evaluate whether the architecture meets the requirements of the customer. With the evaluation environment, CPU selection, IP compatibility check, advanced development of software, and etc. can be performed. A custom SoC can be constructed by cutting down unnecessary blocks from the base platform of the evaluation environment and by combining with the customer’s logic.

Base Platform

Cortex A15/A7 big. LITTLE Base Platform (CA15-PF)

CPU and Memory IF Block

I2S

MIPI

MIPIMultimedia Engine

PCIe

USBHost

SDIO

High Speed IO

Media Processing Block

System Control Block

CCI （Cache Coherent Interconnect）

ARM®Cortex™-A15

ARM® Neon™

L1 Cache

L2 Cache

ARM®Cortex™-A15

ARM® Neon™

L1 Cache

ARM®Cortex™-A7

ARM® Neon™

L1 Cache

ARM®Cortex™-A7

ARM® Neon™

L1 Cache

L2 Cache

ARM®Mali™-T624

L2 Cache

LCDC

DDRSystemCTRL

GPIOI2CUART

SPI eMMCNOR

GbENAND

USBDevice

User logic

Cutdown

High speccustom SoC（A15, A7）

＋

Cortex A9/R4F/M3 base platform (CA9-PF)

User logic

Cutdown

Mid-rangecustom SoC

（A9, R4F, M3）＋

USB3.0Function

Cortex-A9MPcore （2 cores）

Cortex-R4F

Cortex-M3

SATA2Gen2 Host

USB2.0Host/Function

GbE1000/100base

Touch PanelI/F

SD UHS-I

2D/3DGraphics

Processors

LCD I/F 2ch

PCI-expressGen2-4Lane

PCI-expressGen2-4Lane

DDR3 Controllerx32

Flash / SRAMI/F

Serial Flash

IPsec NetworkOff-road engine

x 2ch

SPIUART

I2SI2C

GPIO

Custom SoCH

igh-Perform

ance Subsystem

s

5 6

Socionext provides its original subsystems for specifi c functions. In addition to the hardware, the Software Development Kit (SDK) is also available. These subsystems help to achieve high versatility and flexibility that enable differentiation of the customers’ products.

●Background and ApproachAs SoCs are getting more functional and highly integrated, power consumption is also increasing. At the same time, power saving is also an important requirement with the regulations for power consumption and increase of social awareness for energy saving. Against this background, we have developed an power saving subsystem that satisfies two conflicting elements: performance improvement and reduction of power consumption.

●OutlineWith the power saving subsystem, the following electr ic-power saving measures are integrated to achieve low power consumption.

• Network standby response such as Ethernet and USB• Centralized management of power gating and clock gating• Linkage with the electric-power saving function of the OS• Linkage with the power monitor

●OutlineThe network standby response subsystem reduces the power consumption of the SoC when it is not used for data communication via the network (standby). It enables the subsystem to cover (offl oading) the process of maintaining a network connection with a separate power source. Therefore, maintaining the response to the network while reducing the power consumption of the SoC is made possible.

During the stand-by status, the network fi ltering processes and packet processes are executed by the network standby response subsystem and the fi rmware on the SRAM within the subsystem.

●Features• High-speed execution of each process with the hardware

assist. (Checksum process, TCP/IP segmentation process, etc.)

• Offloading function enabling the load reduction at the main system side CPU

• Improvement of the communication quality by packet loss prevention function

• Network standby response function with the small scale circuit• Platform (OS) independent SDK

●Background and ApproachAs the use of the Internet and the cloud services continue to spread, security functions are required for various types of equipment.

In other words, protection of confi dential information stored in the network connected equipment and prevention of unauthorized access or illegal operation are extremely important. That requires the prevention of software falsification, monitoring by hardware, encryption of the network path, and so on. However, encryption calculation and authentication computing for these security functions impose a very heavy load to be processed only on a CPU. Therefore, applying such security functions to various units has not been easy. To address this problem, Socionext provides subsystems most suitable for the application of these security functions.

●OutlineBy using the subsystem based on the compact controller (micro engine), various types of offl oad functions are achieved. As well as those complex processes such as TLS and IPsec, offl oading functions including network process, general-purpose encryption, and authentication process are available. As high-load processes are executed by the dedicated hardware, the CPU load in the main system can be greatly reduced.

●Features• Support of various encryption and authentication algorithms

(DES/3DES, AES, ARC4, MD5, SHA1/256/512, etc.)• Various hardware offl oading and acceleration functions (TCP/IP

checksum, TCP segmentation, IPsec frame, TLS record, etc.)• Gigabit Ether MAC (optional)• Acceleration of exponentiation, multiplication, division and

remainder calculation required in RSA, by public key encryption calculation acceleration macro (F_PKA) (optional)

• Public key encryption calculation acceleration macro (F_PKA) also available as a stand-alone macro

• Platform (OS) independent SDK

Support AlgorithmIPsec TLS Generic

Encryption

DES-ECB / 3DES-ECB

DES-CBC / 3DES-CBC

AES-ECB *1

AES-CBC *1 *2 *1

AES-CTR *1 -

ARC4

AES-XTS *2

AES-GCM *1 *2 -

Authentication

MD5

(HMAC)

(HMAC)

SHA1 / SHA256

(HMAC)

(HMAC)

SHA512 AES-XCBC-MAC-96 *

3 -

key length: *1:128 / 192 / 256 bit *2:128 / 256 bit *3:128 bit

High-Performance Subsystems

Outline of Electric-power Saving Subsystem

Standbyresponse

Interrupting signal

Main CPU

UDLAlways ON

standby responsesubsystem

PMU (Power Management IP)

Domain splitting

Data

OFF→ON

Power gatingClock gating

Platform

Linux electric-power saving framework extended version

Outline of Network Standby Response Subsystem

Standby responsesubsystem

SoC

GMAC PHYUser

Logic1

CPU（micro controller）

CPU（micro controller） SRAM

MEMORYCtrl.

DRAMFLASH Memory

CPU x n ｐｃ（AP） DMAC

Mainsystem

During the network standby, only subsystem power supply turns on.Within the standby response subsystem, clock of each block turns on when required.

Operating: Power supply ONStandby: Power supply OFF

Standby: Subsystemmaintain the networkconnection

Standby responsemacro (F_TAIKI)

F_TAIKI provides a network accelerator function.

Always power supply ON

Outline of Security Subsystem

APBI/F

IKEAccel.

AXII/F

DMAControl

Micro EngineEncryption/

AuthenticationBlock

SecurityCore

Micro Engine

DMA section Sec core section

F_GM

AC （

Option ）

ControlRegs.

ControlRegs.

EtherFrame

Basing the subsystem configuration on a compact controller (micro engine) enables a wide variety of security functions such as IPsec and TLS.

Power Saving Subsystem

Network Standby Response Subsystem

Security Subsystem

Custom SoCIP M

acros

7 8

IP Macros

Socionext supports customers with the development of advanced SoC by providing high-quality macros verifi ed by its unique IP macro verifi cation system. We develop the rich lineup of IPs in-house, such as CPU, media processing, image processing, and communication I/F, and also prepare various types of IP by cooperating with third party vendors, to meet a vast range of customers’ demands with our cutting-edge technologies. We will continue our development around the circuit technology expertise cultivated on the high-end platforms, and provide stable and advanced IPs.

CY2016～CY2013 CY2014 CY2015

PC peripheral IF

Storage IF

Audio/Video IF

Memory IF

Mobile intra IF

High performance IFDevelopment

completedDevelopment

completedUnder

developmentUnder

developmentUnder

planningUnder

planning

DSIDSI LLILLI CSI2CSI2

SD / MMCSD / MMC

XFI,10GBESE-KR

XFI,10GBESE-KR

SFI-SSFI-S

CEI-11G-SRCAUI, XFI

CEI-11G-SRCAUI, XFI

MIPI M-PHY5.9Gb

MIPI M-PHY5.9Gb

LPDDR1LPDDR1 LPDDR3LPDDR3

SD4.1SD4.1

UFSUFS

LPDDR4LPDDR4

MMC4.5MMC4.5

M-PCIeM-PCIe

HDMI2.06G

HDMI2.06G

ＰＣＩ Express16Gb/laneＰＣＩ Express16Gb/lane

SSICSSIC

USB3.1USB3.1

PCI Express2.5Gb/lane

PCI Express2.5Gb/lane

PCI Express5Gb/lane

PCI Express5Gb/lane

PCI Express6Gb/lane

PCI Express6Gb/lane

SD4.0UHS-IISD4.0UHS-II

USB2.0Device/Host

USB2.0Device/Host

USB3.0Device/Host

USB3.0Device/Host

DDR4DDR4DDR3DDR3 DDR3LDDR3L

D-PHY2.5G~D-PHY2.5G~

D-PHY~1.5GD-PHY~1.5G

CEI-28G-VSRNext

CEI-28G-VSRNext

CEI-28G-VSRCAUI4（c2m）

CEI-28G-VSRCAUI4（c2m）

CEI-28G/11G-SRNext

CEI-28G/11G-SRNext

C-PHYC-PHY

USB3.0HDC

USB3.0HDC

HDMI1.32.25G

HDMI1.32.25G

HDMI1.43G

HDMI1.43G

SATA AHCI3~6Gb

SATA AHCI3~6Gb

SD3.0 /MMC

SD3.0 /MMC

LPDDR2LPDDR2

CEI-28G/11G-SRCAUI4, CAUI, XFICEI-28G/11G-SRCAUI4, CAUI, XFI

ARM CoresWith the comprehensive license agreement with ARM, customers can select the most suitable ARM core from the vast lineup to meet their requirements.

We provide the most suitable ARM core for custom SoC for a wide range of markets such as microcontrollers, embedded equipment, and application equipment.

These ARM cores are available on all process technologies that Socionext offers.

ARM PlatformsThe use of the SNAPs(Socionext ARM based SoC Platform) reduces develop time and risks in ARM core based SoC.

●ARM core based reference designs• Development of custom SoCs based on the verif ied

reference designs, greatly reducing time for design and verifi cation

• Reference designs optimized to each ARM core• Superior extensibility and high customizability• Test benches, simulation environments, and sample boot

codes provided• Available on all process technologies

●ARM core based prototyping environment• SoC prototyping environment combining our original ARM

evaluation chip and FPGA• Hardware system operation verification and performance

evaluation and software advance development• ARM11 based (ARM926 and ARM946 mounted) and

Cortex-A9 based (Cortex-M3 and Cortex-R4F mounted) custom SoC prototyping boards

• Rapid start-up of a prototyping environment made possible by using a “Prototyping Kit” (FPGA reference design, evaluation chip simulation model, etc.) prepared for each of the prototyping boards.

SNAPs are closely linked with Cedar® design service, and achieve fi rst-time perfect operation of custom SoCs.

Cortex-A9 Evaluation Board Cortex-A15 Evaluation BoardARM, ARM7TDMI-S, ARM926EJ-S, ARM946E-S, ARM1176JZF-S, Cortex and AMBA are the trademarks of ARM Limited in the EU and other countries.

ARM Core Based Prototyping Environments

ARM Core GPU Lineup and SNAP Roadmap

Application

Real Time

Micro- Controller

GPU

ARM7TDMI-S

ARM946J-S

Cortex-M3

Mali-400

Cortex-M0

Cortex-M4

T-624 T-678

Cortex-R4F

Cortex-A9Cortex-A5Cortex-A7

Cortex-A53

Cortex-M7

Cortex-A17Cortex-A15

ARM1176JZF-SARM926EJ-S

Available

Planning

ARM core Lineup

SNAP（Reference Design）Roadmap

GPU Lineup

~2013

SNAP11SNAP11 SNAP-A5SNAP-A5 SNAP-A7SNAP-A7SNAP926SNAP926

SNAP-A9SNAP-A9

SNAP946SNAP946SNAP-R4SNAP-R4SNAP-M4SNAP-M4

SNAP-A17SNAP-A17SNAP-A53SNAP-A53

SNAP-M7SNAP-M7SNAP7SNAP7

AvailableAvailable

DesigningDesigning

PlanningPlanning

SNAP-M3SNAP-M3

2014 2015 2016

SNAP Reference Design Block Diagram (CPU: Cortex-A9)

Cortex-A17 Reference Design

APBINTROM Ahb2Apb

DMAC（max 8ch） SRAM

DMACFor ACP（2ch）

ARM IP

ADK,Primecell

FJ IP

3rd IP

Base DesignGIC-400

TimeStamp

Local CRG

CPU Block

EXIU GPIO64chTIMER

2chUART2ch WDT MRBC PMU

PPU-A17

AMBA3 Interconnect（64bit）

AHB BusMatrix（32bit）

ClockReset

Cortex-A17core

CoreSightDebugSystem

Trace

JTAG

Sequencer

PLL Monitor

Main CRG

ARM® Core MacrosIP Macro Roadmap

Custom SoCIP M

acros

9 10

Interface MacrosSocionext provides interface macros that are optimized for various applications to support its customers’ advanced SoC developments.

USB3.0 5.0Gbps Eye Diagram

200ps

IP Evaluation Board and Connection Image

HDMI

USB3.05Gbps

HDMI Application

HDMIcable

Camcorder

Memory

Monitor

Image/Audioprocessingsection

Sensor Image sensor Microphone

Image/Audioengine

Panel/Speaker

HD

MI

-Tx

HD

MI

-Rx Digital

front-end

DDR InterfaceSocionext provides various DDR interface macros from low-to-middle speed forwarding bandwidth to high-speed forwarding bandwidth or low power, with our various process technologies. Moreover, we support custom SoC development by LSI-Package-Board co-design.

● DDR interface macros• High-speed/high-bandwidth DDR3/DDR4• Low power LPDDR2/LPDDR3/DDR3L• DFI compliant (all macro)• Compatible with many dif ferent DRAM configurations

and PKG options, such as Fly-by or PoP, by PHY function (training function).

●DDR interface design support (LSI-Package-Board co-design)• Timing verification: Verifies timing of all DDR-IF systems

including delays between LSI I/O and DRAM• Power Integrity: Optimizes the parasitic inductance,

resonant frequency, and power supply (PKG, PCB) impedance as the power supply impedance design

• Signal Integrity: Optimizes Driver strength, terminator resistance, and interconnect topology

PCI Express InterfaceAccompanied by the signif icant improvement of CPU processing capability and the increasing need for large-size data transmission, it is getting very difficult to achieve the expected architecture performance with the existing bus. PCI Express technology is a high-speed interface that enables data transmission of several hundreds of megabytes to solve this problem. Our PCI Express macro is applicable to maximum of 8 GT/s (Gen3). It has passed the PCI Express standard compliance test sponsored by PCI-SIG, and mutual connectivity and reliability with various types of PCI Express interface have been confi rmed.

●PCI Express LINK macro• Compliant with the standard regulation PCI Express Base

Specifi cation rev. 3.0• Supports lane numbers ×1/ ×4/ ×8.• DualMode (RootComplex/Endpoint selectable)• AMBA3 I/F selectable for user interface.• Integrated DMAC.

●PCI Express PHY macro• Maximum bit transmission rate 64GT/s• Warrants high-speed signal transmission by De-emphasis

function• LINK macro interface compliant with the standard regulation

PIPE3/PIPE4.

DDR Interface Configuration

MemoryController

User I/F

（APB）

DFI

DRAM vendors

OR

Test

CK, ADO,CMD, DM

DQ, DQS

DDR

DDR

DDR

DDR

DDRDDR

DDR

SSTLHSUL

I/ODDRPHY

PCI Express 3.0 8.0Gbps Eye Diagram

IP Evaluation Board

PCI Express macro mounted LSIPCI Express bus

125ps

USB 3.0 InterfaceWe quickly responded to the USB3.0 specifi cation and started developing various LSIs in 2009. We have a record of volume production with an accumulation total of 10M units, and our product was certified by USB-IF as the world’s first inter-operability test compliant device.

In addi t ion, we are developing PHYs for var ious technologies, and provide high-quality macros, which passed our verification including the compliance test, as a LINK + PHY total package. As the macro lineup, we have combinations of three types of Device / Host / HDC (Host Device Controller) LINK and PHY macros.

●Host/HDC macro• Intel xHCI (eXtensible Host Controller Interface) Rev 1.0

supported• Integrated DMAC

●Device/HDC macro• Endpoint for FIFO (Endpoint confi guration is changeable)

HDMI® InterfaceHDMI (High-Definition Multimedia Interface) is the industry standard specifi cation for connecting AV equipment such as camcorders, digital cameras, and HDD recorders to DTVs and PC monitors to transmit digital video and audio signals between these devices.

The latest version HDMI-V2.0 is applicable to 4K2K 60 fps (6 Gbps/ch) and HDCP2.2, CEC2.0. We provide controller and PHY macros that are compliant with the HDMI standard.

●HDMI macros• Non-compressed video transmission• Multiple channel (max 32) audio signal transmission• Contents protection by HDCP2.2• Dual viewing• 3D image and 4K2K (60 fps) panel• Control between devices under Consumer Electronics

Control (CEC) 2.0

Custom SoCIP M

acros

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SD4.0 InterfaceWe provide the Host macro that is compliant with the standard SD Ver 4.0 Specifi cation together with PHY. PHY is compliant with the UHS-II Bus-Interface Specification that was added from SD4.0 and achieves a transfer rate of 312 MB/s. In addition, a controller that is applicable to Legacy Speed IF (maximum 104 MB/s) is mounted, and connection with a conventional SD memory card is supported.

●SD4.0 Host macro• Compliant with SD Host Controller Specifi cations.

Part A2 SD Host Controller Standard Specifi cation Version 4.00.

• Compliant with SDIO Card Specifi cation. Part E1 Secure Digital Input/Output (SDIO) Card Specifi cation Version 4.00.

• 1, 4, 8-bit SD mode supported.• Single port supported.• Double buffer for transfer is mounted (512B, 1 KB, or 2 KB).• Data write protect detect function supported.• Card detect function supported.• Multiple read/write transfer supported.• 1- to 2048-byte transfer data length supported.• Read Wait Option function supported.• UHS-I and UHS-II speed mode supported.

10G-28Gbps SERDES InterfaceWith transmission performance of 10Gbps - 28Gbps per channel and confi guration comprising of multiple channels, we provide a high-performance SERDES macro for constructing 100G/200G/400G optical networks or 100G Ether systems.

The built-in low-jitter, high-performance PLL enables robust transmission up to 28Gbps per channel.

It also supports various standards including OIF-CEI-11G-SR, OIF-CEI-28G-SR, IEEE802.3ba CAUI, XFI and so forth.

• ×1, ×4 lane confi guration.• Comprising of Transmitter/Receiver/PLL and capable of

bidirectional communication with 1 macro.• Up to 112.8Gps per macro

(for unidirectional, ×4 confi guration).• Power-down control on each lane supported.• Power-down control for the entire macro supported.• Implementing Clock-Data recovery for each Receiver lane.• Transmitter Equalization supported.• Receiver Equalization supported.• Built-in termination resistor in Transmitter/Receiver.• Organic fl ip chip package.

(0.8mm/1.0mm Ball Pitch, HDBU & SHDBU Package)

SerialI/F

Transmitter

PLL

Receiver

ParallelI/F

28Gbps output waveforms on test chip

IP Evaluation board (SD40)

SD40 macromounted LSI

USH-Ⅱ Socket

• Re-tuning function supported.• Auto CMD23 supported.• SDMA, ADMA2 supported.• SD-TRAN supported.

●UHS-II PHY• Compliant with SD Memory Card Specifi cations.

Part1 UHS-II Addendum Version 1.00.Part1 Physical Layer Specifi cation Version 4.00.

• Maximum transfer speed 312 MB/s.• UHS-II 2lane (FD/2L-HD) supported.

MIPI LLI InterfaceWe provide LINK macro compatible with LLI Specification Ver. 1.0 and PHY macro compatible with MIPI M-PHY Specification Ver. 2.0 for MIPI, which is the standard for mobile applications. One of the major purposes of LLI interfaces is to share memory between chips, which reduces memory costs. In addition, extending functions with a companion chip connection is possible, and communication between those chips can be achieved with low latency.

●LLI LINK macro• Low Latency traffi c class supported• Auto SAVE function• AXI3.0/AXI4.0 bus interface• APB3.0 Register interface

●M-PHY macro• For HS transfer mode, supports up to HS-G3• For PWM transfer mode, supports from PWM-G0 to G7• Supports lane numbers ×2/×4.• Maximum transfer rate is 23 Gb/s (×4 lane)

Custom SoCIP M

acros / SoC

Developm

ent Support S

ervices “DesignE

xpress®”

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Data ConvertersWe offer various data converter macros addressing low power consumption and small area which are demanded in todayʼs systems, with various process technologies.

●High speed SAR type ADC• Smallest power consumption in the world within the same

class (1/10 of the conventional level)• 10bit/12bit resolution, 50MS/s, 200MS/s conversion rates• Can replace exist ing pipel ine type ADC in mobi le

communication fi eld

●ΔΣ type ADC• Applicable to 16bit - 24bit resolution.• Power consumption of 0.84mW with high precision of

SINAD 85dB.• Optimal for analog signal conversion for various sensors

●ΔΣ type DAC• Applicable 16bit - 24bit resolution.• SINAD 90dB.• Can be used for audio output applications in various electric

products.

●Audio CodecWe provide stereo codec (ADC + DAC) and mixed signal front-end for high quality audio applications.

• Line Inputs: 2 channels each of stereo/mono, and 2 channels of Mic input

• 1 channel of stereo headphone output.• ADC capable of SNR 90dB and DAC SNR 95dB.

Various data converters

0.010 2 4 6 8 10 12 14 16 18 20 22 24

10

1

100

0.1

1000

10000

Resolution [bit]

Con

vers

ion

Freq

uenc

y [M

Hz]

Audio/Audio Codec

Sensor/ΔΣ type ADC

Communication,image/pipeline type ADCCurrent type DAC

High speed IF/Flash type ADCCurrent type DAC

Communication/high speed SAR type ADC

Current type DACControl/SAR type ADC

Low speed DAC

DesignExpress®Analog MacrosWe offer various analog macros (ADC/DAC temperature sensor touch panel AFE DCDC LDO) for our customers’ SoC development to address various applications including communication, image processing, sensor and control.

• All macros silicon verifi ed.• Implemented on many custom SoCs with records of volume production.

This design service provides a consistent development support from specifi cations to system evaluation and PCB design in custom SoC development of our customers. By utilizing this service, our customers can achieve reduction in development period and remake risks, and improvement in product quality and power consumption.

List of development support services• Advanced software development and performance evaluation service under a virtual environment (Cedar®-ESL)• High-order synthesis support service (Cedar®-HLS)• Logic design service• Software development service• Prototype board development service addressing hardware operation verifi cation (Cedar®-PROT)• PCB coordination design support service (PLACATE®)• Specifi cation document-level quality improvement and verifi cation item extraction service (Cedar®-SPEC)• Third-party verifi cation service utilizing random and assertion-based verifi cation technology (Cedar®-SIM)• Large-scale/long data verifi cation and power consumption calculation service utilizing an emulator (Cedar®-EMU)

Power ManagementWe offer various power management macros that enable single power supply development demanded in SoCs with various process technologies.

• DC-DC converter for large current supply applications (switching regulator).

• LDO for low noise power supply applications (linear regulator).

Temperature SensorsWith the features of low power consumption and small area, our temperature sensors with built-in high-precision ΔΣ ADC enable chip temperature measurement at multiple points. They can be used in voltage or frequency control applications where the chip temperature needs to be maintained below the specifi ed value.

Touchscreen AFETouchscreen AFE supports 4-wire resistive fi lm touchscreen panels. This AFE has a built-in driver circuit for operating resistive fi lms, and supports the touch position detection, pen pressure detection and pen interrupt functions. 12bit/10bit SAR ADC is used for detection operation to allow high-precision measurements.

SoC Development Support Services “DesignExpress®”

PCB design

Manufacture

Relationship between custom SoC development flow and development support service

Softwaredevelopment

serviceSoftware

development

Cedar® Logic design service

System specification examinationSystem specification examination

PLACATE®

Custom SoC designCustom SoC design

System evaluation

Logic design

Physical design

Custom SoCA

dvanced Process Technologies / A

dvanced Front and Back E

nds Technologies

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The scaling of processing technology of semiconductors has come down to the deep submicron nodes, and volume production of 28 nm semiconductors has already been started. Socionext is working with Taiwan Semiconductor Manufacturing Company Limited (TSMC) for the manufacturing of 40 nm process and further. By the synergetic effect of the world's best manufacturing capability of TSMC and the quality control system and design engineering ability of Socionext, we will continue to lead the LSI industry in design and manufacture of cutting-edge custom SoCs of 28 nm process and beyond.

Product LineupFor the most-advanced technologies from 28 nm to 0.18 µm, information on the ASIC products best suited for the customer’s products are provided.

Advanced Process Technologies Advanced Front and Back Ends Technologies

1M 10M 100MGate count

CS101

Standard cell

10KGate count

100K 1M 10M 100M

Embedded array/Gate array

1G

CS201150K～400K

＊

0.18µm

90nm

65nm

CS302 40nm

CG88

＊：custom frame

CE88

CS401/CS402/CS405 28nm

CS25155nm

Standard cellThe Standard cells, by optimizing chip sizes, realize LSIs with higher integration and performance than macro-embedded cell arrays.

Embedded arrayOn the gate arrays, macros whose sizes are optimized at the transistor level can be implemented, realizing high-performance LSIs. A wide range of frames can be offered to the customers.

Gate arrayChips where transistors (basic cells) are regularly placed are prepared. In them, only routing is provided. Thus, Gate arrays feature shorter development time.

2013 2014 2015 20172016Volume production start timing

Gat

e le

ngth

(nm

)

16nm / 14nm (Schedule)

20nm

28nm

40nm

55nm

65nm

90nm

0.18µm

～

Technology Roadmap

Design fl owBased on the following design fl ow, we apply a optimized fl ow for the characteristics of the LSI being developed.

As the LSI becomes more refi ned, the number of gates that can be mounted is increasing. In the custom SoC development, the demand to design a chip with more than 100-million gates is increasing.

It is also becoming important to fulfi ll the demands of more complicated designs such as reduction of consumption power. In this situation, Socionext supports and materializes custom SoC development with advanced front and back ends techniques

for each technology for the customers.

System specification design

System level design

Logic synthesis

Equivalence verificationTiming restriction verification

Static timing verificationTemporary wiring simulation

Handoff verification

System level design

Front-end design

Backend design

Signoff verification

Design planning

Functional verification

Physical verificationLithographyverification

Dispersion considerationtiming analysis

Crosstalk noise analysisPower source network analysis

Test pattern generation

Gate simulation

Powerconsumption

analysis

Logicdesign

Specification

Logicsynthesis

Physicaldesign

Signoff

DFT

LSI design flow (outline)

Test circuit insertion

Layout assignment/wiringSignoff verification

RTL design(high-order synthesis)