ALUResult

PC

WriteData

MemData

Instruction

InstructionMemory

DataMemory

I/O Unit

Datapath

Register File

FSM Control

A

WD

A

D

D

Input Port

Output Port

Tmr2Tmr1

RC

SPRG1RG0

This is a project planned to illustrate the structure and operational foundations of Central Processing Units, through the implementation of a configurable system with two processors, one RISC (Reduced Instruction Set Computing) and one CISC(Complex Instruction Set Computing), described in Verilog for FPGA (Field Programmable Gate Array), along with a programming and monitoring user interface software.

ISCKER

Reconfigurable Platform for the Emulation of RISC and CISC Architectures

Reduced/Complex Instruction Set ComputingKey Educational Resource

ISCKER

PROGRAMMER

ISCKEROBSERVER

Authors:A. Gualdrón and J. P. Pinilla

Director:A. Retamoso

Features RISCKER CISCKER# of Instructions 30 244# of Registers 64 4ALU 16 bits 16bitsMemory Architecture Harvard Von NeumannInstructions Size Fixed: 16-bits Variable: 8 to 24-bitsMUL & DIV Hardware units Iterative

Shift Operations

Addressing Modes Immediate,Direct, Indirect,Offset INH,REL,IMM,DIR,EXT,IX,IX+Addressable Memory 65536x32bits 65536x16bits 65536x16bits# of Branch Conditions 2 14Timers 2 x 16 bits 2 x 16 bits

Interruptions

Control Unit Type HCU MCUSimilar Architectures MIPS HC08 and HC11 Freescale

Logic, Arithmetic and RotationBarrel Shifts.

1 bit Logic, Arithmetic andRotation Shifts.

2 by Timer2 External

2 by Timer2 External

The X-ISCKER platform delivers the Verilog HDL description of two processors, an IDE software and the documentation that will allow new learners to familiarize with computer architecture foundations, and computer designers to come up with custom embedded processor solutions to their applications.

Platform Resources Used Available Percentage

CISCKERTotal LE 1,436

22,320

6%Combinational 1,388 6%

Registers 362 2%

RISCKERTotal LE 2,750 12%Combinational 2,428 11%

Registers 1,089 5%Total LE 2,173 10%Combinational 2,062 9%

Registros 832 4%Total LE 3,436 15%Combinational 3,140 14%

Registers 1,643 7%

CISCKERObserver

RISCKERObserver

Altera Cyclone IV: EP4CE22 Resources

http:/semilleroadt.upbbga.edu.co/xiscker

The source files for the X-ISCKER platform and related further development will be kept available at the ADT (Advanced Digital Technologies) students’ research group of the UPB website.

ALU Result

Mem ory

Datapath

A

WDD

CCR

I X

SP

ACCA ACCB

Tm r 2

I n p u t Po r t

Tm r 1

Ou t p u t Po r t

Opcode

ACCD

MM

PC

u- I nstruct ionDecoder

MAR

H I N Z V C

I/OUnit