cwru eecs 317 eecs 317 computer design lecture 6: state machines instructor: francis g. wolff...
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CWRU EECS 317
EECS 317 Computer DesignEECS 317 Computer Design
LECTURE 6: State machines
LECTURE 6: State machines
Instructor: Francis G. [email protected] Western Reserve University This presentation uses powerpoint animation: please viewshow
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CWRU EECS 317
Gated-Clock SR Flip-Flop (Latch Enable)
S
R
Q
Q
LE
Q <= (S NAND LE) NAND NQ;
Asynchronous terminology: Preset and Clear
Synchronous terminology: Set and Reset
NQ <= (R NAND LE) NAND Q;
CLR
PS
Suppose each gate was 5ns: how long does the clockhave to be enabled to latch the data?
Answer: 15ns
Latches require that during the gated-clock the data must also be stable (i.e. S and R) at the same time
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CWRU EECS 317
Structural SR Flip-Flop (Latch)
NANDR S Qn+1
0 0 U0 1 11 0 01 1 Qn
R
S
Q
Q
ENTITY Latch ISPORT(R, S: IN std_logic; Q, NQ: OUT std_logic);
END ENTITY;
ARCHITECTURE latch_arch OF Latch ISBEGIN
Q <= R NAND NQ;NQ <= S NAND Q;
END ARCHITECTURE;
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CWRU EECS 317
Inferring Behavioral Latches: Asynchronous
ARCHITECTURE Latch2_arch OF Latch ISBEGIN
PROCESS (R, S) BEGINIF R= ‘0’ THEN
Q <= ‘1’; NQ<=‘0’;ELSIF S=‘0’ THEN
Q <= ‘0’; NQ<=‘1’;END IF;
END PROCESS;END ARCHITECTURE;
NANDR S Qn+1
0 0 U0 1 11 0 01 1 Qn
R
S
Q
Q
Sensitivity list of signals:Every time a change of state or event occurs on these signals this process will be called
Sensitivity list of signals:Every time a change of state or event occurs on these signals this process will be called
SequentialStatements
SequentialStatements
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CWRU EECS 317
Gated-Clock SR Flip-Flop (Latch Enable)
S
R
Q
Q
LE
ARCHITECTURE Latch_arch OF GC_Latch IS BEGINPROCESS (R, S, LE) BEGIN
IF LE=‘1’ THENIF R= ‘0’ THEN
Q <= ‘1’; NQ<=‘0’;ELSIF S=‘0’ THEN
Q <= ‘0’; NQ<=‘1’;END IF;
END IF;END PROCESS;
END ARCHITECTURE;
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CWRU EECS 317
Rising-Edge Flip-flop
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CWRU EECS 317
Rising-Edge Flip-flop logic diagram
Do not want to code this up as combin-atorial logic!
Too much work!
Do not want to code this up as combin-atorial logic!
Too much work!
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CWRU EECS 317
Inferring D-Flip Flops: Synchronous
ARCHITECTURE Dff_arch OF Dff ISBEGIN
PROCESS (Clock) BEGINIF Clock’EVENT AND Clock=‘1’ THEN
Q <= D;END IF;
END PROCESS;END ARCHITECTURE;
Sensitivity lists contain signals used in conditionals (i.e. IF)
Sensitivity lists contain signals used in conditionals (i.e. IF)
Notice the Process does not contain D:PROCESS(Clock, D)
Notice the Process does not contain D:PROCESS(Clock, D)
Clock’EVENT is what distinguishes a D-FlipFlip from a Latch
Clock’EVENT is what distinguishes a D-FlipFlip from a Latch
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CWRU EECS 317
Inferring D-Flip Flops: rising_edge
ARCHITECTURE Dff_arch OF Dff IS BEGINPROCESS (Clock) BEGIN
IF Clock’EVENT AND Clock=‘1’ THENQ <= D;
END IF;END PROCESS;
END ARCHITECTURE;
ARCHITECTURE dff_arch OF dff IS BEGINPROCESS (Clock) BEGIN
IF rising_edge(Clock) THENQ <= D;
END IF;END PROCESS;
END ARCHITECTURE;
Alternate andmore readable way is to use the rising_edge function
Alternate andmore readable way is to use the rising_edge function
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CWRU EECS 317
Inferring D-Flip Flops: Asynchronous Reset
ARCHITECTURE dff_reset_arch OF dff_reset IS BEGIN
PROCESS (Clock, Reset) BEGIN
IF Reset= ‘1’ THEN -- Asynchronous ResetQ <= ‘0’
ELSIF rising_edge(Clock) THEN --Synchronous Q <= D;
END IF;END PROCESS;
END ARCHITECTURE;
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CWRU EECS 317
Inferring D-Flip Flops: Synchronous Reset
PROCESS (Clock, Reset) BEGINIF rising_edge(Clock) THEN
IF Reset=‘1’ THENQ <= ‘0’
ELSEQ <= D;
END IF;END IF;
END PROCESS;
PROCESS (Clock, Reset) BEGINIF rising_edge(Clock) THEN
IF Reset=‘1’ THENQ <= ‘0’
ELSEQ <= D;
END IF;END IF;
END PROCESS;
PROCESS (Clock, Reset) BEGINIF Reset=‘1’ THEN
Q <= ‘0’ELSIF rising_edge(Clock) THEN
Q <= D;END IF;
END PROCESS;
PROCESS (Clock, Reset) BEGINIF Reset=‘1’ THEN
Q <= ‘0’ELSIF rising_edge(Clock) THEN
Q <= D;END IF;
END PROCESS;
Synchronous Reset
Synchronous FF
Synchronous Reset
Synchronous FF
Asynchronous Reset
Synchronous FF
Asynchronous Reset
Synchronous FF
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CWRU EECS 317
D-Flip Flops: Asynchronous Reset & Preset
PROCESS (Clock, Reset, Preset) BEGINIF Reset=‘1’ THEN --highest priority
Q <= ‘0’;ELSIF Preset=‘1’ THEN
Q <= ‘0’;ELSIF rising_edge(Clock) THEN
Q <= D;END IF;
END PROCESS;
PROCESS (Clock, Reset, Preset) BEGINIF Reset=‘1’ THEN --highest priority
Q <= ‘0’;ELSIF Preset=‘1’ THEN
Q <= ‘0’;ELSIF rising_edge(Clock) THEN
Q <= D;END IF;
END PROCESS;
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CWRU EECS 317
VHDL clock behavioral component
ENTITY clock_driver IS
GENERIC (Speed: TIME := 5 ns);
PORT (Clk: OUT std_logic);END;
ENTITY clock_driver IS
GENERIC (Speed: TIME := 5 ns);
PORT (Clk: OUT std_logic);END;
ARCHITECTURE clock_driver_arch OF clock_driver IS
SIGNAL Clock: std_logic := ‘0’;
BEGIN
Clk <= Clk XOR ‘1’ after Speed;
Clock <= Clk;
END ARCHITECTURE;
CONFIGURATION clock_driver_cfg OF clock_driver ISFOR clock_driver_arch END FOR;
END CONFIGURATION;
ARCHITECTURE clock_driver_arch OF clock_driver IS
SIGNAL Clock: std_logic := ‘0’;
BEGIN
Clk <= Clk XOR ‘1’ after Speed;
Clock <= Clk;
END ARCHITECTURE;
CONFIGURATION clock_driver_cfg OF clock_driver ISFOR clock_driver_arch END FOR;
END CONFIGURATION;
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CWRU EECS 317
Synchronous Sequential Circuit
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CWRU EECS 317
Abstraction: Finite State Machine
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CWRU EECS 317
FSM Representations
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CWRU EECS 317
Moore Machines
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CWRU EECS 317
Simple Design Example
ENTITY FSM_Parity ISPORT (i1: IN std_logic;
o1: OUT std_logic; CLK: IN std_logic; --Clock RST: IN std_logic --Reset
); END;
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CWRU EECS 317
State Encoding– –State Encoding is sequentially done by VHDL TYPE FSMStates IS (s1, s2); --s1=0, s2=1
SIGNAL State, NextState: FSMStates;
– –The non-sequential case requires the following ATTRIBUTE FSMencode: string; ATTRIBUTE FSMencode of FSMStates: TYPE IS “1 0”;
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CWRU EECS 317
Simple Design Example
PROCESS (State, i1) BEGIN CASE State IS
WHEN s1 =>if i1=‘1’ then NextState <= s2; else NextState <= s1; end if;
WHEN s2 =>if i1=‘1’ then NextState <= s1; else NextState <= s2; end if;
WHEN OTHERS => NextState <= NextState; END CASE; END PROCESS;
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CWRU EECS 317
FSM Controller: Current State Process
ARCHITECTURE FSM_Parity_arch OF FSM_Parity IS TYPE FSMStates IS (s1, s2); SIGNAL State, NextState: FSMStates;BEGIN
PROCESS (State, i1) BEGIN CASE State IS
WHEN s1 => if i1=‘1’ then NextState <= s2; else NextState <= s1; end if;
WHEN s2 => if i1=‘1’ then NextState <= s1; else NextState <= s2; end if;
WHEN OTHERS => NextState <= NextState; END CASE; END PROCESS;
WITH State SELECTo1 <= ‘0’ WHEN s1,
‘1’ WHEN s2,‘1’ WHEN OTHERS; - - X, L, W, H, U
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CWRU EECS 317
Alternative: less coding
ARCHITECTURE FSM_Parity_arch OF FSM_Parity IS TYPE FSMStates IS (s1, s2); SIGNAL State, NextState: FSMStates;BEGIN
PROCESS (State, i1) BEGIN CASE State IS
WHEN s1 => if i1=‘1’ then NextState <= s2; else NextState <= s1;
end if;o1 <= ‘0’;
WHEN s2 => if i1=‘1’ then NextState <= s1; else NextState <= s2;
end if; o1 <= ‘1’;
WHEN OTHERS => o1 <= ‘1’; NextState <= NextState;
END CASE; END PROCESS;
Important Note: every input to the state machine must be in the PROCESS sensitivity list
Important Note: every WHEN must assign the same set of signals: i.e. NextState and o1. if you miss one assignment latches will show up!
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CWRU EECS 317
FSM controller: NextState Process
PROCESS (CLK, RST) BEGIN IF RST='1' THEN -- Asynchronous Reset State <= s1;
ELSIF rising_edge(CLK) THEN State <= NextState; END IF; END PROCESS;
END ARCHITECTURE;
CONFIGURATION FSM_Parity_cfg OF FSM_Parity ISFOR FSM_Parity_archEND FOR;
END CONFIGURATION;
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CWRU EECS 317
Logic ImplementationsSynthesis
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CWRU EECS 317
Coke Machine Example
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CWRU EECS 317
Coke Machine State Diagram
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CWRU EECS 317
Coke Machine Diagram II
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CWRU EECS 317
Assignment #6
a) Write the VHDL synchronous code (no latches!) and test bench for the coke II machine. Note: the dc_shell synthesis analyze command will tell you if you inferred latches. Hand code and simulation using the Unix script command.
b) Synthesize the your design and hand in the logic diagram, Unix script include cell, area, timing report.