datasheet 74595
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Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 8
1 Publication Order Number:
MC74HC595A/D
M C 7 4 H C 5 9 5 A
8 - B i t S e r i a l - I n p u t / S e r i a l o r
P a r a l l e l - O u t p u t S h i f t
R e g i s t e r w i t h L a t c h e d
3 - S t a t e O u t p u t s
HighPerformance SiliconGate CMOSThe MC74HC595A consists of an 8bit shift register and an 8bit
Dtype latch with threestate parallel outputs. The shift registeraccepts serial data and provides a serial output. The shift register alsoprovides parallel data to the 8bit latch. The shift register and latchhave independent clock inputs. This device also has an asynchronousreset for the shift register.
The HC595A directly interfaces with the SPI serial data port onCMOS MPUs and MCUs.
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595
Improved Propagation Delays 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity
LOGIC DIAGRAMSERIALDATAINPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCHCLOCK
OUTPUTENABLE
SHIFTREGISTER LATCH
15
1
2
3
4
5
6
7
9
QAQBQCQDQEQFQGQH
SQH
A
VCC= PIN 16GND = PIN 8
PARALLELDATA
OUTPUTS
SERIALDATA
OUTPUT
SO16D SUFFIX
CASE 751B
http://onsemi.com
TSSOP16DT SUFFIXCASE 948F
1
16
PDIP16N SUFFIXCASE 648
116
1
16
MARKINGDIAGRAMS
1
16
MC74HC595ANAWLYYWW
1
16
HC595A
AWLYWW
A = Assembly LocationWL = Wafer LotYY = YearWW = Work Week
HC595AALYW
1
16
Device Package Shipping
ORDERING INFORMATION
MC74HC595AN PDIP16 2000 / Box
MC74HC595AD SOIC16 48 / Rail
MC74HC595ADR2 SOIC16 2500 / Reel
MC74HC595ADT TSSOP16 96 / Rail
MC74HC595ADTR2 TSSOP16 2500 / Reel
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
QA
VCC
SQH
RESET
SHIFT CLOCK
QE
QD
QC
QB
GND
QH
QG
QF
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MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to V CC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to V CC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
35
mA
ICC
DC Supply Current, V CC and GND Pins
75
mA
P D
Power Dissipation in Still Air, Plastic DIPSOIC Package
TSSOP Package
750500450
mW
Tstg
Storage Temperature
65 to + 150
_ C
TL
Lead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP, SOIC or TSSOP Package)
260
_ C
*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/ _ C from 65 _ to 125 _ CSOIC Package: 7 mW/ _ C from 65 _ to 125 _ CTSSOP Package: 6.1 mW/ _ C from 65 _ to 125 _ C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage(Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_ C
tr, tf
Input Rise and Fall Time V CC = 2.0 V(Figure 1) V CC = 4.5 V
VCC = 6.0 V
000
1000500400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCCV
55 to25 _ C
v 85 _ C
v 125 _ C
Unit
VIH
Minimum HighLevel InputVoltage
Vout = 0.1 V or V CC 0.1 V|Iout | v 20 A
2.03.04.56.0
1.52.1
3.154.2
1.52.1
3.154.2
1.52.1
3.154.2
V
VIL
Maximum LowLevel InputVoltage
Vout = 0.1 V or V CC 0.1 V|Iout | v 20 A
2.03.04.56.0
0.50.9
1.351.8
0.50.9
1.351.8
0.50.9
1.351.8
V
VOH
Minimum HighLevel OutputVoltage, Q A Q H
Vin = VIH or VIL|Iout | v 20 A
2.04.56.0
1.94.45.9
1.94.45.9
1.94.45.9
V
Vin = VIH or VIL |Iout | v 2.4 mA|Iout | v 6.0 mA|Iout | v 7.8 mA
3.04.56.0
2.483.985.48
2.343.845.34
2.23.75.2
VOL
Maximum LowLevel OutputVoltage, Q A Q H
Vin = VIH or VIL|Iout | v 20 A
2.04.56.0
0.10.10.1
0.10.10.1
0.10.10.1
V
Vin = VIH or VIL |Iout | v 2.4 mA|Iout | v 6.0 mA|Iout | v 7.8 mA
3.04.56.0
0.260.260.26
0.330.330.33
0.40.40.4
This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this highimpedance cir-cuit. For proper operation, V in andVout should be constrained to therange GND v (Vin or Vout ) v VCC .
Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or V CC ).Unused outputs must be left open.
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
VCCV
Test Conditions
Parameter
Symbol
Unit
v 125 _ C
v 85 _ C
55 to25 _ C
VCCV
Test Conditions
Parameter
Symbol
VOH
Minimum HighLevel OutputVoltage, SQ H
Vin = VIH or VILIIout I v 20 A
2.04.56.0
1.94.45.9
1.94.45.9
1.94.45.9
V
Vin = VIH or VIL |Iout | v 2.4 mAIIout I v 4.0 mAIIout Iv 5.2 mA
3.04.56.0
2.983.985.48
2.343.845.34
2.23.75.2
VOL
Maximum LowLevel OutputVoltage, SQ H
Vin = VIH or VILIIout I v 20 A
2.04.56.0
0.10.10.1
0.10.10.1
0.10.10.1
V
Vin = VIH or VIL |Iout | v 2.4 mAIIout I v 4.0 mAIIout Iv 5.2 mA
3.04.56.0
0.260.260.26
0.330.330.33
0.40.40.4
Iin
Maximum Input LeakageCurrent
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
IOZ
Maximum ThreeStateLeakageCurrent, Q A Q H
Output in HighImpedance StateVin = VIL or VIHVout = VCC or GND
6.0
0.5
5.0
10
A
ICC
Maximum Quiescent SupplyCurrent (per Package)
Vin = VCC or GNDlout = 0 A
6.0
4.0
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book(DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t r = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCCV
55 to25 _ C
v 85 _ C
v 125 _ C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)(Figures 1 and 7)
2.03.04.56.0
6.0153035
4.8102428
4.08.02024
MHz
tPLH,tPHL
Maximum Propagation Delay, Shift Clock to SQ H(Figures 1 and 7)
2.03.04.56.0
1401002824
1751253530
2101504236
ns
tPHL
Maximum Propagation Delay, Reset to SQ H(Figures 2 and 7)
2.03.04.56.0
1451002925
1801253631
2201504438
ns
tPLH,tPHL
Maximum Propagation Delay, Latch Clock to Q A Q H(Figures 3 and 7)
2.03.04.56.0
1401002824
1751253530
2101504236
ns
tPLZ,tPHZ
Maximum Propagation Delay, Output Enable to Q A Q H(Figures 4 and 8)
2.03.04.5
6.0
15010030
26
19012538
33
22515045
38
ns
tPZL,tPZH
Maximum Propagation Delay, Output Enable to Q A Q H(Figures 4 and 8)
2.03.04.56.0
135902723
1701103429
2051304135
ns
tTLH,tTHL
Maximum Output Transition Time, Q A Q H(Figures 3 and 7)
2.03.04.56.0
60231210
75271513
90311815
ns
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input t r = tf = 6.0 ns)
Unit
Guaranteed Limit
VCCV
Parameter
Symbol
Unit
v 125 _ C
v 85 _ C
55 to25 _ C
VCCV
Parameter
Symbol
tTLH,tTHL
Maximum Output Transition Time, SQ H(Figures 1 and 7)
2.03.04.56.0
75271513
95321916
110362219
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum ThreeState Output Capacitance (Output inHighImpedance State), Q A Q H
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ONSemiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25 C, V CC = 5.0 V
CPD Power Dissipation Capacitance (Per Package)* 300 pF
* Used to determine the noload dynamic power consumption: P D = CPD VCC 2f + ICC VCC . For load considerations, see Chapter 2 of theON Semiconductor HighSpeed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input t r = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
VCCV
25 _ C to 55 _ C
v 85 _ C
v 125 _ C
Unit
tsu
Minimum Setup Time, Serial Data Input A to Shift Clock(Figure 5)
2.03.04.56.0
5040109.0
65501311
75601513
ns
tsu
Minimum Setup Time, Shift Clock to Latch Clock(Figure 6)
2.03.04.56.0
75601513
95701916
110802219
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A(Figure 5)
2.03.04.56.0
5.05.05.05.0
5.05.05.05.0
5.05.05.05.0
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock(Figure 2)
2.03.04.56.0
5040109.0
65501311
75601513
ns
tw
Minimum Pulse Width, Reset(Figure 2)
2.03.04.56.0
60451210
75601513
90701815
ns
tw
Minimum Pulse Width, Shift Clock(Figure 1)
2.03.04.56.0
5040109.0
65501311
75601513
ns
tw
Minimum Pulse Width, Latch Clock
(Figure 6)
2.0
3.04.56.0
50
40109.0
65
501311
75
601513
ns
tr, tf
Maximum Input Rise and Fall Times(Figure 1)
2.03.04.56.0
1000800500400
1000800500400
1000800500400
ns
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FUNCTION TABLEInputs Resulting Function
Operation Reset
SerialInput
AShiftClock
LatchClock
OutputEnable
ShiftRegisterContents
LatchRegisterContents
SerialOutput
SQ H
ParallelOutputsQA Q H
Reset shift register L X X L, H, L L U L U
Shift data into shiftregister
H D L, H, L D SR A;SR N SR N+1
U SR G SR H U
Shift register remainsunchanged
H X L, H, L, H, L U U U U
Transfer shift registercontents to latchregister
H X L, H, L U SR N LRN U SR N
Latch register remainsunchanged
X X X L, H, L * U * U
Enable parallel outputs X X X X L * ** * Enabled
Force outputs into highimpedance state
X X X X H * ** * Z
SR = shift register contents D = data (L, H) logic level = LowtoHigh * = depends on Reset and Shift Clock inputsLR = latch register contents U = remains unchanged = HightoLow ** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTSA (Pin 14)
Serial Data Input. The data on this pin is shifted into the8bit serial shift register.
CONTROL INPUTSShift Clock (Pin 11)
Shift Register Clock Input. A low tohigh transition onthis input causes the data at the Serial Input pin to be shiftedinto the 8bit shift register.
Reset (Pin 10)
Activelow, Asynchronous, Shift Register Reset Input. Alow on this pin resets the shift register portion of this deviceonly. The 8bit latch is not affected.
Latch Clock (Pin 12)
Storage Latch Clock Input. A lowtohigh transition onthis input latches the shift register data.
Output Enable (Pin 13)
Activelow Output Enable. A low on this input allows thedata from the latches to be presented at the outputs. A highon this input forces the outputs (Q AQH) into thehighimpedance state. The serial output is not affected bythis control unit.
OUTPUTSQA Q H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Noninverted, 3state, latch outputs.
SQ H (Pin 9)
Noninverted, Serial Data Output. This is the output of theeighth stage of the 8bit shift register. This output does nothave threestate capability.
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SWITCHING WAVEFORMS
SERIALINPUT A 50%
50%SWITCHCLOCK
VCC
GND
VALID
tsu th
Figure 5.
SHIFTCLOCK
OUTPUTSQH
tr tfVCC
GND
90%50%
10%
90%50%
10%
tPLH tPHL
tTLH tTHL
tw
1/fmax
RESET
OUTPUTSQH
SHIFTCLOCK
tw
50%
50%
50%
VCC
GND
VCC
GND
tPHL
trec
tsu
50%
50%
VCC
GND
LATCHCLOCK
QA QHOUTPUTS
50%
tPLH tPHL
tTLH tTHL
90%50%10%
VCC
GND
VCC
GND
SHIFTCLOCK
LATCHCLOCK
Figure 3.
VCC
GNDtw
Figure 1. Figure 2.
Figure 4.
Figure 6.
OUTPUT Q
OUTPUT Q
50%
50%
90%
10%
tPZL tPLZ
tPZH tPHZ
VCC
GND
HIGHIMPEDANCE
VOL
VOHHIGHIMPEDANCE
OUTPUTENABLE
50%
TEST CIRCUITS
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICEUNDER
TEST
OUTPUT
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICEUNDER
TEST
OUTPUTCONNECT TO VCCWHENTESTING tPLZAND tPZL.CONNECT TO GND WHENTESTING tPHZAND tPZH.
1 k
Figure 7. Figure 8.
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D
R
Q
SRA
D Q
LRA
D Q
SRB
D Q
LRB
R
D Q
SRC
D Q
LRC
R
D Q
SRD
D Q
LRD
R
D Q
SRE
D Q
LRE
R
D Q
SRF
D Q
LRFR
D Q
SRG
D Q
LRG
R
D Q
SRH
D Q
LRH
R
EXPANDED LOGIC DIAGRAM
OUTPUTENABLE
LATCHCLOCK
SERIALDATA
INPUT A
SHIFTCLOCK
RESET
13
12
14
11
10
15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL
DATAOUTPUT SQH
PARALLELDATA
OUTPUTS
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TIMING DIAGRAM
SHIFTCLOCK
SERIAL DATAINPUT A
RESETLATCHCLOCK
OUTPUTENABLE
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL DATAOUTPUT SQH
NOTE: implies tha t the output i s in a h ighimpedancestate.
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PACKAGE DIMENSIONS
PDIP16N SUFFIX
CASE 64808ISSUE R
MIN MINMAX MAXINCHES MILLIMETERS
DIMABCDFGHJKLMS
18.806.353.690.391.02
0.212.807.50
00.51
19.556.854.440.531.77
0.383.307.74101.01
0.7400.2500.1450.0150.040
0.0080.1100.295
00.020
0.7700.2700.1750.0210.070
0.0150.1300.305
100.040
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.5. ROUNDED CORNERS OPTIONAL.
2.54 BSC1.27 BSC
0.100 BSC0.050 BSC
A
B1 8
916
F
HG
D 16 PL
S
C
T
SEATINGPLANE
K JM
L
T A0.25 (0.010) M M
0.25 (0.010) T B AM S S
MIN MINMAX MAX
MILLIMETERS INCHES
DIMABCDFGJKMPR
9.803.801.350.350.40
0.190.10
05.800.25
10.004.001.750.491.25
0.250.25
7 6.200.50
0.3860.1500.0540.0140.016
0.0080.004
0 0.2290.010
0.3930.1570.0680.0190.049
0.0090.009
7 0.2440.019
1.27 BSC 0.050 BSC
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
1 8
916
A
B
D 16PL
K
C
G
T SEATING
PLANE
R X 45
M J
F
P 8 PL0.25 (0.010) BM M
SOIC16D SUFFIX
CASE 751B05ISSUE J
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PACKAGE DIMENSIONS
TSSOP16DT SUFFIX
CASE 948F01ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 4.90 5.10 0.193 0.200B 4.30 4.50 0.169 0.177C 1.20 0.047D 0.05 0.15 0.002 0.006F 0.50 0.75 0.020 0.030G 0.65 BSC 0.026 BSCH 0.18 0.28 0.007 0.011J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010L 6.40 BSC 0.252 BSCM 0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.PROTRUSIONS OR GATE BURRS. MOLD FLASH ORGATE BURRS SHALL NOT EXCEED 0.15 (0.006) PERSIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR PROTRUSIONSHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE KDIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED ATDATUM PLANE W.
_ _ _ _
SECTION NN
SEATINGPLANE
IDENT.PIN 1
1 8
16 9
DETAIL E
J
J1
B
C
D
A
KK1
HG
DETAIL E
F
M
L
2X L/2
U
SU0.15 (0.006) T
SU0.15 (0.006) T
SUM0.10 (0.004) V ST
0.10 (0.004) T
V
W
0.25 (0.010)
16X REFK
N
N
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Notes
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