datasheet - stl47n60m6 - n-channel 600 v, 70 mΩ typ., 31 a

15
5 1 2 3 4 PowerFLAT™ 8x8 HV NG1DS2PS34D5Z Drain(5) Gate(1) Driver source (2) Power source (3, 4) Features Order code V DS R DS(on) max. I D STL47N60M6 600 V 82 mΩ 31 A Reduced switching losses Lower R DS(on) x area vs previous generation Low gate input resistance 100% avalanche tested Zener-protected Excellent switching performance thanks to the extra driving source pin Applications Switching applications Description The new MDmesh™ M6 technology incorporates the most recent advancements to the well-known and consolidated MDmesh family of SJ MOSFETs. STMicroelectronics builds on the previous generation of MDmesh devices through its new M6 technology, which combines excellent R DS(on) per area improvement with one of the most effective switching behaviors available, as well as a user-friendly experience for maximum end-application efficiency. Product status link STL47N60M6 Product summary Order code STL47N60M6 Marking 47N60M6 Package PowerFLAT™ 8x8 HV Packing Tape and reel N-channel 600 V, 70 mΩ typ., 31 A MDmesh™ M6 Power MOSFET in a PowerFLAT™ 8x8 HV package STL47N60M6 Datasheet DS12382 - Rev 2 - January 2019 For further information contact your local STMicroelectronics sales office. www.st.com

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5

123

4

PowerFLAT™ 8x8 HV

NG1DS2PS34D5Z

Drain(5)

Gate(1)

Driversource (2)

Powersource (3, 4)

FeaturesOrder code VDS RDS(on) max. ID

STL47N60M6 600 V 82 mΩ 31 A

• Reduced switching losses• Lower RDS(on) x area vs previous generation• Low gate input resistance• 100% avalanche tested• Zener-protected• Excellent switching performance thanks to the extra driving source pin

Applications• Switching applications

DescriptionThe new MDmesh™ M6 technology incorporates the most recent advancements tothe well-known and consolidated MDmesh family of SJ MOSFETs.STMicroelectronics builds on the previous generation of MDmesh devices through itsnew M6 technology, which combines excellent RDS(on) per area improvement withone of the most effective switching behaviors available, as well as a user-friendlyexperience for maximum end-application efficiency.

Product status link

STL47N60M6

Product summary

Order code STL47N60M6

Marking 47N60M6

Package PowerFLAT™ 8x8 HV

Packing Tape and reel

N-channel 600 V, 70 mΩ typ., 31 A MDmesh™ M6 Power MOSFET in a PowerFLAT™ 8x8 HV package

STL47N60M6

Datasheet

DS12382 - Rev 2 - January 2019For further information contact your local STMicroelectronics sales office.

www.st.com

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ±25 V

ID Drain current (continuous) at TC = 25 °C 31 A

ID Drain current (continuous) at TC= 100 °C 20 A

IDM (1) Drain current (pulsed) 124 A

PTOT Total power dissipation at TC = 25 °C 190 W

dv/dt(2) Peak diode recovery voltage slope 15 V/ns

dv/dt(3) MOSFET dv/dt ruggedness 100 V/ns

Tstg Storage temperature range-55 to 150 °C

Tj Operating junction temperature range

1. Pulse width is limited by safe operating area.2. ISD ≤ 31 A, di/dt ≤ 400 A/µs, VDS(peak) < V(BR)DSS, VDD = 400 V

3. VDS ≤ 480 V

Table 2. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 0.66 °C/W

Rthj-pcb (1) Thermal resistance junction-pcb 50 °C/W

1. When mounted on 1 inch2 FR-4, 2 Oz copper board

Table 3. Avalanche characteristics

Symbol Parameter Value Unit

IARAvalanche current, repetitive or not repetitive

(pulse width limited by Tjmax)5.3 A

EASSingle pulse avalanche energy

(starting Tj = 25 °C, ID = IAR, VDD = 50 V)800 mJ

STL47N60M6Electrical ratings

DS12382 - Rev 2 page 2/15

2 Electrical characteristics

(TC= 25 °C unless otherwise specified)

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSSDrain-source breakdownvoltage VGS = 0 V, ID = 1 mA 600 V

IDSS Zero gate voltage drain currentVGS = 0 V, VDS = 600 V 1 µA

VGS = 0 V, VDS = 600 V, TC = 125 °C(1) 100 µA

IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA

VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3.25 4 4.75 V

RDS(on)Static drain-source

on-resistanceVGS = 10 V, ID = 15.5 A 70 82 mΩ

1. Defined by design, not subject to production test.

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance

VDS= 100 V, f = 1 MHz, VGS = 0 V

- 2340 - pF

Coss Output capacitance - 149 - pF

Crss Reverse transfer capacitance - 3.7 - pF

Coss eq.(1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 390 - pF

RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 1.4 - Ω

Qg Total gate charge VDD = 480 V, ID = 36 A, VGS = 0 to 10 V

(see Figure 14. Test circuit for gatecharge behavior)

- 52.2 - nC

Qgs Gate-source charge - 16.5 - nC

Qgd Gate-drain charge - 23 - nC

1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0to 80% VDSS

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 300 V, ID = 18 A,

RG = 4.7 Ω, VGS = 10 V

(see Figure 13. Switching times testcircuit for resistive load andFigure 18. Switching time waveform)

- 21.5 - ns

tr Rise time - 18.7 - ns

td(off) Turn-off delay time - 54.6 - ns

tf Fall time - 8.1 - ns

STL47N60M6Electrical characteristics

DS12382 - Rev 2 page 3/15

Table 7. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD (1) Source-drain current - 31 A

ISDM , (2) (1) Source-drain current (pulsed) - 124 A

VSD (3) Forward on voltage VGS = 0 V, ISD = 31 A - 1.6 V

trr Reverse recovery timeISD = 36 A, di/dt = 100 A/µs, VDD = 60 V(see Figure 15. Test circuit for inductiveload switching and diode recovery times)

- 281 ns

Qrr Reverse recovery charge - 3.67 µC

IRRM Reverse recovery current - 26.1 A

trr Reverse recovery time ISD = 36 A, di/dt = 100 A/µs, VDD = 60 V,Tj = 150 °C (see Figure 15. Test circuitfor inductive load switching and dioderecovery times)

- 424 ns

Qrr Reverse recovery charge - 7.2 µC

IRRM Reverse recovery current - 34 A

1. This value is limited by package.2. Pulse width is limited by safe operating area.3. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.

STL47N60M6Electrical characteristics

DS12382 - Rev 2 page 4/15

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area

GIPG080120191350SOA

10 2

10 1

10 0

10 -1

10 -1 10 0 10 1 10 2

ID (A)

VDS (V)

tp =1 µs

tp =10 µs

tp =100 µs

tp =1 ms

tp =10 mssingle pulse

TJ≤150 °CTC=25 °CVGS=10 V

Operation in this areais limited by R DS(on)

Figure 2. Thermal impedance

10 -1

10 -2

10 -3

10 -6 10 -5 10 -4 10 -3 10 -2

K

tp (s)

δ = 0.5

δ = 0.2δ = 0.1

δ = 0.05

δ = 0.02δ = 0.01

Single pulse

Zth PowerFLAT 8x8 HV

Figure 3. Output characteristics

GIPG101220181057OCH

120

100

80

60

40

20

00 2 4 6 8 10 12 14 16

ID (A)

VDS (V)

VGS =7 V

VGS =8 V

VGS =7, 8, 9, 10 V

VGS =6 V

VGS =9 VVGS =10 V

Figure 4. Transfer characteristics

GIPG101220181058TCH

120

100

80

60

40

20

04 5 6 7 8 9

ID (A)

VGS (V)

VDS =16 V

Figure 5. Gate charge vs gate-source voltage

GIPG101220181058QVG

600

500

400

300

200

100

0

12

10

8

6

4

2

00 10 20 30 40 50 60

VDS (V)

VGS (V)

Qg (nC)

VDD = 480 V,

Qgs

ID = 36 A

Qg

VDS

Qgd

Figure 6. Static drain-source on-resistance

GIPG090120191039RID

76

74

72

70

68

660 5 10 15 20 25 30

RDS(on) (mΩ)

ID (A)

VGS =10 V

STL47N60M6Electrical characteristics (curves)

DS12382 - Rev 2 page 5/15

Figure 7. Capacitance variations

GIPG101220181057CVR

10 4

10 3

10 2

10 1

10 0

10 -1 10 0 10 1 10 2

C (pF)

VDS (V)

f = 1 MHz

Figure 8. Normalized gate threshold voltage vstemperature

GIPG101220181029VTH

1.1

1.0

0.9

0.8

0.7

0.6-75 -25 25 75 125

VGS(th) (norm.)

TJ (°C)

ID = 250 μA

Figure 9. Normalized on-resistance vs temperature

GIPG101220181029RON

2.2

1.8

1.4

1.0

0.6

0.2-75 -25 25 75 125

RDS(on) (norm.)

VGS = 10 V

TJ (°C)

Figure 10. Normalized V(BR)DSS vs temperature

GIPG101220181055BDV

1.08

1.04

1.00

0.96

0.92

0.88-75 -25 25 75 125

V(BR)DSS (norm.)

ID = 1 mA

TJ (°C)

Figure 11. Output capacitance stored energy

ADG181220181310EOS

20

16

12

8

4

00 100 200 300 400 500 600

EOSS (µJ)

VDS (V)

Figure 12. Source-drain diode forward characteristics

GIPG080120191351SDF

1.1

1.0

0.9

0.8

0.7

0.6

0.50 5 10 15 20 25 30

VSD (V)

ISD (A)

Tj = -50 °C

Tj = 25 °C

Tj = 150 °C

STL47N60M6Electrical characteristics (curves)

DS12382 - Rev 2 page 6/15

3 Test circuits

Figure 13. Switching times test circuit for resistive load

AM15855v1

VGS

PW

VD

RG

RL

D.U.T.

2200µF

3.3µF VDD

GND2 (power)

GND1 (driver signal)

+

Figure 14. Test circuit for gate charge behavior

GADG180720181011SA

RL

47 kΩ

2.7 kΩ

1 kΩ

IG= CONST100 Ω

D.U.T.

+pulse width

VGS

2200μF

VG

VDD

GND1 GND2

Figure 15. Test circuit for inductive load switching anddiode recovery times

AM15857v1

AD

D.U.T.

SB

G

25Ω

A A

BB

RG

G

FASTDIODE

D

S

L=100µH

µF3.3 1000

µF VDD

GND1 GND2

D.U.T.

+

Figure 16. Unclamped inductive load test circuit

AM15858v1

Vi

Pw

VD

ID

D.U.T.

L

2200µF

3.3µF VDD

GND1 GND2

+

Figure 17. Unclamped inductive waveform

AM01472v1

V(BR)DSS

VDDVDD

VD

IDM

ID

Figure 18. Switching time waveform

AM01473v1

0

VGS 90%

VDS

90%

10%

90%

10%

10%

ton

td(on) tr

0

toff

td(off) tf

STL47N60M6Test circuits

DS12382 - Rev 2 page 7/15

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®

packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitionsand product status are available at: www.st.com. ECOPACK® is an ST trademark.

STL47N60M6Package information

DS12382 - Rev 2 page 8/15

4.1 PowerFLAT™ 8x8 HV package information

Figure 19. PowerFLAT™ 8x8 HV package outline

8222871_Rev_4

STL47N60M6PowerFLAT™ 8x8 HV package information

DS12382 - Rev 2 page 9/15

Table 8. PowerFLAT™ 8x8 HV mechanical data

Ref.Dimensions (in mm)

Min. Typ. Max.

A 0.75 0.85 0.95

A1 0.00 0.05

A3 0.10 0.20 0.30

b 0.90 1.00 1.10

D 7.90 8.00 8.10

E 7.90 8.00 8.10

D2 7.10 7.20 7.30

E1 2.65 2.75 2.85

E2 4.25 4.35 4.45

e 2.00 BSC

L 0.40 0.50 0.60

Figure 20. PowerFLAT™ 8x8 HV footprint

8222871_REV_4_footprint

Note: All dimensions are in millimeters.

STL47N60M6PowerFLAT™ 8x8 HV package information

DS12382 - Rev 2 page 10/15

4.2 PowerFLAT™ 8x8 HV packing information

Figure 21. PowerFLAT™ 8x8 HV tape

W (1

6.00

±0.3

)

E (1.75±0.1)

F (7

.50±

0.1)

A0 (8.30±0.1)P1 (12.00±0.1)

P2 (2.0±0.1) P0 (4.0±0.1)

D0 ( 1.55±0.05)

D1 ( 1.5 Min)

T (0.30±0.05)

B0 (8

.30±

0.1)

K0 (1.10±0.1)

Note: Base and Bulk qu antity 3000 pcs

8229819_Tape_revA

Note: All dimensions are in millimeters.

Figure 22. PowerFLAT™ 8x8 HV package orientation in carrier tape

STL47N60M6PowerFLAT™ 8x8 HV packing information

DS12382 - Rev 2 page 11/15

Figure 23. PowerFLAT™ 8x8 HV reel

8229819_Reel_revA

Note: All dimensions are in millimeters.

STL47N60M6PowerFLAT™ 8x8 HV packing information

DS12382 - Rev 2 page 12/15

Revision history

Table 9. Document revision history

Date Revision Changes

15-Nov-2017 1 First release

22-Jan-2019 2

Modified Table 1. Absolute maximum ratings, Table 2. Thermal data,Table 3. Avalanche characteristics, Table 4. On/off states, Table 5. Dynamic,Table 6. Switching times and Table 7. Source-drain diode.

Added Section 2.1 Electrical characteristics (curves).

Modified Section 3 Test circuits.

Minor text changes.

STL47N60M6

DS12382 - Rev 2 page 13/15

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1 PowerFLAT 8x8 HV package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 PowerFLAT™ 8x8 HV packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

STL47N60M6Contents

DS12382 - Rev 2 page 14/15

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2019 STMicroelectronics – All rights reserved

STL47N60M6

DS12382 - Rev 2 page 15/15