datasheets procesador ecu megane

HC05

MC68HC05B6/DRev. 4

MC68HC05B4MC68HC705B5MC68HC05B6MC68HC05B8MC68HC05B16MC68HC705B16MC68HC705B16NMC68HC05B32MC68HC705B32

TECHNICALDATA

MC68H

C05B6TECH

NICA

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TA

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123456789101112131415

INTRODUCTION

MODES OF OPERATION AND PIN DESCRIPTIONS

MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

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1234567891011121314

15

INTRODUCTION


MEMORY AND REGISTERS

INPUT/OUTPUT PORTS

PROGRAMMABLE TIMER

SERIAL COMMUNICATIONS INTERFACE

PULSE LENGTH D/A CONVERTERS

ANALOG TO DIGITAL CONVERTER

RESETS AND INTERRUPTS

CPU CORE AND INSTRUCTION SET

ELECTRICAL SPECIFICATIONS

MECHANICAL DATA

ORDERING INFORMATION

APPENDICES

HIGH SPEED OPERATION

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CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05B6/D rev. 4)

Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication youhave just received. Having used the document, please complete this card (or a photocopy of it, if you prefer). 1. How would you rate the quality of the document? Check one box in each category.

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SECTION 1 INSECTION 2 MSECTION 3 MSECTION 4 INSECTION 5 PSECTION 6 SSECTION 7 PSECTION 8 ASECTION 9 RSECTION 10 SECTION 11 SECTION 12 SECTION 13 SECTION 14 SECTION 15

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EMORY AND REGISTERSPUT/OUTPUT PORTS

ROGRAMMABLE TIMERERIAL COMMUNICATIONS INTERFACEULSE LENGTH D/A CONVERTERSNALOG TO DIGITAL CONVERTERESETS AND INTERRUPTSCPU CORE AND INSTRUCTION SETELECTRICAL SPECIFICATIONSMECHANICAL DATAORDERING INFORMATIONAPPENDICESHIGH SPEED OPERATION

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume anyliability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, includingwithout limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheetsand/or specifications can and do vary in different applications and actual performance may vary over time. All operatingparameters, including Typicals, must be validated for each customer application by customers technical experts. Motoroladoes not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, orauthorized for use as components in systems intended for surgical implant into the body, or other applications intended tosupport or sustain life, or for any other application in which the failure of the Motorola product could create a situation wherepersonal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributorsharmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges thatMotorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks ofMotorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

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All Trade Marks recognized. This document contains information on new products. Specifications and information herein aresubject to change without notice.

MC68HC05B6

High-density ComplementaryMetal Oxide Semiconductor

(HCMOS) Microcomputer Unit

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ConventionsWhere abbreviations are used in the text, an explanation can be found in theglossary, at the back of this manual. Register and bit mnemonics are defined in theparagraphs describing them.

An overbar is used to designate an active-low signal, eg: RESET.

Unless otherwise stated, shaded cells in a register diagram indicate that the bit iseither unused or reserved; u is used to indicate an undefined state (on reset).Unless otherwise stated, pins labelled NU should be tied to VSS in an electricallynoisy environment. Pins labelled NC can be left floating, since they are not bondedto any part of the device.

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MC68HC0Rev. 4

ParagraphNumber

TABLE OF CONTENTS

1.1 F1.2 M

2.1 M2.1.12.2 S2.3 J2.4 L2.4.12.4.22.4.2.12.4.32.4.3.12.5 2.5.12.5.22.5.32.5.42.5.52.5.62.5.72.5.82.5.8.12.5.8.22.5.8.32.5.9 RDI (Receive data in).................................................................................2132.5.10 TDO (Transmit data out) ............................................................................2132.5.11 SCLK..........................................................................................................2132.5.12

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TABLE OF CONTENTS

PLMA .........................................................................................................213

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1 INTRODUCTION

eatures.............................................................................................................12ask options for the MC68HC05B6 ..................................................................13

2 MODES OF OPERATION AND PIN DESCRIPTIONS

odes of operation ............................................................................................21Single chip mode .........................................................................................21

erial RAM loader .............................................................................................22ump to any address........................................................................................24ow power modes..............................................................................................26

STOP ...........................................................................................................26WAIT ............................................................................................................28

Power consumption during WAIT mode .................................................28SLOW mode.................................................................................................29

Miscellaneous register...........................................................................29Pin descriptions ..............................................................................................210

VDD and VSS ............................................................................................210IRQ ............................................................................................................210RESET .......................................................................................................210TCAP1 .......................................................................................................210TCAP2 .......................................................................................................211TCMP1.......................................................................................................211TCMP2.......................................................................................................211OSC1, OSC2 .............................................................................................211

Crystal ..................................................................................................211Ceramic resonator................................................................................211External clock .......................................................................................212 Go to: www.freescale.com 7

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PageNumberTABLE OF CONTENTS

2.5.13 PLMB .........................................................................................................2132.5.14 VPP1..........................................................................................................2132.5.15 VRH ...........................................................................................................2132.5.16 VRL............................................................................................................2132.5.17 PA0 PA7/PB0 PB7/PC0 PC7 ............................................................2132.5.18

3.1 R3.2 R3.3 R3.4 S3.5 E3.5.13.5.23.5.33.5.43.5.53.6 E3.7 E3.8

4.1 I4.2 P4.3 P4.4 P4.5 P4.5.14.5.24.5.34.5.3.14.5.44.6 O

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TABLE OF CONTENTS

PD0/AN0PD7/AN7...................................................................................213

3 MEMORY AND REGISTERS

egisters ...........................................................................................................31AM ..................................................................................................................31OM ..................................................................................................................31elf-check ROM ................................................................................................32EPROM...........................................................................................................33

EEPROM control register.............................................................................33EEPROM read operation .............................................................................35EEPROM erase operation ...........................................................................35EEPROM programming operation ...............................................................36Options register (OPTR) ..............................................................................36

EPROM during STOP mode ...........................................................................37EPROM during WAIT mode ............................................................................37

Miscellaneous register......................................................................................39

4 INPUT/OUTPUT PORTS

nput/output programming .................................................................................41orts A and B ....................................................................................................42ort C ................................................................................................................43ort D ................................................................................................................43ort registers .....................................................................................................44

Port data registers A and B (PORTA and PORTB) ......................................44Port data register C (PORTC)......................................................................44Port data register D (PORTD)......................................................................45

A/D status/control register......................................................................45Data direction registers (DDRA, DDRB and DDRC)....................................45

ther port considerations ..................................................................................46

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MC68HC0Rev. 4

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5 PROGRAMMABLE TIMER

5.1 Counter ..............................................................................................................515.1.1 Counter register and alternate counter register ...........................................535.2 T5.2.15.2.25.3 I5.3.15.3.25.4 O5.4.15.4.25.4.35.5 P5.5.15.6 T5.7 T5.8 T

6.1 S6.2 S6.3 S6.4 F6.5 D6.6 R6.6.16.6.26.7 R6.8 S6.9 T6.10 S6.11 S6.11.16.11.26.11.36.11.46.11.56.12 B6.13 S6.14 S

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TABLE OF CONTENTS

imer control and status ....................................................................................54Timer control register (TCR) ........................................................................54Timer status register (TSR)..........................................................................56

nput capture......................................................................................................57Input capture register 1 (ICR1) ....................................................................57Input capture register 2 (ICR2) ....................................................................58

utput compare.................................................................................................59Output compare register 1 (OCR1)..............................................................59Output compare register 2 (OCR2)............................................................510Software force compare .............................................................................511

ulse Length Modulation (PLM) ......................................................................511Pulse length modulation registers A and B (PLMA/PLMB) ........................511

imer during STOP mode................................................................................512imer during WAIT mode.................................................................................512imer state diagrams .......................................................................................512

6 SERIAL COMMUNICATIONS INTERFACE

CI two-wire system features ............................................................................61CI receiver features .........................................................................................63CI transmitter features.....................................................................................63unctional description........................................................................................63ata format ........................................................................................................65eceiver wake-up operation ..............................................................................65

Idle line wake-up ..........................................................................................66Address mark wake-up ................................................................................66

eceive data in (RDI) ........................................................................................66tart bit detection...............................................................................................66ransmit data out (TDO) ....................................................................................68CI synchronous transmission ..........................................................................69CI registers ....................................................................................................610

Serial communications data register (SCDR) ............................................610Serial communications control register 1 (SCCR1) ...................................610Serial communications control register 2 (SCCR2) ...................................614Serial communications status register (SCSR)..........................................616Baud rate register (BAUD) .........................................................................618

aud rate selection ..........................................................................................619CI during STOP mode ...................................................................................621CI during WAIT mode ....................................................................................621



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7 PULSE LENGTH D/A CONVERTERS

7.1 Miscellaneous register.......................................................................................737.2 PLM clock selection...........................................................................................747.3 P7.4 P

8.1 A8.2 A8.2.18.2.28.2.38.3 A8.4 A8.5 P

9.1 R9.1.19.1.29.1.39.1.49.1.4.19.1.4.29.1.59.2 I9.2.19.2.29.2.39.2.3.19.2.3.29.2.3.39.2.3.49.2.4

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LM during STOP mode ...................................................................................74LM during WAIT mode ....................................................................................74

8 ANALOG TO DIGITAL CONVERTER

/D converter operation.....................................................................................81/D registers......................................................................................................83

Port D data register (PORTD)......................................................................83A/D result data register (ADDATA) ...............................................................83A/D status/control register (ADSTAT)...........................................................84

/D converter during STOP mode.....................................................................86/D converter during WAIT mode......................................................................86ort D analog input............................................................................................86

9 RESETS AND INTERRUPTS

esets ...............................................................................................................91Power-on reset.............................................................................................92 Miscellaneous register ................................................................................92RESET pin ...................................................................................................93Computer operating properly (COP) watchdog reset ..................................93

COP watchdog during STOP mode .......................................................94COP watchdog during WAIT mode ........................................................94

Functions affected by reset..........................................................................95nterrupts ...........................................................................................................96

Interrupt priorities.........................................................................................96Nonmaskable software interrupt (SWI) ........................................................96Maskable hardware interrupts......................................................................97

External interrupt (IRQ)..........................................................................97 Miscellaneous register ..........................................................................99Timer interrupts ....................................................................................910Serial communications interface (SCI) interrupts.................................910

Hardware controlled interrupt sequence....................................................911



MC68HC0Rev. 4

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10 CPU CORE AND INSTRUCTION SET

10.1 Registers .........................................................................................................10110.1.1 Accumulator (A) .........................................................................................10210.1.210.1.310.1.410.1.510.2 I10.2.110.2.210.2.310.2.410.2.510.2.610.3 A10.3.110.3.210.3.310.3.410.3.510.3.610.3.710.3.810.3.910.3.10

11.1 A11.2 D11.2.111.2.211.3 A11.4 C

12.1 M12.1.112.1.2

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Index register (X)........................................................................................102Program counter (PC)................................................................................102Stack pointer (SP)......................................................................................102Condition code register (CCR)...................................................................102

nstruction set ..................................................................................................103Register/memory Instructions ....................................................................104Branch instructions ....................................................................................104Bit manipulation instructions ......................................................................104Read/modify/write instructions ...................................................................104Control instructions ....................................................................................104Tables.........................................................................................................104

ddressing modes.........................................................................................1011Inherent....................................................................................................1011Immediate ................................................................................................1011Direct........................................................................................................1011Extended..................................................................................................1012Indexed, no offset.....................................................................................1012Indexed, 8-bit offset..................................................................................1012Indexed, 16-bit offset................................................................................1012Relative ....................................................................................................1013Bit set/clear ..............................................................................................1013Bit test and branch ...................................................................................1013

11 ELECTRICAL SPECIFICATIONS

bsolute maximum ratings ..............................................................................111C electrical characteristics ............................................................................112

IDD trends for 5V operation ........................................................................113IDD trends for 3.3V operation .....................................................................116

/D converter characteristics...........................................................................118ontrol timing ................................................................................................1110

12 MECHANICAL DATA

C68HC05B family pin configurations ............................................................12152-pin plastic leaded chip carrier (PLCC) ..................................................12164-pin quad flat pack (QFP).......................................................................122



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12.1.3 56-pin shrink dual in line package (SDIP)..................................................12312.2 MC68HC05B6 mechanical dimensions...........................................................12412.2.1 52-pin plastic leaded chip carrier (PLCC) ..................................................12412.2.2 64-pin quad flat pack (QFP).......................................................................12512.2.3 56-pin shrink dual in line package (SDIP)..................................................126

13.1 E13.2 V13.3 R

A.1 FA.2 S

B.1 F

C.1 FC.2 EC.2.1C.3 EC.3.1C.4 OC.5 BC.5.1C.5.2C.5.3C.5.4C.5.5C.6 DC.7 C

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13 ORDERING INFORMATION

PROMS.........................................................................................................132erification media ............................................................................................132OM verification units (RVU)...........................................................................132

A MC68HC05B4

eatures ........................................................................................................... A1elf-check mode............................................................................................... A5

B MC68HC05B8

eatures ........................................................................................................... B1

C MC68HC705B5

eatures ........................................................................................................... C1PROM ............................................................................................................ C5

EPROM programming operation................................................................. C5PROM registers.............................................................................................. C6

EPROM control register .............................................................................. C6ptions register (OPTR)................................................................................... C7ootstrap mode ................................................................................................ C8

Erased EPROM verification ...................................................................... C11EPROM parallel bootstrap load ................................................................ C11EPROM (RAM) serial bootstrap load and execute ................................... C13RAM parallel bootstrap load and execute ................................................. C14Bootstrap loader timing diagrams ............................................................. C17

C electrical characteristics ........................................................................... C19ontrol timing ................................................................................................. C19



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D MC68HC05B16

D.1 Features............................................................................................................D1D.2 Self-check routines ...........................................................................................D2D.3 E

E.1 FE.2 EE.3 EE.3.1E.3.2E.3.3E.3.4E.3.5E.4 BE.4.1E.4.2E.4.3E.4.4E.4.4.1E.5 AE.6 DE.7 AE.8 CE.9 E

F.1 FF.2 EF.3 RF.4 EF.4.1F.4.2F.4.3F.4.4F.4.5F.5 BF.5.1

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TABLE OF CONTENTS

xternal clock ...................................................................................................D4

E MC68HC705B16

eatures............................................................................................................ E2xternal clock ................................................................................................... E5PROM............................................................................................................. E5

EPROM read operation............................................................................... E5EPROM program operation......................................................................... E5EPROM/EEPROM/ECLK control register ................................................... E6Mask option register.................................................................................... E8EEPROM options register (OPTR).............................................................. E9

ootstrap mode .............................................................................................. E10Erased EPROM verification ...................................................................... E13EPROM/EEPROM parallel bootstrap........................................................ E13EEPROM/EPROM/RAM serial bootstrap.................................................. E16RAM parallel bootstrap ............................................................................. E19

Jump to start of RAM ($0050) ............................................................. E20bsolute maximum ratings ............................................................................. E21C electrical characteristics ........................................................................... E22/D converter characteristics.......................................................................... E24ontrol timing ................................................................................................. E26PROM electrical characteristics ................................................................... E28

F MC68HC705B16N

eatures............................................................................................................ F2xternal clock ................................................................................................... F5ESET pin........................................................................................................ F5PROM............................................................................................................. F5

EPROM read operation............................................................................... F5EPROM program operation......................................................................... F6EPROM/EEPROM/ECLK control register ................................................... F6Mask option register.................................................................................... F8EEPROM options register (OPTR).............................................................. F9

ootstrap mode .............................................................................................. F10Erased EPROM verification ...................................................................... F13



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F.5.2 EPROM/EEPROM parallel bootstrap.........................................................F13F.5.3 Serial RAM loader......................................................................................F16F.5.3.1 Jump to start of RAM ($0051)..............................................................F16F.6 Absolute maximum ratings ..............................................................................F19F.7 DC electrical characteristics ............................................................................F20F.8 AF.9 CF.10 E

G.1 FG.2 E

H.1 FH.2 EH.3 RH.4 EH.4.1H.4.2H.4.3H.4.4H.4.5H.5 BH.5.1H.5.2H.5.3H.5.3.1H.6 AH.7 DH.8 AH.9 CH.10 E

I.1 DI.2 AI.3 C

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/D converter characteristics...........................................................................F22ontrol timing ..................................................................................................F24PROM electrical characteristics ....................................................................F26

G MC68HC05B32

eatures ...........................................................................................................G1xternal clock ...................................................................................................G2

H MC68HC705B32

eatures ........................................................................................................... H3xternal clock ................................................................................................... H7ESET pin........................................................................................................ H7PROM ............................................................................................................ H7

EPROM read operation............................................................................... H8EPROM program operation ........................................................................ H8EPROM/EEPROM control register ............................................................. H8Mask option register ................................................................................. H11Options register (OPTR) ........................................................................... H12

ootstrap mode .............................................................................................. H13Erased EPROM verification ...................................................................... H16EPROM/EEPROM parallel bootstrap........................................................ H16Serial RAM loader..................................................................................... H19

Jump to start of RAM ($0051)............................................................. H19bsolute maximum ratings ............................................................................. H22C electrical characteristics ........................................................................... H23/D converter characteristics.......................................................................... H25ontrol timing ................................................................................................. H27PROM electrical characteristics ................................................................... H29

I HIGH SPEED OPERATION

C electrical characteristics ...............................................................................I2/D converter characteristics..............................................................................I3ontrol timing for 5V operation...........................................................................I4



MC68HC0Rev. 4

FigureNumber

LIST OF FIGURES

1-12-12-22-32-42-53-14-14-24-35-15-25-35-45-56-16-26-36-46-56-66-76-86-96-107-17-27-38-18-29-1 Reset timing diagram..........................................................................................919-2 Watchdog system block diagram........................................................................939-3

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LIST OF FIGURES

Interrupt flow chart..............................................................................................98

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MC68HC05B6 block diagram .............................................................................13MC68HC05B6 load program in RAM and execute schematic diagram.............23MC68HC05B6 jump to any address schematic diagram...................................25STOP and WAIT flowcharts ................................................................................27Slow mode divider block diagram .......................................................................29Oscillator connections ......................................................................................212Memory map of the MC68HC05B6 ....................................................................32Standard I/O port structure.................................................................................42ECLK timing diagram..........................................................................................43Port logic levels...................................................................................................4616-bit programmable timer block diagram ..........................................................52Timer state timing diagram for reset .................................................................513Timer state timing diagram for input capture ....................................................513Timer state timing diagram for output compare ................................................514Timer state timing diagram for timer overflow...................................................514Serial communications interface block diagram .................................................62SCI rate generator division .................................................................................64Data format.........................................................................................................65SCI examples of start bit sampling technique ....................................................67SCI sampling technique used on all bits.............................................................67Artificial start following a framing error ...............................................................68SCI start bit following a break.............................................................................68SCI example of synchronous and asynchronous transmission ..........................69SCI data clock timing diagram (M=0) ...............................................................612SCI data clock timing diagram (M=1) ...............................................................613PLM system block diagram.................................................................................71PLM output waveform examples.........................................................................72PLM clock selection............................................................................................74A/D converter block diagram ..............................................................................82Electrical model of an A/D input pin....................................................................86 Go to: www.freescale.com 15

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FigureNumber

PageNumberTITLE

10-1 Programming model ......................................................................................... 10110-2 Stacking order .................................................................................................. 10111-1 Run IDD vs internal operating frequency (4.5V, 5.5V) ...................................... 11311-2 Run IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V) ....................... 11311-3 Wait IDD vs internal operating frequency (4.5V, 5.5V)...................................... 11311-411-511-611-711-811-911-1011-1111-1211-1312-112-212-312-412-512-6A-1A-2A-3B-1B-2C-1C-2C-3C-4C-5C-6C-7C-8C-9C-10D-1D-2D-3E-1E-2E-3

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LIST OF FIGURES

Wait IDD (SM = 1) vs internal operating frequency (4.5V, 5.5V)....................... 114Increase in IDD vs frequency for A/D, SCI systems active, VDD = 5.5V........... 114IDD vs mode vs internal operating frequency, VDD = 5.5V................................ 114Run IDD vs internal operating frequency (3 V, 3.6V)......................................... 116Run IDD (SM = 1) vs internal operating frequency (3V,3.6V) ........................... 116Wait IDD vs internal operating frequency (3V, 3.6V)......................................... 116Wait IDD (SM = 1) vs internal operating frequency (3V, 3.6V).......................... 117Increase in IDD vs frequency for A/D, SCI systems active, VDD = 3.6V............ 117IDD vs mode vs internal operating frequency, VDD = 3.6V................................ 117Timer relationship........................................................................................... 111252-pin PLCC pinout for the MC68HC05B6....................................................... 12164-pin QFP pinout for the MC68HC05B6......................................................... 12256-pin SDIP pinout for the MC68HC05B6........................................................ 12352-pin PLCC mechanical dimensions .............................................................. 12464-pin QFP mechanical dimensions................................................................. 12556-pin SDIP mechanical dimensions................................................................ 126MC68HC05B4 block diagram.............................................................................A2Memory map of the MC68HC05B4 ....................................................................A3MC68HC05B4 self-check schematic diagram....................................................A7MC68HC05B8 block diagram.............................................................................B2Memory map of the MC68HC05B8 ....................................................................B3MC68HC705B5 block diagram.......................................................................... C2Memory map of the MC68HC705B5 ................................................................. C3Modes of operation flow chart (1 of 2)............................................................... C9Modes of operation flow chart (2 of 2)............................................................. C10Timing diagram with handshake...................................................................... C11EPROM(RAM) parallel bootstrap schematic diagram ..................................... C12EPROM (RAM) serial bootstrap schematic diagram ....................................... C15RAM parallel bootstrap schematic diagram..................................................... C16EPROM parallel bootstrap loader timing diagram ........................................... C17 RAM parallel loader timing diagram ............................................................... C18MC68HC05B16 block diagram.......................................................................... D3Oscillator connections ....................................................................................... D4Memory map of the MC68HC05B16 ................................................................. D5MC68HC705B16 block diagram.........................................................................E2Memory map of the MC68HC705B16 ................................................................E3Modes of operation flow chart (1 of 2)..............................................................E11



MC68HC0Rev. 4

FigureNumber

PageNumberTITLE

E-4 Modes of operation flow chart (2 of 2) ............................................................. E12E-5 Timing diagram with handshake...................................................................... E14E-6 Parallel EPROM loader timing diagram ........................................................... E14E-7 EPROM Parallel bootstrap schematic diagram................................................ E15E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram ......................... E17E-9E-10E-11F-1F-2F-3F-4F-5F-6F-7F-8F-9F-10G-1G-2H-1H-2H-3H-4H-5H-6H-7H-8H-9H-10I-1

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.5B6 MOTOROLAxi

LIST OF FIGURES

Parallel RAM loader timing diagram ................................................................ E19RAM parallel bootstrap schematic diagram..................................................... E20Timer relationship ............................................................................................ E28MC68HC705B16N block diagram.......................................................................F2Memory map of the MC68HC705B16N..............................................................F3Modes of operation flow chart (1 of 2) ..............................................................F11Modes of operation flow chart (2 of 2) ..............................................................F12Timing diagram with handshake.......................................................................F14Parallel EPROM loader timing diagram ............................................................F14EPROM parallel bootstrap schematic diagram.................................................F15RAM load and execute schematic diagram ......................................................F17Parallel RAM loader timing diagram .................................................................F18Timer relationship .............................................................................................F26MC68HC05B32 block diagram .......................................................................... G2Memory map of the MC68HC05B32 ................................................................. G3MC68HC705B32 block diagram ........................................................................ H4Memory map of the MC68HC705B32 ............................................................... H5Modes of operation flow chart (1 of 2) ............................................................. H14Modes of operation flow chart (2 of 2) ............................................................. H15Timing diagram with handshake...................................................................... H17Parallel EPROM loader timing diagram ........................................................... H17EPROM parallel bootstrap schematic diagram................................................ H18RAM load and execute schematic diagram ..................................................... H20Parallel RAM loader timing diagram ................................................................ H21Timer relationship ............................................................................................ H29Timer relationship ................................................................................................ I5



MOTOROLxii

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LIST OF FIGURES

THIS PAGE LEFT BLANK INTENTIONALLY



MC68HC0Rev. 4

TableNumber

LIST OF TABLES

1-12-13-13-23-34-16-16-26-36-46-56-68-18-29-19-29-310-110-210-310-410-510-610-710-810-911-111-211-311-411-5 A/D characteristics for 3.3V operation ..............................................................11911-6 Control timing for 5V operation.......................................................................111011-7

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.5B6 MOTOROLAxiii

LIST OF TABLES

Control timing for 3.3V operation....................................................................1111

TPG


Data sheet appendices.......................................................................................11Mode of operation selection ...............................................................................21EEPROM control bits description .......................................................................34Register outline...................................................................................................38IRQ sensitivity.....................................................................................................39I/O pin states ......................................................................................................42Method of receiver wake-up .............................................................................611SCI clock on SCLK pin .....................................................................................613First prescaler stage .........................................................................................618Second prescaler stage (transmitter) ...............................................................618Second prescaler stage (receiver)....................................................................619SCI baud rate selection ....................................................................................620A/D clock selection .............................................................................................84A/D channel assignment.....................................................................................85Effect of RESET, POR, STOP and WAIT............................................................95Interrupt priorities ...............................................................................................97IRQ sensitivity.....................................................................................................99MUL instruction.................................................................................................105Register/memory instructions...........................................................................105Branch instructions ...........................................................................................106Bit manipulation instructions.............................................................................106Read/modify/write instructions .........................................................................107Control instructions...........................................................................................107Instruction set (1 of 2).......................................................................................108Instruction set (2 of 2).......................................................................................109M68HC05 opcode map...................................................................................1010Absolute maximum ratings ...............................................................................111DC electrical characteristics for 5V operation...................................................112DC electrical characteristics for 3.3V operation................................................115A/D characteristics for 5V operation .................................................................118 Go to: www.freescale.com 19

MOTOROLxiv

TableNumber

PageNumberTITLE

13-1 MC order numbers ........................................................................................... 13113-2 EPROMs for pattern generation ....................................................................... 132A-1 Mode of operation selection ...............................................................................A1A-2 Register outline ..................................................................................................A4A-3 MC68HC05B4 self-check results .......................................................................A6B-1C-1C-2C-3C-4C-5D-1D-2E-1E-2E-3E-4E-5E-6E-7E-8E-9E-10E-11E-12E-13E-14E-15F-1F-2F-3F-4F-5F-6F-7F-8F-9F-10F-11F-12F-13F-14

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.A MC68HC05B6Rev. 4

LIST OF TABLES

Register outline ..................................................................................................B4Register outline ................................................................................................. C4Mode of operation selection .............................................................................. C8Bootstrap vector targets in RAM ..................................................................... C14Additional DC electrical characteristics for MC68HC705B5............................ C19Additional control timing for MC68HC705B5................................................... C19Mode of operation selection .............................................................................. D2Register outline ................................................................................................. D6Register outline ..................................................................................................E4EPROM control bits description .........................................................................E6EEPROM control bits description .......................................................................E7Mode of operation selection .............................................................................E10Bootstrap vector targets in RAM ......................................................................E18Absolute maximum ratings ...............................................................................E21DC electrical characteristics for 5V operation ..................................................E22DC electrical characteristics for 3.3V operation ...............................................E23A/D characteristics for 5V operation.................................................................E24A/D characteristics for 3.3V operation..............................................................E25Control timing for 5V operation.........................................................................E26Control timing for 3.3V operation......................................................................E27DC electrical characteristics for 5V operation ..................................................E28Control timing for 5V operation.........................................................................E28Control timing for 3.3V operation......................................................................E28Register outline ..................................................................................................F4EPROM control bits description .........................................................................F7EEPROM control bits description .......................................................................F8Mode of operation selection .............................................................................F10Bootstrap vector targets in RAM ......................................................................F16Absolute maximum ratings ...............................................................................F19DC electrical characteristics for 5V operation ..................................................F20DC electrical characteristics for 3.3V operation ...............................................F21A/D characteristics for 5V operation.................................................................F22A/D characteristics for 3.3V operation..............................................................F23Control timing for 5V operation.........................................................................F24Control timing for 3.3V operation......................................................................F25DC electrical characteristics for 5V operation ..................................................F26Control timing for 5V operation.........................................................................F26



MC68HC0Rev. 4

TableNumber

PageNumberTITLE

F-15 Control timing for 3.3V operation......................................................................F26G-1 Register outline.................................................................................................. G4H-1 Register outline.................................................................................................. H6H-2 EPROM control bits description......................................................................... H9H-3 EEPROM control bits description .................................................................... H10H-4H-5H-6H-7H-8H-9H-10H-11H-12H-13H-14H-15I-1I-2I-3

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.5B6 MOTOROLAxv

LIST OF TABLES

Mode of operation selection ............................................................................ H13Bootstrap vector targets in RAM...................................................................... H19Absolute Maximum ratings .............................................................................. H22DC electrical characteristics for 5V operation.................................................. H23DC electrical characteristics for 3.3V operation............................................... H24A/D characteristics for 5V operation ................................................................ H25A/D characteristics for 3.3V operation ............................................................. H26Control timing for 5V operation........................................................................ H27Control timing for operation at 3.3V................................................................. H28DC electrical characteristics for 5V operation.................................................. H29Control timing for 5V operation........................................................................ H29Control timing for 3.3V operation..................................................................... H29Ordering information............................................................................................ I1DC electrical characteristics for 5V operation...................................................... I2A/D characteristics for 5V operation .................................................................... I3



MOTOROLxvi

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LIST OF TABLES




MC68HC0Rev. 4

1The MC68low-cost siROM, EEPinterface, pfrequencie

This data sof appendi


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.5B6 MOTOROLA1-1

INTRODUCTION

INTRODUCTIONHC05B6 microcomputer (MCU) is a member of Motorolas MC68HC05 family ofngle chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM,ROM, A/D converter, pulse length modulated outputs, I/O, serial communicationsrogrammable timer system and watchdog. The fully static design allows operation at

s down to dc to further reduce the already low power consumption to a few micro-amps.

heet is structured such that devices similar to the MC68HC05B6 are described in a setces (see Table 1-1).

Table 1-1 Data sheet appendices

Device Appendix Differences from MC68HC05B6

MC68HC05B4 A 4K bytes ROM; no EEPROM

MC68HC05B8 B 7.25K bytes ROM

MC68HC705B5 C6K bytes EPROM; self-check replaced by bootstrap firmware; no EEPROM

MC68HC05B16 D 16K bytes ROM; increased RAM and self-check ROM

MC68HC705B16 E16K bytes EPROM; increased RAM; self-check replaced by bootstrap firmware; modified power-on reset routine

MC68HC705B16N F16K bytes EPROM; increased RAM; self-check replaced by bootstrap firmware; modified power-on reset routine

MC68HC05B32 G 32K bytes ROM; no page zero ROM; increased RAM

MC68HC705B32 H32K bytes EPROM; no page zero ROM; increased RAM; self-check mode replaced by bootstrap firmware

TPG

For More Information On This Product, Go to: www.freescale.com123

MOTOROL1-2

11.1 Features

Hardware features

Fully static design featuring the industry standard M68HC05 family CPU core

On chip crystal oscillator with divide by 2 or a software selectable divide by 32 option (SLOW mode)

2.1 MH

High sp

176 byt

5936 by

256 byt

Write/e

Self tes

Power s

Three 8

Softwar

16-bit ti

Compu

Serial cselectio

8 chann

2 pulse

One int

Availabshrink d

Complethe M68

Extend


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.A MC68HC05B6Rev. 4

INTRODUCTION

z internal operating frequency at 5V; 1.0 MHz at 3V

eed version available

es of RAM

tes of user ROM plus 14 bytes of user vectors

es of byte erasable EEPROM with internal charge pump and security bit

rase protect bit for 224 of the 256 bytes EEPROM

t/bootstrap mode

aving STOP, WAIT and SLOW modes

-bit parallel I/O ports and one 8-bit input-only port

e option available to output the internal E-clock to port pin PC2

mer with 2 input captures and 2 output compares

ter operating properly (COP) watchdog timerommunications interface system (SCI) with independent transmitter/receiver baud rate n; receiver wake-up function for use in multi-receiver systems

el A/D converter

length modulation systems which can be used as D/A converters

errupt request input plus 4 on-board hardware interrupt sources

le in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat pack (QFP) and 56-pin ual in line (SDIP) packageste development system support available using the MMDS05 development station with HC05B32EM emulation module

ed operating temperature range of -40 to +125 C

TPG

For More Information On This Product, Go to: www.freescale.com 24

MC68HC0Rev. 4

1.2 Mask options for the MC68HC05B6

The MC68HC05B6 has three mask options that are programmed during manufacture and must bespecified on the order form.

Power-on-reset delay (tPORL) = 16 or 4064 cycles Automatic watchdog enable/disable following a power-on or external reset

Watchd

Warning:


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.5B6 MOTOROLA1-3

INTRODUCTION

og enable/disable during WAIT mode

It is recommended that an external clock is always used if tPORL is set to 16 cycles. Thiswill prevent any problems arising with oscillator stability when the device is put intoSTOP mode.

Figure 1-1 MC68HC05B6 block diagram

Port

A

PA0PA1PA2PA3PA4PA5PA6PA7

Port

B

PB0PB1PB2PB3PB4PB5PB6PB7

Port

C

PC0PC1PC2/ECLKPC3PC4PC5PC6PC7

16-bit programmable

timer

Port

D

PD0/AN0PD1/AN1PD2/AN2PD3/AN3PD4/AN4PD5/AN5PD6/AN6PD7/AN7

Oscillator

176 bytesRAM

COP watchdogRESET

IRQ

VDDVSS

OSC1OSC2

M68HC05CPU

SCIA/D converter

PLM

TCAP1TCAP2

TCMP1TCMP2

VRHVRL

RDISCLKTDO

VPP1

256 bytesEEPROM

Charge pump

2 / 32

PLMA D/APLMB D/A

8-bit

432 bytes

User ROM5950 bytes

self check ROM

(including 14 bytesUser vectors)

TPG


MOTOROL1-4

1


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.A MC68HC05B6Rev. 4

INTRODUCTION


TPG


MC68HC0Rev. 4

2

2.1

The MC68Table 2-1 s

2.1.1

This is the self-containports and tthe MCU.


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.5B6 MOTOROLA2-1



Modes of operation

HC05B6 MCU has two modes of operation, namely single chip and self check modes.hows the conditions required to enter each mode on the rising edge of RESET.

Single chip mode

normal operating mode of the MC68HC05B6. In this mode the device functions as aed microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O

he 8-bit input-only port, available to the user. All address and data activity occurs within

Table 2-1 Mode of operation selection

IRQ pin TCAP1 pin PD3 PD4 Mode

VSS to VDD VSS to VDD X X Single chip

2VDD VDD 1 0 Serial RAM loader

2VDD VDD 1 1 Jump to any address

TPG


MOTOROL2-2

22.2 Serial RAM loader

The load program in RAM and execute mode is entered if the following conditions are satisfiedwhen the reset pin is released to VDD. The format used is identical to the format used for theMC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to 1.

IRQ at 2xVDD

In the loadthe SCI pothe last byt$0051. Thebyte. The pSCI is confirate is 9600the RAM lo

If immediaexecution. Tlength of thadditional dthe MCU, including th

To load a pIn this instawhich will cis instructe

The erased

Figure 2-1


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.A MC68HC05B6Rev. 4


TCAP1 at VDDPD3 at VDD for at least 30 machine cycles after resetPD4 at VSS for at least 30 machine cycles after reset

program in RAM and execute routine, user programs are loaded into MCU RAM viart and then executed. Data is loaded sequentially, starting at RAM location $0050, untile is loaded. Program control is then transferred to the RAM program starting at location first byte loaded is the count of the total number of bytes in the program plus the countrogram starts at the second byte in RAM. During the firmware initialization stage, thegured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The baud with a 4 MHz crystal. A program to convert ASCII S-records to the format required byader is available from Motorola.

te execution is not desired after loading the RAM program, it is possible to hold offhis is accomplished by setting the byte count to a value that is greater than the overall

e loaded data. When the last byte is loaded, the firmware will halt operation expectingata to arrive. At this point, the reset switch is placed in the reset position which will reset

but keep the RAM program intact. All routines can now be entered from this state,e one which will execute the program in RAM (see Section 2.3). rogram in the EEPROM, the load program in RAM and execute function is also used.nce the process involves two distinct steps. Firstly, the RAM is loaded with a programontrol the loading of the EEPROM, and when the RAM contents are executed, the MCUd to load the EEPROM.

state of the EEPROM is $FF.shows the schematic diagram of the circuit required for the serial RAM loader.

TPG


MC68HC0Rev. 4

Fig

OSC1OSC2RESET

VDD

181617

10 k W

0.01 m F

10 nF 47 m F

10 M W

P1GND+5V2xVDD

RESET 10

9600 Bd

RS232

Connec for th


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.5B6 MOTOROLA2-3


ure 2-1 MC68HC05B6 load program in RAM and execute schematic diagram

32

IRQ

TCAP2TCMP2

TCAP1


PC7PC6PC5PC4PC3PC2PC1PC0

VSS

PD7PD6PD5

PD4

PD3

PD2PD1PD0


2425262728293031

19

41

4 MHz22 pF 22 pF

VRH

VRL

VPP1

PLMA

PLMB

TCMP1

RDITDO

NCNC

RS232 level translatorsuggested:MC145406 or MAX232

SCLK

10 k W

11

9

22

8

7

40

20

21

51

1

232

345121314

33343536373839

4243444546474849

615

5052

Connect as required for the application

t as requirede application

MC

68H

C05

B6 (5

2-pi

n pa

ckag

e)

TPG


MOTOROL2-4

22.3 Jump to any address

The jump to any address mode is entered when the reset pin is released to VDD, if the followingconditions are satisfied:

IRQ at 2xVDD TCAP1 at VDD

This functimethods o

To executeport B andexecution o


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.A MC68HC05B6Rev. 4


PD3 at VDD for at least 30 machine cycles after resetPD4 at VDD for at least 30 machine cycles after reset

on allows execution of programs previously loaded in RAM or EEPROM using theutlined in Section 2.2.

the jump to any address function, data input at port A has to be $CC and data input at port C should represent the MSB and LSB respectively, of the address to jump to forf the user program. A schematic diagram of the circuit required is shown in Figure 2-2.

TPG


MC68HC0Rev. 4

OSC1OSC2RESET

VDD

181617

10 k W

0.01 m F

10 nF 47 m F

10 M W

P1GND+5V2xVDD

RESET 10

8

MSB

LSBS

elec

t req

uire

d ad

dres

s

Note:


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.5B6 MOTOROLA2-5


Figure 2-2 MC68HC05B6 jump to any address schematic diagram

32

IRQ

TCAP2TCMP2

TCAP1


PC7PC6PC5PC4PC3PC2PC1PC0

VSS

PD7PD6PD5

PD4

PD3

PD2PD1PD0


2425262728293031

19

41

4 MHz22 pF 22 pF

VRH

VRL

VPP1

PLMA

PLMB

TCMP1

RDITDO

NCNC

SCLK

10 k W

11

9

22

8

7

40

20

21

51

1

232

345121314

33343536373839

4243444546474849

615

5052

Connect as required for the application

x 10 kW optional (see note)

8 x 10 k W

8 x 10 k W

These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 arekept in input mode during application.

MC

68H

C05

B6 (5

2-pi

n pa

ckag

e)

TPG


MOTOROL2-6

22.4 Low power modes

The STOP and WAIT instructions have different effects on the programmable timer, the serialcommunications interface, the watchdog system, the EEPROM and the A/D converter. Thesedifferent effects are described in the following sections.

2.4.1

The STOPinternal ocommunicathe MCU toof a reset (During STSection 10while exitin

All other recontinues uis turned correspond

When leavstabilise beor 4064 cyfetching the

Warning:

Note:

The followMC68HC0


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.A MC68HC05B6Rev. 4


STOP

instruction places the MCU in its lowest power consumption mode. In STOP mode, thescillator is turned off, halting all internal processing including timer, serialtions interface and the A/D converter (see flowchart in Figure 2-3). The only way for wake-up from the STOP mode is by receipt of an external interrupt or by the detectionlogic low on RESET pin or a power-on reset). OP mode, the I-bit in the CCR is cleared to enable external interrupts (see.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles countg STOP mode (see Section 2.4.3). gisters and memory remain unaltered and all input/output lines remain unchanged. Thisntil an external interrupt (IRQ) or reset is sensed, at which time the internal oscillator

on. The external interrupt or reset causes the program counter to vector to theing locations ($1FFA, B and $1FFE, F respectively).

ing STOP mode, a tPORL internal cycles delay is provided to give the oscillator time tofore releasing CPU operation. This delay is selectable via a mask option to be either 16cles. The CPU will resume operation by servicing the interrupt that wakes it up, or by reset vector, if reset wakes it up.

If tPORL is selected to be 16 cycles, it is recommended that an external clock signal isused to avoid problems with oscillator stability while the device is in STOP mode.

The stacking corresponding to an eventual interrupt to go out of STOP mode will onlybe executed when going out of STOP mode.

ing list summarizes the effect of STOP mode on the individual modules of the5B6.

The watchdog timer is reset; refer to Section 9.1.4.1The EEPROM acts as read-only memory (ROM); refer to Section 3.6All SCI activity stopped; refer to Section 6.13The timer stops counting; refer to Section 5.6The PLM outputs remain at current level; refer to Section 7.3The A/D converter is disabled; refer to Section 8.3The I-bit in the CCR is cleared

TPG


MC68HC0Rev. 4

STOP WAIT

w

Watchdog active?YES

NO

Oscillator active. Timer, SCI,


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.5B6 MOTOROLA2-7


Figure 2-3 STOP and WAIT flowcharts

Timer interrupt?

IRQ external

interrupt?

SCI interrupt?

Stop oscillator and all clocks.

Clear I bit.

Reset?

IRQ external

interrupt?

Generate atchdog reset

Reset?

(1) Fetch reset vector or(2) Service interrupt:

a. stackb. set I-bitc. vector to interrupt

routine

(1) Fetch reset vector or(2) Service interrupt:

a. stackb. set I-bitc. vector to interrupt

routine

Turn on oscillator. Wait for time delay to

stabiliseRestart processor clock

NO

YES

YES

YES

YES

YES

YES

NO NO

NO

NO

NO

A/D, EEPROM clocks active. Processor clocks stopped

Clear I-bit

TPG


MOTOROL2-8

22.4.2 WAIT

The WAIT instruction places the MCU in a low power consumption mode, but WAIT modeconsumes more power than STOP mode. All CPU action is suspended and the watchdog isdisabled, but the timer, A/D and SCI systems remain active and operate as normal (see flowchartin Figure 2-3). All other memory and registers remain unaltered and all parallel input/output linesremain unchanged. The programming or erase mechanism of the EEPROM is also unaffected, aswell as the

During WAmiscellanesensed, theor reset se

Any IRQ, tilow on the

If a non-resremaining

If a reset e

Note:

The followi

2.4.2.1

Power conconsumptiolowest whetimer cannprogrammefunctionalit

Power cons


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.A MC68HC05B6Rev. 4


charge pump high voltage generator.

IT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in theous register (Section 2.5) is not affected by WAIT mode. When any interrupt or reset is program counter vectors to the locations containing the start address of the interrupt

rvice routine.

mer (overflow, input capture or output compare) or SCI interrupt (in addition to a logicRESET pin) causes the processor to exit WAIT mode.et exit from WAIT mode is performed (i.e. timer overflow interrupt exit), the state of the

systems will be unchanged.

xit from WAIT mode is performed the entire system reverts to the disabled reset state.

The stacking corresponding to an eventual interrupt to leave WAIT mode will only beexecuted when leaving WAIT mode.

ng list summarizes the effect of WAIT mode on the modules of the MC68HC05B6.

The watchdog timer functions according to the mask option selected; refer to Section 9.1.4.2The EEPROM is not affected; refer to Section 3.7The SCI is not affected; refer to Section 6.14The timer is not affected; refer to Section 5.7The PLM is not affected; refer to Section 7.4The A/D converter is not affected; refer to Section 8.4The I-bit in the CCR is cleared

Power consumption during WAIT mode

sumption during WAIT mode depends on how many systems are active. The powern will be highest when all the systems (A/D, timer, EEPROM and SCI) are active, andn the EEPROM erase and programming mechanism, SCI and A/D are disabled. Theot be disabled in WAIT mode. It is important that before entering WAIT mode, ther sets the relevant control bits for the individual modules to reflect the desired

y during WAIT mode.

umption may be further reduced by the use of SLOW mode.

TPG


MC68HC0Rev. 4

2.4.3 SLOW mode

The SLOW mode function is controlled by the SM bit in the miscellaneous register at location$000C. It allows the user to insert, under software control, an extra divide-by-16 between theoscillator and the internal clock driver (see Figure 2-4). This feature permits a slow down of all theinternal operations and thus reduces power consumption. The SLOW mode function should not beenabled while using the A/D converter or while erasing/programming the EEPROM unless theinternal A/D

2.4.3.1

SM Slow

1 (s

0 (c

The SM bitentering ST

Note:

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