day7: january 25, 2000 precise exceptions ilp intro
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CS184b: Computer Architecture [Single Threaded Architecture: abstractions, quantification, and optimizations]. Day7: January 25, 2000 Precise Exceptions ILP intro. Today. Handling Exceptions ILP where? scoreboard tomasulo. Exceptions. - PowerPoint PPT PresentationTRANSCRIPT
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Caltech CS184b Winter2001 -- DeHon
1
CS184b:Computer Architecture
[Single Threaded Architecture: abstractions, quantification, and
optimizations]
Day7: January 25, 2000
Precise Exceptions
ILP intro
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2
Today
• Handling Exceptions
• ILP– where?– scoreboard– tomasulo
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3
Exceptions
• Problem: Maintain sequentially consistent view, while relaxing strict, sequential dependence ordering
• Sequential stream from ISA
• Data/control dependence less strict
• Relaxed dependence accelerates execution
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In-Pipe
MPY R1,R2,R3 IF ID MPY1 MPY2 MPY3 WBLW R4,16(R6) IF ID EX MEM ---- WB
Fault for later instruction should not be visible before earlier.
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Out-of-Order Completion
MPY R1,R2,R3 IF ID EX MPY1 MPY2 MPY3 MPY4 WBLW R7,(R4) IF ID ALU MEM WBADD R4,R5,R6 IF ID ALU --- WB
State changes from later operations should not be visible if earlier operations fail.
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Solutions
• Stall side-effects as hazards– limit concurrency
• Imprecise exceptions – ? Recoverable / restartable
• Expose Pipeline– limit scalability, weaken abstraction
• Save list of PCs– cumberson
• Precise Exception support
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In-Order Completion
• Stall like data hazards
• Save up faults in pipeline until commit point– (faults, like WB occur in set place when know
predecessors haven’t faulted)
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In-Order
MPY R1,R2,R3 IF ID MPY1 MPY2 MPY3 WBLW R4,16(R6) IF ID EX MEM ---- WB
Commit fault with write back.
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In-Order Completion
MPY R1,R2,R3 IF ID EX MPY1 MPY2 MPY3 MPY4 WBLW R7,(R4) IF ID ALU MEM WBADD R4,R5,R6 IF ID ALU --- WB
MPY R1,R2,R3 IF ID EX MPY1 MPY2 MPY3 MPY4 WBLW R7,(R4) IF ID ALU MEM WBADD R4,R5,R6 IF ID ALU WB
IO
OO
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Re-Order Buffer
• Continue to execute
• Write-back to register file in-order
• Buffer results between completion and WB
• Bypass with newer results
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Re-Order
IF IDReorder
Bypass
EX
ALU
MPY
LD/ST
RF
Complex (big) bypass logic.
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History Buffer
• Keep track of values overwritten in register file
• Can restore old state from there
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History
IF
ID EX
ALU
MPY
LD/ST
RF
History
History Buffer contain:PC Reg. # prev. reg value
Use history to “rollback” state of computation to consistent/committed point.
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Future File
• Keep two copies of register file– committed / visible set– working set
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Future
IF
ID EX
ALU
MPY
LD/ST
RF
“Architecture” Register File
“Future”
Future RF contains working stateArchitecture RF contains only committed (seq. order) state.
Reorder
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Memory
• Note: may need to do re-order/bypass to memory as well– same issue as RF– not want to make visible state change– may want to run ahead (avoid adding dep.)
• Bigger issue as we go to longer latencies, OO-issue, etc.
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Instruction Level Parallelism
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Real Issue
• Sequential ISA Model adds an artificial constraint to the computational problem.
• Original problem (real computation) is not sequentially dependent as a long critical path.– Path Length != # of instructions
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Dataflow Graph
• Real problem is a graph
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Task Has Parallelism
MPY R3,R2,R2 MPY R4,R2,R5
MPY R3,R6,R3 ADD R4,R4,R7
ADD R4,R3,R4
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More when pipelined
• Working on stream (loop)
• may be able to perform all ops at once– …appropriately staggered in time.
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Problem
• For sequential ISA:– must linearize graph– create false dependencies
MPY R3,R2,R2 MPY R4,R2,R5
MPY R3,R6,R3 ADD R4,R4,R7
ADD R4,R3,R4
MPY R3,R2,R2MPY R3,R6,R3MPY R4,R2,R5ADD R4,R4,R7ADD R4,R3,R4
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ILP
• The original problem had parallelism
• Can we exploit it?
• Can we rediscover it after?– linearizing– scheduling– assigning resources
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If we can find the parallelism...
• …and will spend the silicon area
• can execute multiple instructions simultaneously
MPY R3,R2,R2; MPY R4,R2,R5MPY R3,R6,R3; ADD R4,R4,R7ADD R4,R3,R4IF
IDEX
RFALU1
ALU2
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First Challenge:Multi-issue, maintain depend
• Like Pipelining
• Let instructions go if no hazard
• Detect (potential hazards) – stall for data available
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Scoreboarding
• Easy conceptual model:– Each Register has a valid bit– At issue, read registers– If all registers have valid data
• mark result register invalid (stale)
• forward into execute
– else stall until all valid– When done
• write to register
• set result to valid
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Scoreboard MPY R3,R2,R2MPY R4,R2,R5MPY R3,R6,R3ADD R4,R4,R7ADD R4,R3,R4
2: 13: 14: 15: 16: 17: 1
IF
IDEX
RFALU1
ALU2
R2.valid=1
issue
Set R3.valid=0
2: 13: 04: 15: 16: 17: 1
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Scoreboard MPY R3,R2,R2MPY R4,R2,R5MPY R3,R6,R3ADD R4,R4,R7ADD R4,R3,R4
2: 13: 04: 15: 16: 17: 1
IF
IDEX
RFALU1
ALU2
R2.valid=1R5.valid=1
issue
Set R4.valid=0
2: 13: 04: 05: 16: 17: 1
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Scoreboard MPY R3,R2,R2MPY R4,R2,R5MPY R3,R6,R3ADD R4,R4,R7ADD R4,R3,R4
2: 13: 04: 05: 16: 17: 1
IF
IDEX
RFALU1
ALU2
R3.valid=0R6.valid=1
stall
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Scoreboard MPY R3,R2,R2MPY R4,R2,R5MPY R3,R6,R3ADD R4,R4,R7ADD R4,R3,R4
2: 13: 04: 05: 16: 17: 1
IF
IDEX
RFALU1
ALU2
MPY R3 complete
Set R3.valid=1
2: 13: 14: 05: 16: 17: 1
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Scoreboard MPY R3,R2,R2MPY R4,R2,R5MPY R3,R6,R3ADD R4,R4,R7ADD R4,R3,R4
2: 13: 14: 05: 16: 17: 1
IF
IDEX
RFALU1
ALU2
R3.valid=1R6.valid=1
Set R3.valid=0
2: 13: 04: 05: 16: 17: 1
issue
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Scoreboard
• Of course, bypass– bypass as we did in pipeline– incorporate into stall checks
• so can continue as soon as result shows up
• Also, careful not to issue – when result register invalid (WAW)
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Ordering
• As shown– issue instructions in order– stall on first dependent instruction
• get head-of-line-blocking
• Alternative– Out of order issue
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Example
MPY R3,R2,R2MPY R4,R2,R5MPY R3,R6,R3ADD R4,R4,R7ADD R4,R3,R4
MPY R3,R2,R2MPY R3,R6,R3MPY R4,R2,R5ADD R4,R4,R7ADD R4,R3,R4
MPY R3,R2,R2 MPY R4,R2,R5
MPY R3,R6,R3 ADD R4,R4,R7
ADD R4,R3,R4
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Example
• This sequence block on in-order issue– second instruction depend
on first
• But 3rd instruction not depend on first 2.
MPY R3,R2,R2MPY R3,R6,R3MPY R4,R2,R5ADD R4,R4,R7ADD R4,R3,R4
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Example
• Out of Order– look beyond head pointer
for enabled instructions– issue and scoreboard next
found
MPY R3,R2,R2MPY R3,R6,R3MPY R4,R2,R5ADD R4,R4,R7ADD R4,R3,R4
MPY R3,R6,R3 stalls for R3 to be computed
MPR4,R2,R5 can be issued while R3 waiting
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False Sequentialization on Register Names
• Problem: reuse of small set of register names may introduce false sequentialization
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
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False Sequentialization
• Recognize:– register names are just a way of describing local
dataflow
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
This says: the result of adding R5 and R6 gets stored into the address pointed to by R1
R2 only describes the dataflow.
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Renaming
• Trick:– separate ISA (“architectural”) register names
from functional/physical registers– allocate a new register on definitions
• (compare def-use chains in cs134b?)
– keep track of all uses (until next definition)– assign all uses the new register name at issue– use new register name to track dependencies,
bypass, scoreboarding...
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Example
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
Rename TableR1: P2R2: P6R3: P7R4: P8R5: P9R6: P10Free Table: P1 P3 P4 P11
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Example
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
Rename TableR1: P2R2: P6R3: P7R4: P8R5: P9R6: P10Free Table: P1 P3 P4 P11
Rename TableR1: P2R2: P1R3: P7R4: P8R5: P9R6: P10Free Table: P3 P4 P11
Issue: ADD P1,P7,P8
Allocate P1 for R2
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Example
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
Rename TableR1: P2R2: P1R3: P7R4: P8R5: P9R6: P10Free Table: P3 P4 P11
Rename TableR1: P2R2: P1R3: P7R4: P8R5: P9R6: P10Free Table: P3 P4 P11
Issue: SW P1,(P2)
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Example
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
Rename TableR1: P2R2: P1R3: P7R4: P8R5: P9R6: P10Free Table: P3 P4 P11
Rename TableR1: P3R2: P1R3: P7R4: P8R5: P9R6: P10Free Table: P2 P4 P11
Issue: ADD P3,1,P2
Allocate P3 for P1
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Example
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
Rename TableR1: P3R2: P1R3: P7R4: P8R5: P9R6: P10Free Table: P2 P4 P11
Rename TableR1: P3R2: P4R3: P7R4: P8R5: P9R6: P10Free Table: P2 P11
Issue: ADD P4,P9,P10
Allocate P4 for R2
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Example
ADD R2,R3,R4SW R2,(R1)ADD R1,1,R1ADD R2,R5,R6SW R2,(R1)
Rename TableR1: P3R2: P4R3: P7R4: P8R5: P9R6: P10Free Table: P2 P11
Rename TableR1: P3R2: P4R3: P7R4: P8R5: P9R6: P10Free Table: P2 P11
Issue: SW P4,(P3)
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Free Physical Register
• Free after complete last use
• Identify last use by next def?
• Or, allocate in order (LRU) – interlock if re-assignment conflict– (should correspond to having no free physical
registers)
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Tomasulo
• Register renaming
• Scoreboarding
• Bypassing
• IBM 1967
• …what’s keeping x86 ISA alive today– compensate for small number of arch. Registers– dusty deck code
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Today
• Seen can turn a basic block– (code between branches)
• Into executing dataflow graph– I.e. once issues, only dataflow dependencies
limit parallelism
• …all the more reason to want large basic blocks (minimize branch, branch effects)
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Reading Note
• Today: HP4.1-2, Tomasulo
• Next Week: – rest of HP4– Fisher/predict relevant
• probably touch on Tuesday
– Subbarao Quantifying…• probably Thursday
• Following Week: VLIW and EPIC– Fisher, IA-64...
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Big Ideas
• Data Versioning– keep old copies, until commit– working versus finalized
• Parallelism does exist in the problem– obscured by ISA linearization
• Dataflow Interpretation– preserve dependencies, not control flow
sequence– rediscover non-linear “graph”