ddhdl ppt

2/13/2015

Shailendra Kumar Tiwari (Asst. Prof) 1

Department of Electronics & Communication Engineering, MIT, Manipal

Digital Design & Hardware Description Language

(DDHDL)

S. K. Tiwari (Asst. Prof.) Department of Electronics & Communication Engineering, MIT, Manipal

Course Overview Reference Books Introduction Moores law Technology generation Why integrated circuits? Programmable Logic Devices(PLD) Logic Circuit implementation using PLD

Outline

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Course Overview Digital System implementation using MSI/LSI PLDs & Combinational and Seq. Circuit implementation using PLDs. ASICs, FPGA and CPLDs ACTEL, XILINX and ALTERA Logic

modules Programmable I/O cells, ASIC Design flow & Simulation hierarchy

Testing Combinational Circuit Fault Table ,Boolean difference method , Path Sensitization, D-Algorithm, PODEM, Fault-collapsing technique.

Testing sequential circuits Design-for-test(DFT) and Y-Chart.

VHDL modeling concepts-syntax, Data types, Delay and delay models Sequential modeling, Structural modeling & Dataflow modeling Subprograms, Packages ,Writing test benchesM

odul

e-03

Mod

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02M

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e-01


Reference Books1. M.J.S.Smith (1997),Application Specific Integrated

Circuits, Addison Wesley.2. Alexander Miczo(1987) , Digital logic testing and

simulation , John Wiley & Sons.3. Vishwani D. Agrawal (2002) Essentials Of Electronic

Testing For Digital, Memory And Mixed-signal VlsiCircuits Kluwer Academic Publishers

4. J.Bhaskar (2002) , VHDL Primer , 3rd edition, AddisonWesley Longman Singapore Pvt Ltd.

PrerequisitePrerequisite for this course is DIGITAL LOGIC DESIGN.

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IntroductionThe first electronic Computer


Intel, 1971.2,300 transistors (12mm2)740 KHz operation(10m PMOS technology)

Intel, 2006.291,000,000 transistors(143mm2)3 GHz operation(65nm CMOS technology)

Intel Core 2 MicroprocessorIntel 4004 Microprocessor

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Moores law. In 1965, Gordon Moore noted that the number of

transistors on a chip doubled every 18 to 24months.

He made a prediction that semiconductortechnology will double its effectiveness every 18months


Moores law.


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Technology generation Generation Level Year Number of

TransistorsDRAM

integration

Small Scale Integration

1950s Less than 102

Medium Scale Integration

1960s 102 to 103

Large Scale Integration

1970s 103 to 105 4K, 16 K, 64 K

Very Large Scale Integration

1980s 105 to 107 256 K, 1M, 4M

Ultra Large Scale Integration

1990s 107 to 109 16 M, 64 M,256M

Super Large Scale Integration

2000s More than 109 1 Gb, 4Gb andabove


Why integrated circuits?Integration of a large function of large no of logic devices on a single chip provides the following advantage

Less area or increased volume, and therefore compactness.

Less power consumption. Less testing requirement at the system level. Higher reliability mainly due to improved on chip

interconnection. Higher speed due to significant reduced interconnection

length. Significant cost saving.


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Programmable Logic Devices(PLD)Definition: A Programmable Logic Device (PLD) is a chipthat is manufactured with a programmable configuration,enabling it to serve in many arbitrary applications

Programmable logic arrays (PLAs) implement two-levelcombinational logic in sum-of-products (SOP) form. Toimplement the sequential logic we need additional memoryelement i.e. Flip-Flops.

M N P PLD


Types of the ANDOR structured programmable logic devices are

1. Programmable read-only memory (PROM)2. Programmable logic array (PLA)3. Programmable array logic (PAL)

Programmable Logic Devices(PLD)

PLD AND Plane OR PlanePROM Fixed Programmable

PLA Programmable ProgrammablePAL Programmable Fixed


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PLD NotationProgrammable(Fig. a to f )

Fixed(Fig. g and h)


Slide No 15

Read Only MemoryTypes of ROM

1.PROM2.EPROM3.EEPROM or E2PROM4.MASK Programmable ROM

Advantage1. Ease of Design2. Design can be changed, modified rapidly3. Faster than discrete MSI/SSI circuit

Disadvantage1. Non-utilization of complete hardware2. Increased power requirement3. Increased size for large number of input


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Lecture-02

Review of Lecture 01 PROM PLA PAL Example Problems

Outline


Programmable Read Only Memory


Slide-13

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Programmable Logic Array


Programmable Logic Array

Advantage1. Logic function is implemented with minimum hardware.2. Comparatively less power dissipation.

Disadvantage1. We have two degree of freedom i.e. AND plane and OR

plane both are programmable therefore it is difficult to program.


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Programmable Array Logic


Advantage1. The OR array is fixed and hence it is

easy to program.2. Less expensive.3. Speed is high in PAL than PLADisadvantage1. Common product term can not be used

more than once.

Programmable Array Logic


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PAL Outputs

1. OR gate2. NOR gate3. EXOR gate4. EXNOR gate5. Registered output6. Registered output with enable7. Programmable Input/output


Programmable Array Logic1

2

9

10

20

18

11

1917

1413

12

Programmable I/O Pin

Programmable I/O Pin

4 Registered Output

CLOCK

GND

VCC

Enable

16 R 4INPUT

16 InputsR Registered output4 Outputs


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F0= A + BCF1= AC+ABF2= BC+ABF3= BC+AB

Implement the following functions using PROM, PLA and PAL.


Example Problem

Lecture-03 & 04

One input one-output sequence detector that produces anoutput value 1 every time the sequence 0101 is detected andan output value 0 at all other times. For example, if the inputsequence is 010101 then the corresponding output sequenceis 000101.


Example Problem-1

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Solution-1

Alternate approach


Solution-1

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An application of PROM is to realize lookuptable for an arithmetic function. Using PROMof smallest appropriate size draw the logicdiagram in PLD notation for a PROMrealization of the look-up tablecorresponding to the decimal arithmeticexpression f(x)= 2x+2 for 0x6. where f(x)and x are expressed in binary.

Example Problem-2


f(x)= 2x+2

x x2 x1 x0 f(x) y3 y2 y1 y0

0 0 0 0 2 0 0 1 01 0 0 1 4 0 1 0 02 0 1 0 6 0 1 1 03 0 1 1 8 1 0 0 04 1 0 0 10 1 0 1 05 1 0 1 12 1 1 0 06 1 1 0 14 1 1 1 0

Solution-2


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A coffee machine operates only after you have inserted Rs 15.The machine has a single slot that accept only Rs. 5 coins only one coin at a time. A sensor indicates to control the value ofcoin inserted. If the total amount is equal to Rs 15 the machinedispense a single cup of coffee. The given memory element isJK flip flop (Use Moor model)

A/0 B/0

D/1 C/0

In=0In=0

In=0

In=1

In=1

In=1

A= No Coin.B= Rs 5 CoinC= Rs 10 coinsD= Rs 15 Coins

Moor Machine output depends only on the current state

Example Problem-3

J K Q+

0 0 Q

0 1 0

1 0 1

1 1 Q

Q Q+ J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Solution-3


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Current State

I/P Next State O/P

Q1 Q0 C Q1+ Q0+ Z J1 K1 J0 K0

0 0 0 0 0 0 0 X 0 X

0 0 1 0 1 0 0 X 1 X

0 1 0 0 1 0 0 X X 0

0 1 1 1 0 0 1 X X 1

1 0 0 1 0 0 X 0 0 X

1 0 1 1 1 0 X 0 1 X

1 1 0 0 0 1 X 1 X 1

1 1 1 0 0 1 X 1 X 1

J0=C

K0=C+Q1J1=CQ0K1=Q0Z=Q1Q0

Solution-3

In a car security system, we usually want to connect the siren in such a way that thesiren will activate when it is triggered by one or more sensors. In addition, there will be amaster switch to turn the system on or off. Let us assume that there is a car door switchD, a vibration detector switch V, and the master switch M. We will use the conventionthat when the door is opened D = 1, otherwise, D = 0. Similarly, when the car is beingshaken, V = 1, otherwise, V = 0. Thus, we want the siren S to turn on, that is, set S = 1,when either D = 1 or V = 1, or when both D = 1and V = 1, but only for when the systemis turned on, that is, when M = 1. However, when we turn off the system, and either enteror drive the car, we do not want the siren to turn on. Hence, when M = 0, it does notmatter what values D and V have, the siren should remain off.

Example Problem-4 & Solution


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Design a code converter that converts BCD messages into Excess-3 code. The converter has four input lines carrying signals labeled w, x , y, andz, and four output lines carrying signals f1, f2, f3, and f4.



Let the sine function be sin(x), where 0 x < 1. The angle x will be described by fourbinary digits x1, x2, x3, x4, where x1 has weight 1/2 , x2 weight 1/4 , and so on. Thus,for example, to specify an angle of 45, the input x must equal 1/4 , i.e., x = 0100. Tospecify an angle of 30, x must equal 1/6 . However, it is impossible to represent thisvalue precisely with four bits; the closest possible value is 3 /16 or x = 0011.

Similarly the number z = z1z2z3z4 such that 0 z < 1, z1 has weight , z2 has weight , and so on. The sine of 30 is equal to 0.5. Hence, the output values in row x = 0011are specified to be z = 1000. Similarly, the sine of 45 is 0.707. Clearly, the closest output value would be z = 1011, which is equal to 0.6875. In a similar manner, the entire truth table is constructed.

Example Problem-6


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Solution-6



Input OutputA B C D W X Y Z0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1

Braille is a system which allows a blind person to readalphanumeric by feeling a pattern of raised dots () given inDesign a circuit that converts BCD to Braille and implement thesame PLA

Example Problem-7& Solution

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Example Problem-8 & SolutionImplement the F=acd + bcd+ab+bc using ALTERA MAX structure. Givenprogrammable switch is EPROM based and PAL contains fixed 3-wide arrayOR plane and sharable expander term of 2-wide array AND plane.(2009,2011)


Implement a sequence detector to detect an overlapping sequence 1010using PLA and D flip-flop.(2011).

Design a 1011 sequence detector using PROM and D-FF. Overlapping isallowed (2010)

Design a 0110 sequence detector using PLA and D-FF. Overlapping isallowed.(2010)

Implement 1010 overlapping sequence detector using D-FF and PLA .(2009).

Previous Semester Exam Questions

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Based on class notes problem,Implement Example problem 1 to 8 &Previous Semester Exam Questionsusing PROM PLA PAL


Lecture-05 What is an ASIC? Why ASICs? Classification of ASIC Full Custom ASIC Semi Custom ASIC Gate array based ASIC


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ASICs are silicon chips that have been designed fora specific application.

An ASIC is NOT software programmable toperform different tasks.

ICs that are not ASICs are :DRAM, SRAM

ICs which are ASICs: Baseband processor in

mobile phone Chipsets in PCs MPEG encoders/ decoders

Silicon Die

What is an ASIC?


Why ASICs?Design Requirements

Technology-driven: Greater Complexity Increased Performance Higher Density Lower Power Dissipation

Market-driven: Shorter Time-to-Market (TTM) Cheaper with the competition


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ASICs are fabricated on a circular silicon wafer.The fabrication process remains the same, butthe architecture makes ASICs to be divided intotypes.


Classification of ASICs

ASIC

Full Custom ASICs

Semi Custom ASICs

Cell Based (CBIC)

MASK gate array


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When engineers have a specific application to bedesigned and they are bothered about the performance,speed, power and cost, they go for designing Full CustomASIC.

The circuit is partitioned into a collection of sub-circuitsaccording to some criteria such as functionality. Whichare laid out specifically for one chip.

Every transistor is designed and drawn by hand. Typically only way to design analog portions of ASICs. Usually used for layout of microprocessors.

Full-custom design is very time consuming; thus themethod is inappropriate for very large circuits, unlessperformance is of utmost importance

Full Custom ASIC


Full Custom ASIC

Actual 0.35 full-custom layout

0.35 is thechannel lengthof smallestMOS transistor


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Semi Custom ASIC A semi-custom ASIC, also known as a cell-based ASIC,

uses pre-designed logic cells (AND gates, OR gates,Multiplexers, Flip-flops etc.) known as standard cells.

Simpler than full-custom design.

Only the placement of the standard cells and theinterconnection is done in a semi-custom ASIC.However, the standard cells can be placed anywhere onthe silicon die.

Possibly megacells , megafunctions , full-custom blocks , system-level macros( SLMs ), fixed blocks , cores , or Functional Standard Blocks ( FSBs ). Eg. Microprocessor, multiplier, etc.


Semi Custom ASIC All mask layers are customized - transistors and

interconnect Automated buffer sizing, placement and routing

Custom blocks can be embedded Manufacturing lead time is about eight weeks.

Layout of the standard CellSemicustom ASIC


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Semi Custom ASIC


Feedthrough-It is a piece of metal that isused to pass a signal through a cell.

Spacer cells-The width of each standardcell is adjusted so that they will be alignedusing spacer cells

Row end cell - The power buses areconnected to additional vertical rails usingrow end cell

Power cells-If the row of standard cells arelong then vertical power rails can also berun through metal 2 through the cell rowusing special power cells

Semi Custom ASIC


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Gate-Array Based ASICs In a gate-array-based ASIC, the transistors are predefined on the

silicon wafer. The predefined pattern of transistors is called the base array. The smallest element that is replicated to make the base array is

called the base or primitive cell. The top level interconnect between the transistors is defined by the

designer in custom masks - Masked Gate Array (MGA) Design is performed by connecting predesigned and characterized

logic cells from a library (macros). After validation, automatic placement and routing are typically used

to convert the macro-based design into a layout on the ASIC usingprimitive cells.

Types of MGAs: Channeled Gate Array Channelless Gate Array Structured Gate Array


Gate-Array Based ASICsChanneled Gate Array

Only the interconnect is customized. The interconnect uses predefined

spaces between rows of base cells. Manufacturing lead time is between

two days and two weeks.

Channelless Gate Array There are no predefined areas set

aside for routing, routing is over the top of the gate-array devices.

Achievable logic density is higher than for channeled gate arrays.

Manufacturing lead time is between two days and two weeks.

Channel gate-array die

Sea-Of-Gates (SOG) array die


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Gate-Array Based ASICsStructured Gate Array

Only the interconnect is customized

Custom blocks (the same for each design) can be embedded

These can be complete blocks such as a processor or memory array, or

An array of different base cells better suited to implementing a specific function

Manufacturing lead time is between two days and two weeks.

Gate array die with embedded block


Useful Definition:

1. Standard Parts: Some digital ICs and its analogcounterparts (analog/digital converters) are standard partsor ICs. Designers can use it from the data book or buy itfrom distributers and They can use it for differentmicroelectronics systems.

2. Glue Logic: Function implementation using standard ICsand then implementation of remaining function with one ortwo custom ICs.

3. Application Specific Standard Products (ASSPs): TheIC that might or might not considered as an ASIC are thecontroller chip for a PC, it is used for an specific applicationbut sold to many different vendors


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A Cell Based ASIC is using AND gate as standard Cells andtwo 2 to 4 decoder as fixed block. Implement a 4 to 16 decoder.

Example Problem-09


Implement the sum of fulladder using Mask Gate Array ASICs.Consider the base cell of 2:1 MUX and in one base array only 3base cells are fabricated. Show the customization steps beforeand after defining the Mask. (2010)


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Implement the difference of fullsubtractor using Mask Gate ArrayASICs. Consider the base cell of NAND gate (2-input) and in onebase array only 3 base cells are fabricated. Show thecustomization steps before and after defining the Mask.(2009)



ASIC Applications The application field for ASICs could, in theory, be

considered endless. Here are a few applications : Aerospace subsystems and sensors Wireless communication systems Medical instrumentation Telecommunications products Consumer electronics, CDs, digital synthesizers, mini-

discs Computer products, graphics cards, MPEG

technology. Etc.

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ASIC Design Flow

End Sem. 2008, 2010

Ref

er A

SIC

by

M J

Sm

ith fo

r Exp

lana

tion


http://iroi.seu.edu.cn/books/asics/Book2/CH07/CH07.1.htm#pgfId=1300

Link for ASIC By M. J. Smith

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Field Programmable Gate Array(FPGA)

One step above the PLD in complexity. It is usuallylarge and more complex than PLD.

The word Field in the name refers to the ability of thegate array to be programmed for a particular functionby the user instead of by the manufacturer of thedevice. In other word device can be programmed onthe field or site.

The word Array is used to denote a series of columnsand rows of the gates that can be configured by theend user.


Symmetrical Array

LB

LB LB

LB

LB

LB

LB LB LB

Row-based

Sea-of-Gates

LB

LB LB

LB

LB

LBLB

LB LB

LB

LB LB LBLB LB

Hierarchical (CPLD)

PLD

PLD

PLD

PLD

PLD

PLD

PLD

PLD

FPGA Architectures LB

Logi

c Bl

ock

also

cal

led

CLB

(Con

figur

able

Log

ic B

lock

)

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Company General Architecture

Logic Block Type Programming

TechnologyACTEL Row based Mux Based Anti-fuseXilinx Symmetric

ArrayLook-Up Table(LUT) Static RAM

Altera Hierarchical PLD

PLD Block EPROM

Algorotronix Sea-of-gates Mux and basic gates Static RAM

AMD Hierarchical PLD

PLD Block EEPROM

Features of commercially available FPGAs


Shannons Expansion Theorem

Using Shannons Expansion Theorem we expand the Boolean F in terms of Boolean variable A

F=A.F(A=1) + A.F(A=0)

Example

F=AB+ABC+ABCF=A(BC)+A(B+BC)

OR,F=B(A+AC)+B(AC)

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Shannons Expansion Theorem


Verify the table all entries are not correct

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ACT 1 Simple Logic Module


ACT 1 Simple Logic Module Multiplexer-based logic

module. Logic functions

implemented byinterconnecting signalsfrom the routing tracks tothe data inputs and selectlines of the multiplexers.

Inputs can also be tied to alogical 1 or 0, since thesesignals are alwaysavailable in the routingchannel.

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8 Input combinational function

2-to-1 Multiplexer Y = A S + B S

A

B

S

10

2 to 1 MUX using ACT 1 Logic Module


3 input AND gate ACT 1 Logic Module

Implementation of a three-input AND gate

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SR Latch using ACT 1 Logic Module

Implementation of S-R Latch

Qnext = S + R'Q=S+RQ(S+S)

=S+RQS+RQS

Qnext = S + R'Q=S(R+R)+RQ

=SR+SR+RQ


JK Flip FlopQnext = K'Q + JQ

T Flip FlopQnext = TQ' + T'Q

Implement using ACT1 LM

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Architecture of ACTEL FPGA

The Actel ACT family interconnect scheme shown inprevious slide is similar to a channeled gate array.

The channel routing uses dedicated rectangular areasof fixed size within the chip called wiring channels (orjust channels ).

The horizontal channels run across the chip in thehorizontal direction. In the vertical direction there aresimilar vertical channels that run over the top of thebasic logic cells, the Logic Modules

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Horizontal and Vertical Channel Architecture(ACTEL)


Each track holds one wire. The capacity of a fixed wiringchannel is equal to the number of tracks it contains.Figure(previous Slide) shows a detailed view of thechannel and the connections to each Logic Moduletheinput stubs and output stubs

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Poly-Silicon Diffusion Antifuse

An antifuse is the opposite of a regular fuse. an antifuse is normally an open circuit until you force a

programming current through it (about 5 mA). In a polydiffusion antifuse the high current density causes a

large power dissipation in a small area, which melts a thininsulating dielectric between polysilicon and diffusionelectrodes and forms a thin (about 20 nm in diameter),permanent, and resistive silicon link


antifuse polysilicon ONO dielectric

n+ antifuse diffusion

2

Figure shows a polydiffusion antifusewith an oxidenitrideoxide ( ONO )dielectric sandwich of: silicon dioxide(SiO 2 ) grown over the n -type antifusediffusion, a silicon nitride (Si 3 N 4 ) layer,and another thin SiO 2 layer.

The layered ONO dielectric results in atighter spread of blown antifuseresistance values than using a single-oxide dielectric.

The effective electrical thickness isequivalent to 10nm of SiO 2 (Si 3 N 4has a higher dielectric constant thanSiO 2 , so the actual thickness is lessthan 10 nm)

Poly-Silicon Diffusion Antifuse

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Metal-Metal Antifuse

Figure shows a QuickLogic metalmetal antifuse ( ViaLink ) The link is an alloy of tungsten, titanium, and silicon with a bulk

resistance of about 500 cm.

Advantages Connections to a metalmetal antifuse are direct to

metalthe wiring layers. Connections from a polydiffusion antifuse to the wiring layers require extra space and create additional parasitic capacitance.

Direct connection to the low-resistance metal layers makes it easier to use larger programming currents to reduce the antifuse resistance

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Universal Logic Gate: Multiplexer

NOT OR AND

4-to-1 Multiplexer Y = AS0S1 + BS0S1 + CS0S1 + DS0S1 Correction

required

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ACT 2 and ACT 3 Logic Modules The C-Module for combinational logic Actel introduced S-Modules (sequential) which basically

add a flip-flop to the MUX based C-Module ACT 2 S-Module ACT 3 S-Module


ACT 2 Logic Module: C-Mod

8-input combinational function

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ACT 2 Logic Module: C-Mod

Example of a Logic Function Implemented with the Combinatorial Logic Module


ACT 3 Logic Module: S-Mod

Sequential Logic Module

Up to 7-input function plus D-type flip-flop with clear

The storage element can be either a register or a latch. It can also be

bypassed so the logic module can be used as a Combinatorial Logic Module

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Transparent Latch

Transparent Latch connects the input to the output.1. If we apply high signal to select line and input is equal to output then

it is transparent high latch.2. If we apply low signal to select line and input is equal to output then it

is transparent Low latch.


ACT 2 and ACT 3 Logic Modules The equivalent circuit of the SE

(sequential element)

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Case 1C2=0, C1=1 and Clr=1Transparent Low Latch.

Case 2C2=CLK, C1=0 and Clr=1Positive edge triggered


Xilinx 3000 series FPGA

Xilinx XC3020 CLB is basic building block 64 Configurable Logic Block. 64 input output interface Block

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Xilinx 3000 series FPGA CLB


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Flip-flops with Clock Enable


Xilinx 3000 series FPGA Mode1. FG Mode

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2. F Mode


3. FGM Mode

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(a) Circuit for a two-input LUT

x 1

x 2

f

0/1

0/1

0/1

0/1

0 0 1 1

0 1 0 1

1 0 0 1

x 1 x 2

(b) f 1 x 1 x 2 x 1 x 2 + =

f 1

(c) Storage cell contents in the LUT

x 1

x 2

1

0

0

1

f 1

A Two-Input Lookup TableLUTs can be implemented using MUXsWe do not normally care about the implementation, just the functioning

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f

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

x 2

x 3

x 1

A Three-Input LUT

A simple extension of the two-input LUT leads to the figure at rightAgain, at this point we are interested in function and not form


Look-Up Table(LUT)

Address Decoder

SRAM Cells

Mux-Tree

Input Output

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can program to bypass the FF

Out1

D Q

Clock

Select

Flip-flop In1 In2 In3 LUT In4

can program to bypass the FF

Out2

D Q

Clock

Select

Flip-flop In1 In2 In3 LUT In4

Inclusion of a Flip-Flop with a LUTA Flip-Flop can be selected for inclusion or notLatches the LUT output


Implement the following function with Xilinx CLB

1. F= xy+z;2. Y= ab+c3. Z=abc;4. G=F+YZ

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In Fig Q1A implement the following function using respective blocks F1= (ABCDE) F2= (ACD+BCD+AB+BC) F3= F1.F2 i. Find the no. of CLBs and LUTs required to implement F3 ii. Show the SRAM contents of Xilinx XC 3000. iii. Draw the entire layout for ACT-2, PAL(three wide OR gate) and

Xilinx- XC3000 with proper routing between different blocks.


Programmable InterconnectGeneral-purpose Interconnects

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Direct Interconnects Between Adjacent CLBs


Vertical and Horizontal Long Lines

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Uses of Tristate Buffers


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Configuration Memory Cell(SRAM)

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Altera Complex Programmable Logic Device



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Altera Complex Programmable Logic DeviceMacrocell for EMP7032, 7064, and 7096 Devices



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Sharable Expanders




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Parallel Expanders



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EPROM

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Programmable I/O cells

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DC Output


DC Output

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AC Output


DC Input

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DC Input


DC InputNoise Margin

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DC InputNoise Margin


AC InputMetastability

ddhdl ppt

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