ddr controller
TRANSCRIPT
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An introduction to SDRA
and memory controller
Benny kesson
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Presentation outline DRAM history and evolution SDRAM scheduling basics
Memory efficiency Memory controller overview
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DRAM history DRAM was patented in 1968 by Denn Significantly cheaper than SRAM .
1 transistor and 1 capacitor vs. 6 transisto
A bit is represented by a high or low chargcapacitor.
Significantly slower than SRAM. SRAM used for on-chip memory like cach
scratchpads. DRAM is off-chip.
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The DRAM evolution
There has been multiple improvementDRAM design in the past ten years. A clock signal was added making the des
synchronous (SDRAM). The data bus transfers data on both risingfalling edge of the clock (DDR SDRAM).
Second generation of DDR memory (DDRscales to higher clock frequencies.
DDR3 is currently being standardized by J
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Presentation outline DRAM history and evolution SDRAM scheduling basics
Memory efficiency Memory controller overview
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Multi-bank architectur SDRAMs have a multi-bank architecture and is
in banks, rows and columns.
Many chips are combined on a memory module
the word width. This is called the memory config
Typical figures:
4 8 banks
16K rows / bank
1024 columns / row
4 16 bits / column
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Nave memory access
The requested row isactivatedand copied to therow buffer of thecorresponding bank.
Readand/or writeburstsare issued to the activerow.
The row is prechargedandstored back into thememory array.
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Refresh The capacitor is leaking and needs to be
periodically refreshed in order not to loos All banks must be precharged when a ref
command is issued. A DDR2 memory needes to be refreshedevery 64 ms.
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SDRAM command summ
Start a refresh operationREFRefresh
Close a row in a particular baPREPrechargeInitiate a write burst to an actWRWrite
Initiate a read burst to an actRDRead
Activate a row in a particular ACTActivate
Ignores all inputsNOPNo operation
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Pipelined memory acces
The SDRAM interface has a separate and command bus.
When data is transferred to or from a b
other banks are activated and prechar(bank preparation). Pipelining memory accesses increase
efficiency and throughput.
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Presentation outline DRAM history and evolution SDRAM scheduling basics
Memory efficiency Memory controller overview
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Memory efficiency Memory efficiency is the fraction between
amount of clock cycles when data is transand the total amount of clock cycles.
Five contributions to memory efficiency a Bank conflict efficiency Refresh efficiency
Data efficiency Read/write efficiency Command conflict efficiency
cyclestotal
cyclestransfer
efficiency _
_=
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Timing behaviour Delays are required between SDRAM co This limits the efficiency of pipelined acce
2ACT to ACT (diff. bank)
2WR to RD turn-around
3ACT to RD/WR
12ACT to ACT (same bank)
9ACT to PRE
CyclesCommand delay
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Bank conflict efficienc Bank conflicts occur when bank preparation fails
the requested row in a bank. This occurs due to the timing constraints of the m
Consider two consecutive bursts to different rows in th
The ACT to ACT delay for a bank is 12 cycles, which clow efficiency. Bank conflict efficiency is highly traffic dependent.
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Refresh efficiency
No data can be transfered when the memoryrefreshed.
Recall that memory needs to be refreshed ev
ms. With 8192 rows this means that a row shrefreshed, on average, every 7.8 s. A refresh command executes in 75 ns on a D
400 256 Mb device. This corresponds to rougof the time.
Refresh efficiency is independent of traffic.
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Data efficiency
A memory burst can access segments of theprogrammed burst size. This causes problemalignment.
If the requested data is poorly aligned an extsegment, and thus unrequested data, have tfetched.
The efficiency loss grows with smaller requebigger burst sizes. Alignment depends on data format, compiler
technology etc.
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Read / write efficiency
It takes time to reverse the direction ofdata bus. Read to write switch costs 2 cycles.
Write to read switch costs 4 cycles. Extra NOPs inserted between requests.
Switch frequency dependent on traffic
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Command conflict efficien
Command bus uses single data rate. Congestion can occur on command bu
Precharge and activate commands may n
be issued simultaneously. Problem depends on traffic and grows
smaller burst sizes. Command efficiency is generally quite
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Presentation outline DRAM history and evolution SDRAM scheduling basics
Memory efficiency Memory controller overview
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A general memory contro A general memory controller consists of two parts. The front-end:
buffers requests and responses. provides an interface to the rest of the system. is independent of the memory type.
The back-end: provides an interface towards the target memory. is dependent on the memory type.
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Functional blocks A general memory controller consists of four
functional blocks Memory mapping Arbiter
Command generator Data path
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Memory mapping
The memory map decodes a memory addres(bank, row, column). Decoding is done by slicing the address.
Different maps affect the memory access pa Bank sequential access Bank interleaving
Impacts bank conflict efficiency.
Bank interleavingBank sequential access
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Arbiter
The arbiter chooses the order in whichrequests access memory. Potentially multiple layers of arbitration.
An arbiter can have many different pro High memory efficiency Predictable Fast Fair
Flexible Some properties are contradictive and
being traded in arbiter design.
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Command generator
Generates the commands for the memory. Customized for a particular memory
generation. Parameterized to handle different ti
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Controller designs Two directions in controller design
Static memory controllers Dynamic memory controllers
We will look into how these address thinteresting memory controller prope
Efficiency
Predictability Flexibili
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Static memory controlle Schedule is created at design-tim
Traffic must be well-known and spe A fixed schedule is not flexible.
Computing schedules is not possiblfor large systems.
Allocated bandwidth, worst-case latand memory efficiency can be deriv
the schedule. Static controllers are predictable!
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Dynamic memory contro Dynamic memory controllers
schedule requests in run-time. are flexible.
Clever tricks: Schedule refresh when it does not
interfere.
Reorder bursts to minimize bank co Prefer read after read and write afte
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Dynamic memory contro Dynamic arbitration
allows diverse service to unpredictatraffic.
provides good average-cases. are very difficult to predict.
The schedule is not known in adv
can provide statistical guarantees bon simulation. memory efficiency is difficult to calc
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Memory controller summ
Efficiency
Predictability Flexibility
Staticcontroller design
Dy
contro
Static memory controllersare found in critical
systems with well-known
traffic.
Dynamic controllers ageneral pur
soft-real timwith unpre
traff
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