ddr timing cookbook v2 - intel · source synchronous ddr interfaces are no exception. this document...

Reference Document

Source-Synchronous DDR IO

Timing Constraints Cookbook

Written by David Olsen, 12/17/2010

Copyright © Altera Corporation, 2010

3

Disclaimer

The following document is intended to provide guidance on how to constrain double-data rate interfaces in Altera

FPGAs when Timing Constraints are not provided for you. For Altera’s double data rate memory controller IP, for

instance, timing constraints are provided for you, and those scripts should always be used.

This material was written to complement the Altera training classes available through www.altera.com.

The Quartus II Software Design Series: Timing Analysis

http://www.altera.com/education/training/courses/IDSW120

Advanced Timing Analysis with TimeQuest

http://www.altera.com/education/training/courses/IDSW125

This document provides TimeQuest commands to constrain a specific design referred to in the document. Please be

advised that these constraints will very likely need to be modified to work with your own design. Do not attempt to

constrain your design without thoroughly understanding its configuration, and please do not attempt to copy and

paste these commands directly, expecting them to work right off the bat. You must understand your design and

make appropriate modifications to these constraints in order to be assured of success.

Furthermore, these design examples may only be used within Altera Corporation devices and remain the property of

Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties,

representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation,

warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed.

Altera expressly does not recommend, suggest, or require that these examples be used in combination with any

other product not provided by Altera.

5

Table of Contents:

1.0 Executive Summary ....................................................................................................................................... 7

2.0 Document Organization ................................................................................................................................. 7

3.0 Timing Scenarios and Waveforms ................................................................................................................. 9

3.1 Clock / Data Alignment Combinations: ............................................................................................................. 9

4.0 Source-Synchronous DDR Input Timing Analysis ......................................................................................... 12

4.1 Source-Synchronous DDR Output Timing Analysis ......................................................................................... 15

5.0 Datasheet Timing Information and SDC System Parameters ...................................................................... 18

5.1 SDC Parameters for All Clock/Data Alignment Configurations and Datasheet Options ................................. 19

5.2 Input and Output Delay Calculations Given Various Datasheet Information ................................................. 20

6.0 Timing Constraints for all 16 Input and Output Configurations .................................................................. 21

6.1 Timing Constraints for Input/Output Configuration CCSS .............................................................................. 22

6.1.1 Example Timing Reports for Input/Output Configuration CCSS ............................................................. 24

6.2 Timing Constraints for Input/Output Configuration CCSO ............................................................................. 26

6.3 Timing Constraints for Input/Output Configuration CCOS ............................................................................. 28

6.3 Timing Constraints for Input/Output Configuration CCOS ............................................................................. 28

6.4 Timing Constraints for Input/Output Configuration CCOO ............................................................................ 30

6.4 Timing Constraints for Input/Output Configuration CCOO ............................................................................ 30

6.5 Timing Constraints for Input/Output Configuration CESS .............................................................................. 32

6.5 Timing Constraints for Input/Output Configuration CESS .............................................................................. 32



6.7 Timing Constraints for Input/Output Configuration CEOS ............................................................................. 36

6.7 Timing Constraints for Input/Output Configuration CEOS ............................................................................. 36

6.8 Timing Constraints for Input/Output Configuration CEOO ............................................................................ 38

6.8 Timing Constraints for Input/Output Configuration CEOO ............................................................................ 38

6.9 Timing Constraints for Input/Output Configuration ECSS .............................................................................. 40

6.9 Timing Constraints for Input/Output Configuration ECSS .............................................................................. 40

6.10 Timing Constraints for Input/Output Configuration ECSO ............................................................................. 42

6.10 Timing Constraints for Input/Output Configuration ECSO ............................................................................. 42

6.11 Timing Constraints for Input/Output Configuration ECOS ............................................................................. 44

6.11 Timing Constraints for Input/Output Configuration ECOS ............................................................................. 44

6.12 Timing Constraints for Input/Output Configuration ECOO ............................................................................ 46

6.12 Timing Constraints for Input/Output Configuration ECOO ............................................................................ 46

6.13 Timing Constraints for Input/Output Configuration EESS .............................................................................. 48

6


6.14 Timing Constraints for Input/Output Configuration EESO ............................................................................. 50

6.14 Timing Constraints for Input/Output Configuration EESO ............................................................................. 50

6.15 Timing Constraints for Input/Output Configuration EEOS ............................................................................. 52

6.15 Timing Constraints for Input/Output Configuration EEOS ............................................................................. 52



Appendix ................................................................................................................................................................. 56

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1.0 Executive Summary

The objective of this guide is to provide “recipes” to construct TimeQuest timing constraints for a typical source

synchronous double-data rate interface, given a number of different input and output configurations. It shows the

SDC commands required to deal with situations where data is launched and latched on same-edge clocks, for

instance, and where data is launched and latched on opposite clock edges. It also shows you how to deal with

situations where the clock and data are either center-aligned or edge-aligned. The guide also describes the formulas

and timing exceptions needed to fully constrain a source synchronous DDR design, given a variety of types of data

sheet specifications.

It is important to remember that there is usually more than one valid way to perform static timing analysis on any

design. Source synchronous DDR interfaces are no exception. This document just presents one straight-forward,

commonly-applied methodology that you can use on the reference designs provided or modify to work on your own

designs. The actual hardware and timing scripts referenced in this guide are available with this document and can

be used for practice. Please search the Altera Wiki for: DDR_Timing_Cookbook_designs.zip

Reminder: For Altera Memory Controller IP, please use the Timing Constraints provided with the IP!

2.0 Document Organization

As an FPGA designer, you may be expected to constrain your design given a number of different starting points. The

FPGA inputs, for example, can be constrained using either the tCO specification of the upstream ASSP, the

setup/hold requirements of the FPGA, or the ASSP’s clock/data output skew specification. Likewise, you may have

to constrain the FPGA outputs given either the setup/hold requirements of the downstream ASSP or the ASSP’s

clock/data input skew given all of the different input clock/data configurations. Multiplying these combinations

together, this equates to 4x3=12 different ways to constrain the inputs and 12x4x2=96 different ways to constrain

the outputs because output constraints are tied to the input constraints. This Application Note teaches you how to

build constraints for all such situations and hopefully demystifies the process. Fortunately, there are macros

available, like “derive_pll_clocks,” which greatly simplifies the process.

FPGA Design:

Design Details

- Input and Output DDIO blocks used for data input and output (through minimal internal FPGA Logic)

- Input and output PLLs used for phase shifting internal clocking

- Registered transmit clock through DDIO output block

Internal

FPGA

Logic

8

Throughout this document, Tcl parameters will be used to simplify and to make explicit the constraints that are

being set. These same Tcl parameters are used in the design files and timing script mentioned previously. Unlike

Application Note 433 (which is also recommended reading for anyone trying to constrain a source synchronous

interface) this guide does not address the theory behind these constra

recipes that you can under various circuit architectures.

Input Clock and Data Conditions:

Input Clock/Data Clock Transfer

(a) Center-Aligned same-edge

(b) Center-Aligned opposite-edge

(c) Edge-Aligned same-edge

(d) Edge-Aligned opposite-edge

Given ASSP tco, FPGA tsu/th, or ASSP skew

Output Clock and Data Conditions:

Output Clock/Data Clock Transfer

Center-Aligned same-edge




Center-Aligned opp-edge




Edge-Aligned same-edge




Edge-Aligned opp-edge




Given FPGA tsu/th or ASSP skew


are used in the design files and timing script mentioned previously. Unlike


interface) this guide does not address the theory behind these constraints. Rather, it just presents a series of

recipes that you can under various circuit architectures.

Given Input Condition (above)

(a)

(b)

(c)

(d)

(a)

(b)

(c)

(d)

(a)

(b)

(c)

(d)

(a)

(b)

(c)

(d) FPGA Output Interface


are used in the design files and timing script mentioned previously. Unlike


ints. Rather, it just presents a series of

FPGA Input Interface

9

3.0 Timing Scenarios and Waveforms

In this section, the timing diagrams for sixteen different

with a 4-letter acronym for convenience

connected to a single ASSP on the input and output side. The relevant clocks and

3.1 Clock / Data Alignment Combinations:

Input Configuration:

Center-Aligned same-edge transition


Center-Aligned opp-edge transition






Edge-Aligned same-edge transition


Edge-Aligned opp-edge transition






Timing Scenarios and Waveforms

sixteen different input and output configurations are presented

letter acronym for convenience. The timing diagrams relate to the following system, where an FPGA is

connected to a single ASSP on the input and output side. The relevant clocks and data signals highlighted below.

Data Alignment Combinations:

Output Configuration:

transition Center-Aligned same-edge transition

transition Center-Aligned opp-edge transition



transition Edge-Aligned same-edge transition

transition Edge-Aligned opp-edge transition











are presented and labeled

to the following system, where an FPGA is

data signals highlighted below.

Label

CCSS

CCSO

CCOS

CCOO

CESS

CESO

CEOS

CEOO

ECSS

ECSO

ECOS

ECOO

EESS

EESO

EEOS

EEOO

10

Timing Waveforms:

Legend: “WXYZ” � W=Input Alignment(C or E), X=Output Alignment(C or E), Y=Input Edge Transfer(S or O), Z=Output Edge Transfer(S or O)

“C”=Center,”E”=Edge, “S”=Same, “O”=Opposite

vir_clk_in vir_clk_in

rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data


rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data


rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data


rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data

CCOS CEOS

CCOO CEOO

CCSS CESS

CCSO CESO

11

Timing Waveforms (cont.):

Legend: “WXYZ” �� W=Input Alignment(C or E), X=Output Alignment(C or E), Y=Input Edge Transfer(S or O), Z=Output Edge Transfer(S or O)

“C”=Center,”E”=Edge, “S”=Same, “O”=Opposite


rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data


rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data


rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data


rx_clk rx_clk

rx_data rx_data

rx_pll[0] rx_pll[0]

clk clk

tx_pll[0] tx_pll[0]

tx_pll[1] tx_pll[1]

tx_clk tx_clk

tx_data tx_data

ECOS EEOS

ECOO EEOO

ECSS EESS

ECSO EESO

12

4.0 Source-Synchronous DDR Input Timing Analysis

Methodology

• Create a virtual clock for input delay constraints

• Create a base clock on the input clock port

• Specify input delays relative to the virtual clock

o Use appropriate formula for the data you are

• Adjust default setup/hold relationships (if appropriate)

• Duplicate input delays to constrain data for falling clock edge

o Add -clock_fall and -add_delay

• Deal with any other exceptions, as required

SDC Input Delay Constraint Formulas (excluding timing exception

set_input_delay -clock [get_clocks vir_clk_in] set_input_delay -clock [get_clocks vir_clk_in] set_input_delay -clock [get_clocks vir_clk_in] [get_ports data_in*] -add_delayset_input_delay -clock [get_clocks vir_clk_in] [get_ports data_in*] -add_delay

Delay Formulas:

Synchronous DDR Input Timing Analysis

Create a virtual clock for input delay constraints

Create a base clock on the input clock port

Specify input delays relative to the virtual clock

Use appropriate formula for the data you are given

Adjust default setup/hold relationships (if appropriate)

Duplicate input delays to constrain data for falling clock edge

add_delay options

Deal with any other exceptions, as required

(excluding timing exceptions):

clock [get_clocks vir_clk_in] -max <ip_delay_max> [get_ports data_in*] clock [get_clocks vir_clk_in] -min <ip_delay_min> [get_ports data_in*] clock [get_clocks vir_clk_in] -clock_fall -max <ip_delay_max>

add_delay clock [get_clocks vir_clk_in] -clock_fall -min <ip_delay_min>

add_delay

[get_ports data_in*] [get_ports data_in*]

<ip_delay_max> \

<ip_delay_min> \

13

Timing Exceptions for Source-Synchronous DDR Input

Center-Aligned Input, Same-Edge Transfer

set_false_path -setup -rise_from [get_clocks vir_clk

set_false_path -setup -fall_from [get_clocks vir_clk_in]

set_false_path -hold -rise_from [get_clocks vir_clk_in]

set_false_path -hold -fall_from [get_clocks vir_clk_in]

Edge-Aligned Input, Same-Edge Transfer

set_false_path -setup -fall_from [get_clo

set_false_path -setup -rise_from [get_clocks vir_clk_in]



Synchronous DDR Input Delay Constraints:

Edge Transfer

rise_from [get_clocks vir_clk_in] -fall_to [get_clocks rx_data_clk

fall_from [get_clocks vir_clk_in] -rise_to [get_clocks rx_data_clk

rise_from [get_clocks vir_clk_in] -rise_to [get_clocks rx_data_clk

fall_from [get_clocks vir_clk_in] -fall_to [get_clocks rx_data_clk

Edge Transfer





fall_to [get_clocks rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

14

Center-Aligned Input, Opposite-Edge Transfer





Edge-Aligned Input, Opposite-Edge Transfer



set_false_path –hold -fall_from [get_clocks vir_clk_in]


Edge Transfer





Edge Transfer




rise_from [get_clocks vir_clk_in] -fall_to [get_clocks rx_data_cl

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

rx_data_clk]

15

4.1 Source-Synchronous DDR Output Timing Analysis

Methodology:

• Create a generated clock on the output clock port

o Accounts for delay to output clock port

• Specify output delays relative to the generated clock

• Adjust default setup/hold relationships (if

• Duplicate output delays to constrain data for falling clock edge

o Add -clock_fall and -add_delay

• Deal with any other exceptions as required

SDC Output Delay Constraint Formulas (excluding timing exceptions)

set_output_delay -clock [get_clocks clk_out] set_output_delay -clock [get_clocks clk_out] set_output_delay -clock [get_clocks clk_out] [get_ports data_out*] -add_delay set_output_delay -clock [get_clocks clk_out] [get_ports data_out*] -add_delay

Delay Formulas:

Synchronous DDR Output Timing Analysis

Create a generated clock on the output clock port

Accounts for delay to output clock port

Specify output delays relative to the generated clock

Adjust default setup/hold relationships (if necessary)

Duplicate output delays to constrain data for falling clock edge

add_delay options

exceptions as required

(excluding timing exceptions):

clocks clk_out] -max <op_max_delay> [get_ports data_out*]clock [get_clocks clk_out] -min <op_min_delay> [get_ports data_out*]clock [get_clocks clk_out] -clock_fall –max <op_max_delay>

add_delay clock [get_clocks clk_out] -clock_fall -min <op_min_delay>

add_delay

[get_ports data_out*] [get_ports data_out*] <op_max_delay> \

<op_min_delay> \

16

Timing Exceptions for Source-Synchronous DDR Out

Center-Aligned Output, Same-Edge Transfer

set_false_path -setup -rise_from [get_clocks

set_false_path -setup -fall_from [get_clocks

set_false_path -hold -rise_from [get_clocks

set_false_path -hold -fall_from [get_clocks

set_false_path -from [get_pins {tx_pll|altp

Edge-Aligned Output, Same-Edge Transfer

set_false_path -setup -rise_from [get

set_false_path -setup -fall_from [get




set_multicycle_path -setup -end 0


Synchronous DDR Output Delay Constraints:

Edge Transfer

rise_from [get_clocks tx_data_clk] -fall_to [get_clocks tx_clk]

fall_from [get_clocks tx_data_clk] -rise_to [get_clocks tx_clk]

rise_from [get_clocks tx_data_clk] -rise_to [get_clocks tx_clk]

fall_from [get_clocks tx_data_clk] -fall_to [get_clocks tx_clk]

from [get_pins {tx_pll|altpll_component|pll|clk[1]}] -to [get_ports {clk_out}]

Edge Transfer



[get_clocks tx_data_clk] -rise_to [get_clocks tx_clk]



end 0 -rise_from [get_clocks tx_data_clk] -rise_to [get_clocks

end 0 -fall_from [get_clocks tx_data_clk] -fall_to [get_clocks

to [get_ports {clk_out}]

]

]

]


rise_to [get_clocks tx_clk]

fall_to [get_clocks tx_clk]

17

Center-Aligned Output, Opposite-Edge Transfer






Edge-Aligned Output, Opposite-Edge Transfer








Edge Transfer






Edge Transfer






end 0 -rise_from [get_clocks tx_data_clk] -fall_to [get_clocks

end 0 -fall_from [get_clocks tx_data_clk] -rise_to [get_clocks

]


]


_to [get_clocks tx_clk]

_to [get_clocks tx_clk]

18

5.0 Datasheet Timing Information and SDC System Parameters

Typical datasheet timing parameters for the

presented with enough data below to constrain input timing in three different ways and to constain output timing

two ways. This gives you the opportunity to explore all the common starting points y

Section 2.0). The Tcl definitions used to express these values are

input and output delay formulas that follow

Inputs Constraint Options: 1. ASSP tCO specification

2. FPGA setup/hold requirements

3. ASSP clock/data output skew

Center-Aligned Clock/Data:

FPGA_tSU_c = period/4 - ASSP_op_skew = 2.0 ns

FPGA_tH_c = period/4 - ASSP_op_skew = 2.0 ns

Output Constraint Options: 1. ASSP Setup/hold requirements

2. ASSP clock/data input skew

Center-Aligned Clock/Data:

ASSP_tSU_c = period/4 - ASSP_ip_skew = 0.5 ns

ASSP_tH_c = period/4 - ASSP_ip_skew = 0.5

Datasheet Timing Information and SDC System Parameters

timing parameters for the FPGA and its companion ASSP are presented below. You are

to constrain input timing in three different ways and to constain output timing

two ways. This gives you the opportunity to explore all the common starting points you might face (as described in

used to express these values are shown in Section 5.1. In order to understand

input and output delay formulas that follow in this guide, these parameter definitions should be observed

ASSP tCO specification ASSP_tCO =

ASSP_tCOmin =

FPGA setup/hold requirements (see formulas below)

ASSP clock/data output skew ASSP_op_skew =

Edge-Aligned Clock/Data:

ASSP_op_skew = 2.0 ns FPGA_tSU_e = - ASSP_op_skew =

ASSP_op_skew = 2.0 ns FPGA_tH_e = period/2 – ASSP_op_skew

ASSP Setup/hold requirements (see formulas below)

ASSP clock/data input skew ASSP_ip_skew =

Edge-Aligned Clock/Data:

= 0.5 ns ASSP_tSU_e = - ASSP_ip_skew

0.5 ns ASSP_tH_e = period/2 - ASSP_ip_skew

below. You are actually

to constrain input timing in three different ways and to constain output timing in

ou might face (as described in

In order to understand the

these parameter definitions should be observed.

= 0.5 ns

= - 0.5 ns

(see formulas below)

= 0.5 ns

ASSP_op_skew = -0.5 ns

SP_op_skew = 4.5 ns

(see formulas below)

2.0 ns

= -2.0 ns

ASSP_ip_skew = 3.0 ns

19

5.1 SDC Parameters for All Clock/Data Alignment Configurations and Datasheet Options

System Constraints and Variables Required to Capture Datasheet Information: #********************************************************************************** # System Variables / Datasheet Parameters (all times in nanoseconds) #********************************************************************************** # ASSP Transmit Clock Details: set T 10.000; # System clock period set clk_uncert 0.300; # ASSP clock uncertainty set vir_rise 0; # Rising-edge of virtual clock set vir_fall [expr $T/2 ]; # Falling-edge of virtual clock set clk_rise 0; # R-edge of input clock set clk_fall [expr $T/2.0 ]; # F-edge of input clock set rx_rise_c [expr $T/4.0 ]; # R-edge of rx_clk (center-al.) set rx_fall_c [expr $rx_rise_c+$T/2.0]; # F-edge of rx_clk (center-al.) set rx_rise_e 0; # R-edge of rx_clk (edge-al.) set rx_fall_e [expr $T/2.0]; # F-edge of rx_clk (edge-al.) # Board Traces: set dat_trc_max 0.250; # Board data trace (250 ps) set clk_trc_max 0.250; # Board clk trace (250 ps) set dat_trc_min 0.250; # set clk_trc_min 0.250; # (assume all matched lengths) # Info for FPGA Inputs: set ASSP_tCO 0.500; # ASSP tCO spec set ASSP_tCOmin -0.500; # ASSP tCOmin spec set FPGA_tSU_c 2.000; # FPGA setup rqmt. (center-al.)* set FPGA_tH_c 2.000; # FPGA hold rqmt. (center-al.) set FPGA_tSU_e -0.500; # FPGA setup rqmt. (edge-al.)** set FPGA_tH_e 4.500; # FPGA hold rqmt. (edge-al.) set ASSP_op_skew 0.5; # ASSP output skew spec. # Info for FPGA Outputs: set ASSP_tSU_c 0.5; # ASSP setup rqmt. (center-al.) set ASSP_tH_c 0.5; # ASSP hold rqmt. (center-al.) set ASSP_tSU_e -2.0; # ASSP setup rqmt. (edge-al.) set ASSP_tH_e 3.0; # ASSP hold rqmt. (edge-al.) set ASSP_ip_skew 2.0; # ASSP input skew spec.

# * ”center-al.” = “center-aligned”

# **”edge-al.” = “edge-aligned”

Reminder: These constraints are provided so that the subsequent formulas in this guide will make sense

20

5.2 Input and Output Delay Calculations Given Various Datasheet Information

As we have discussed, the way that you calculate the input delay or output delay constraint depends on the input

information given (ie. what data you have on the devices’ respective data sheets or what timing constraints have

been imposed upon you by your board designer). The following Tcl commands are taken from a generalized

constraint script (provided in the Appendix) and are included to illustrate what the numerical expressions would

look like for a variety of scenarios. They pull values from the parameter definitions described in Section 5.1: # Settings: Scenario Label: # ========= =============== # IP_setting 1 # Center-Aligned Input, ASSP tCO Rqmnts. # ---------- 2 # Center-Aligned Input, FPGA Setup & Hold # 3 # Center-Aligned Input, ASSP Output Skew # 4 # Edge-Aligned Input, ASSP tCO Rqmnts. # 5 # Edge-Aligned Input, FPGA Setup & Hold # 6 # Edge-Aligned Input, ASSP Output Skew # # OP_setting 1 # Center-Aligned Output, ASSP Setup & Hold # ---------- 2 # Center-Aligned Output, ASSP Input Skew # 3 # Edge-Aligned Output, ASSP Setup & Hold # 4 # Edge-Aligned Output, ASSP Input Skew switch -exact -- $IP_setting { 1 { # Center-Aligned Input, ASSP tCO Rqmnts. set ip_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tCOmax ] set ip_del_min [expr $dat_trc_min - $clk_trc_max + $ASSP_tCOmin ] } 2 { # Center-Aligned Input, FPGA Setup & Hold set ip_del_max [expr + $T/4.0 - $FPGA_tSU_c ] set ip_del_min [expr - $T/4.0 + $FPGA_tH_c ] } 3 { # Center-Aligned Input, ASSP Output Skew set ip_del_max [expr + $ASSP_op_skew] set ip_del_min [expr - $ASSP_op_skew] } 4 { # Edge-Aligned Input, ASSP tCO Rqmnts. set ip_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tCOmax ] set ip_del_min [expr $dat_trc_min - $clk_trc_max + $ASSP_tCOmin ] } 5 { # Edge-Aligned Input, FPGA Setup & Hold set ip_del_max [expr + (0) - $FPGA_tSU_e ] set ip_del_min [expr - $T/2.0 + $FPGA_tH_e ] } 6 { # Edge-Aligned Input, ASSP Output Skew set ip_del_max [expr $ASSP_ip_skew] set ip_del_min [expr - $ASSP_ip_skew] } }

21

#******************************************************************************************** # Output Delay Value Formulas #******************************************************************************************** # Select Output Conditions Based on Parameters Above: # switch -exact -- $OP_setting { 1 { # Center-Aligned Output, ASSP Setup & Hold set op_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tSU_c ] set op_del_min [expr $dat_trc_min - $clk_trc_max - $ASSP_tH_c ] } 2 { # Center-Aligned Output, ASSP Input Skew set op_del_max [expr $T/4 - $ASSP_ip_skew] set op_del_min [expr -$T/4 + $ASSP_ip_skew] } 3 { # Edge-Aligned Output, ASSP Setup & Hold set op_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tSU_e ] set op_del_min [expr $dat_trc_min - $clk_trc_max - $ASSP_tH_e ] } 4 { # Edge-Aligned Output, ASSP Input Skew set op_del_max [expr (0) - $ASSP_op_skew]; set op_del_min [expr (0) - $T/2 + $ASSP_op_skew]; } }

6.0 Timing Constraints for all 16 Input and Output Configurations

In Section 6, the full sets of SDC timing constraings are described for all 16 input/output configurations. In this

section, it is assumed that you have already calculated the numerical values for the delay values (as per the formulas

shown in Section 5.2), so numbers are displayed instead of mathematical expressions. Observe the use of the

derive_pll_clocks SDC macro in the constraints that follow. It greatly simplifies the process of entering

constraints as it allows you to minimize the amount of manual generated clock definitions you must create yourself.

(As a side note: if you like, you can actually rely completely on the derive_pll_clocks command for all PLL

outputs to keep them fully parameterized. In this document, however, we have added explicit definitions for

rx_data_clk and tx_data_clk just to make it easier to read the subsequent false path and multicycle path

constraints and also to report timing. This is not necessarily recommended for your own design.)

22

6.1 Timing Constraints for Input/Output Configuration CCSS

Center-aligned same-edge input transition, Center-aligned same-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 2.500 7.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}]

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#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #**************************************************************

24

6.1.1 Example Timing Reports for Input/Output Configuration CCSS

Inputs:

report_timing -from_clock { vir_clk_in } -to_clock { rx_data_clk } \ -setup -npaths 1 -detail full_path -panel_name {Report Timing}

report_timing -from_clock { vir_clk_in } -to_clock { rx_data_clk } \ -hold -npaths 1 -detail full_path -panel_name {Report Timing}

25

Outputs:

report_timing -from_clock { tx_data_clk } -to_clock { tx_clk } \ -setup -npaths 1 -detail full_path -panel_name {Report Timing}

report_timing -from_clock { tx_data_clk } -to_clock { tx_clk } \ -hold -npaths 1 -detail full_path -panel_name {Report Timing}

26

6.2 Timing Constraints for Input/Output Configuration CCSO

Center-aligned same-edge input transition, Center-aligned opposite-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 2.500 7.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}]

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#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #**************************************************************

28

6.3 Timing Constraints for Input/Output Configuration CCOS

Center-aligned opposite-edge input transition, Center-aligned same-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 7.500 12.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}]

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#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #**************************************************************

30

6.4 Timing Constraints for Input/Output Configuration CCOO

Center-aligned opposite-edge input transition, Center-aligned opposite-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 7.500 12.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}]

31

#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #**************************************************************

32

6.5 Timing Constraints for Input/Output Configuration CESS

Center-aligned same-edge input transition, Edge-aligned same-edge output transition #************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 2.500 7.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}]

33

#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0

34

6.6 Timing Constraints for Input/Output Configuration CCSO

Center-aligned same-edge input transition, Center-aligned opposite-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 2.500 7.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] #**************************************************************

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# Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0

36

6.7 Timing Constraints for Input/Output Configuration CEOS

Center-aligned opposite-edge input transition, Edge-aligned same-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 7.500 12.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}]

37

#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0

38

6.8 Timing Constraints for Input/Output Configuration CEOO

Center-aligned opposite-edge input transition, Edge-aligned opposite-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 7.500 12.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data}]

39

#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0

40

6.9 Timing Constraints for Input/Output Configuration ECSS

Edge-aligned same-edge input transition, Center-aligned same-edge output transition

#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 2.500 7.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}]

41

#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #**************************************************************

42

6.10 Timing Constraints for Input/Output Configuration ECSO


#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 2.500 7.500 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}]

43

#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #**************************************************************

44

6.11 Timing Constraints for Input/Output Configuration ECOS


#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 5.000 10.000 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data[1]}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] 0.500 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -0.500 [get_ports {tx_data*}]

45

#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #**************************************************************

46

6.12 Timing Constraints for Input/Output Configuration ECOO


#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 5.000 10.000 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data[0]}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}]

47


48

6.13 Timing Constraints for Input/Output Configuration EESS


#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] #**************************************************************

49

# Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0

50

6.14 Timing Constraints for Input/Output Configuration EESO


#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data[1]}]

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#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0

52

6.15 Timing Constraints for Input/Output Configuration EEOS


#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 5.000 10.000 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data[1]}]

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#************************************************************** # Set False Path #************************************************************** set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #************************************************************** # Set Multicycle Path #************************************************************** set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0

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6.16 Timing Constraints for Input/Output Configuration EESS


#************************************************************** # Time Information #************************************************************** set_time_format -unit ns -decimal_places 3 #************************************************************** # Create Clock #************************************************************** create_clock -name {vir_clk_in} -period 10.000 -waveform { 0.000 5.000 } create_clock -name {clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk}] create_clock -name {rx_clk} -period 10.000 -waveform { 5.000 10.000 } [get_ports {rx_clk}] #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks create_generated_clock -name {rx_data_clk} -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase 90.000 -master_clock {rx_clk} [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {data_clk} -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase -90.000 -master_clock {clk} [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add create_generated_clock -name {tx_clk} -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] -master_clock {tx_pll|altpll_component|pll|clk[1]} [get_ports {tx_clk}] #************************************************************** # Set Clock Uncertainty #************************************************************** derive_clock_uncertainty #************************************************************** # Set Input Delay #************************************************************** set_input_delay -add_delay -max -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] set_input_delay -add_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] 0.500 [get_ports {rx_data*}] set_input_delay -add_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] -0.500 [get_ports {rx_data*}] #************************************************************** # Set Output Delay #************************************************************** set_output_delay -add_delay -max -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}] set_output_delay -add_delay -max -clock_fall -clock [get_clocks {tx_clk}] -2.000 [get_ports {tx_data*}] set_output_delay -add_delay -min -clock_fall -clock [get_clocks {tx_clk}] -3.000 [get_ports {tx_data*}]

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56

Appendix

Universal Tcl/SDC Timing Script:

Can be configured to handle all timing scenarios discussed in this document with just six settings:

Input edges

Input configuration

Output edges

Output configuration

Receive clock phase

Transmit clock phase

*These can be set in the script (see below)

## Copyright (C) 1991-2010 Altera Corporation ## Your use of Altera Corporation's design tools, logic functions ## and other software and tools, and its AMPP partner logic ## functions, and any output files from any of the foregoing ## (including device programming or simulation files), and any ## associated documentation or information are expressly subject ## to the terms and conditions of the Altera Program License ## Subscription Agreement, Altera MegaCore Function License ## Agreement, or other applicable license agreement, including, ## without limitation, that your use is for the sole purpose of ## programming logic devices manufactured by Altera and sold by ## Altera or its authorized distributors. Please refer to the ## applicable agreement for further details. ## ## ## rev 1 written by David Olsen - 09/10/2010 ## rev 2 written by David Olsen - 12/14/2010 ## ## PLEASE SET TIMING ANALYSIS SWITCHS BELOW (see "<---") #******************************************************************************************** # Timing Analysis Switches: #******************************************************************************************** # # CONSTANTS: # ========== set same 1; # Define constant for same edge transfers set opp 0; # Define constant for opposite edge transfers # # Explanation of Setting Nomenclature: # ==================================== # VARIABLE: POSSIBLE VALUES: DESCRIPTION: # --------- ---------------- ------------ # # IP_edges: $same=1 # SAME-EDGE TXFER ON INPUT # $opp=1 # OPP-EDGE TXFER ON INPUT #

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# OP_edges: $same=1 # SAME-EDGE TXFER ON OUTPUT # $opp=1 # OPP-EDGE TXFER ON OUTPUT # # IP_setting: 1 # Center-Aligned Input, ASSP tCO Rqmnts. # 2 # Center-Aligned Input, FPGA Setup & Hold # 3 # Center-Aligned Input, ASSP Output Skew # 4 # Edge-Aligned Input, ASSP tCO Rqmnts. # 5 # Edge-Aligned Input, FPGA Setup & Hold # 6 # Edge-Aligned Input, ASSP Output Skew # # OP_setting: 1 # Center-Aligned Output, ASSP Setup & Hold # 2 # Center-Aligned Output, ASSP Input Skew # 3 # Edge-Aligned Output, ASSP Setup & Hold # 4 # Edge-Aligned Output, ASSP Input Skew # # # Settings for this Run: (Please edit to match Hardware Setup): # ---------------------- set IP_setting 1; # <--- (see above for options) set OP_setting 1; # <--- (see above for options) set IP_edges $same; # <--- (choose "same" or "opp") set OP_edges $same; # <--- (choose "same" or "opp") set rcp 0; # <--- (set "rx_data_clk" phase from PLL settings) set dcp 90; # <--- (set "data_clk" phase from PLL settings) #******************************************************************************************** # System Variables / Datasheet Parameters #******************************************************************************************** # Clock Details (general): set T 10.000; # System clock period (ns) set clk_uncert 0.000; # ASSP clock uncertainty (could set to 0.3ns) # ASSP Transmit Clock: set vir_rise 0; # Rising edge of virtual clock (ns) set vir_fall [expr $T/2.0 ]; # Falling edge of virtual clock (ns) # FPGA Input Clock: set clk_rise 0; # Rising edge of input clock set clk_fall [expr $T/2.0 ]; # Falling edge of input clock # FPGA DDR Input Clock (options): set rx_rise_cs [expr $T/4.0 ]; # Rising-edge,Center-aligned Same-edge txfer set rx_fall_cs [expr $rx_rise_cs+$T/2.0]; # Fall-edge, Center-aligned Same-edge txfer set rx_rise_co [expr 3.0/4.0*$T ]; # Rising-edge,Center-aligned Opp-edge txfer set rx_fall_co [expr 5.0/4.0*$T ]; # Fall-edge, Center-aligned Opp-edge txfer set rx_rise_es 0; # Rising-edge,Edge-aligned Same-edge txfer set rx_fall_es [expr $T/2.0]; # Fall-edge, Edge-aligned Same-edge txfer set rx_rise_eo [expr $T/2.0]; # Rising-edge,Edge-aligned Opp-edge txfer set rx_fall_eo [expr $T]; # Fall-edge, Edge-aligned Opp-edge txfer # Board Traces: set dat_trc_max 0.250; # Max Board data trace (250 ps) set clk_trc_max 0.250; # Max Board clk trace (250 ps) set dat_trc_min 0.250; # Min Board data trace (250 ps) set clk_trc_min 0.250; # Min Board clk trace (250 ps) # Data for FPGA Input Timing Constraints (3 options): set ASSP_tCOmax 0.500; # ASSP tCO spec set ASSP_tCOmin -0.500; # ASSP tCOmin spec set FPGA_tSU_c 2.000; # FPGA setup rqmt. (center-aligned) set FPGA_tH_c 2.000; # FPGA hold rqmt. (center-aligned)

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set FPGA_tSU_e -0.500; # FPGA setup rqmt. (edge-aligned) set FPGA_tH_e 4.500; # FPGA hold rqmt. (edge-aligned) set ASSP_op_skew 0.5; # ASSP output skew spec. # Info for FPGA Outputs (2 options): set ASSP_tSU_c 0.500; # ASSP setup rqmt. (center-aligned) set ASSP_tH_c 0.500; # ASSP hold rqmt. (center-aligned) set ASSP_tSU_e -2.000; # ASSP setup rqmt. (edge-aligned) set ASSP_tH_e 3.000; # ASSP hold rqmt. (edge-aligned) set ASSP_ip_skew 2.000; # ASSP input skew spec. #******************************************************************************************** # Input Delay Value Formulas #******************************************************************************************** # Select Input Conditions Based on Parameters Above: # switch -exact -- $IP_setting { 1 { # Center-Aligned Input, ASSP tCO Rqmnts. set ip_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tCOmax ] set ip_del_min [expr $dat_trc_min - $clk_trc_max + $ASSP_tCOmin ] } 2 { # Center-Aligned Input, FPGA Setup & Hold set ip_del_max [expr + $T/4.0 - $FPGA_tSU_c ] set ip_del_min [expr - $T/4.0 + $FPGA_tH_c ] } 3 { # Center-Aligned Input, ASSP Output Skew set ip_del_max [expr + $ASSP_op_skew] set ip_del_min [expr - $ASSP_op_skew] } 4 { # Edge-Aligned Input, ASSP tCO Rqmnts. set ip_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tCOmax ] set ip_del_min [expr $dat_trc_min - $clk_trc_max + $ASSP_tCOmin ] } 5 { # Edge-Aligned Input, FPGA Setup & Hold set ip_del_max [expr + (0) - $FPGA_tSU_e ] set ip_del_min [expr - $T/2.0 + $FPGA_tH_e ] } 6 { # Edge-Aligned Input, ASSP Output Skew set ip_del_max [expr $ASSP_op_skew] set ip_del_min [expr - $ASSP_op_skew] } } #******************************************************************************************** # Output Delay Value Formulas #******************************************************************************************** # Select Output Conditions Based on Parameters Above: # switch -exact -- $OP_setting { 1 { # Center-Aligned Output, ASSP Setup & Hold set op_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tSU_c ]

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set op_del_min [expr $dat_trc_min - $clk_trc_max - $ASSP_tH_c ] } 2 { # Center-Aligned Output, ASSP Input Skew set op_del_max [expr $T/4 - $ASSP_ip_skew] set op_del_min [expr -$T/4 + $ASSP_ip_skew] } 3 { # Edge-Aligned Output, ASSP Setup & Hold set op_del_max [expr $dat_trc_max - $clk_trc_min + $ASSP_tSU_e ] set op_del_min [expr $dat_trc_min - $clk_trc_max - $ASSP_tH_e ] } 4 { # Edge-Aligned Output, ASSP Input Skew set op_del_max [expr (0) - $ASSP_ip_skew]; set op_del_min [expr (0) - $T/2 + $ASSP_ip_skew]; } } #******************************************************************************************** # Time Information #******************************************************************************************** set_time_format -unit ns -decimal_places 3 #******************************************************************************************** # Create Clocks #******************************************************************************************** # Virtual clocks: create_clock -name {vir_clk_in} -period $T -waveform [ list $vir_rise $vir_fall ] # Input clocks: create_clock -name {clk} -period $T -waveform [ list $clk_rise $clk_fall ] [get_ports {clk}] if {$IP_setting < 4} {; # ie. CENTER-ALIGNED Transfer: if {$IP_edges == $same} {; # Same-edge transfer: (90 deg forward in phase) create_clock -name {rx_clk} -period $T -waveform [ list $rx_rise_cs $rx_fall_cs ] [get_ports {rx_clk}] } else { # Opp-edge transfer: (90 deg back in phase) create_clock -name {rx_clk} -period $T -waveform [ list $rx_rise_co $rx_fall_co ] [get_ports {rx_clk}] } } else {; # ie. EDGE-ALIGNED Transfer: # "rx_pll" will shift the edge appropriately, thus... if {$IP_edges == $same} {; # Same-edge transfer: (0 deg forward in phase) create_clock -name {rx_clk} -period $T -waveform [ list $rx_rise_es $rx_fall_es ] [get_ports {rx_clk}] } else { # Opp-edge transfer: (180 deg forward in phase) create_clock -name {rx_clk} -period $T -waveform [ list $rx_rise_eo $rx_fall_eo ] [get_ports {rx_clk}] } } # Derive all PLL Output clocks: derive_pll_clocks # Add "rx_data_clk" to "rx_pll[0]":

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create_generated_clock -name rx_data_clk -source [get_pins {rx_pll|altpll_component|pll|inclk[0]}] -phase $rcp [get_pins {rx_pll|altpll_component|pll|clk[0]}] -add # Add "data_clk" to "tx_pll[0]": create_generated_clock -name data_clk -source [get_pins {tx_pll|altpll_component|pll|inclk[0]}] -phase $dcp [get_pins {tx_pll|altpll_component|pll|clk[0]}] -add # Registered Clock Output create_generated_clock -source [get_pins {TX_CLK|altddio_out_component|auto_generated|ddio_outa[0]|dataout}] \ [get_ports {tx_clk}] #******************************************************************************************** # Set Clock Uncertainty <OPTIONAL> #******************************************************************************************** #set_clock_uncertainty -setup $clk_uncert ; # jitter on output bus from ASSP spec #set_clk_uncertainty -hold $clk_uncert ; # jitter on output bus from ASSP spec #******************************************************************************************** # Set Input Delay #******************************************************************************************** set_input_delay -max -clock [get_clocks {vir_clk_in}] $ip_del_max [get_ports {rx_data*}] set_input_delay -min -clock [get_clocks {vir_clk_in}] $ip_del_min [get_ports {rx_data*}] set_input_delay -max -clock_fall -clock [get_clocks {vir_clk_in}] $ip_del_max [get_ports {rx_data*}] -add_delay set_input_delay -min -clock_fall -clock [get_clocks {vir_clk_in}] $ip_del_min [get_ports {rx_data*}] -add_delay #******************************************************************************************** # Set Output Delay #******************************************************************************************** set_output_delay -max -clock [get_clocks {tx_clk}] $op_del_max [get_ports {tx_data*}] set_output_delay -min -clock [get_clocks {tx_clk}] $op_del_min [get_ports {tx_data*}] set_output_delay -max -clock_fall -clock [get_clocks {tx_clk}] $op_del_max [get_ports {tx_data*}] -add_delay set_output_delay -min -clock_fall -clock [get_clocks {tx_clk}] $op_del_min [get_ports {tx_data*}] -add_delay #******************************************************************************************** # Set False Path #******************************************************************************************** # Inputs: switch -exact -- $IP_edges \ $same { # ie. Input False Paths for Same Edge Transfers: set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}]

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set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] } \ $opp { # ie. Input False Paths for Opposite Edge Transfers: set_false_path -setup -rise_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] set_false_path -setup -fall_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -rise_from [get_clocks {vir_clk_in}] -fall_to [get_clocks {rx_data_clk}] set_false_path -hold -fall_from [get_clocks {vir_clk_in}] -rise_to [get_clocks {rx_data_clk}] } # Outputs: switch -exact -- $OP_edges \ $same { # ie. Output False Paths for Same Edge Transfers: set_false_path -setup -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] } \ $opp { # ie. Output False Paths for Opposite Edge Transfers: set_false_path -setup -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] set_false_path -setup -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] set_false_path -hold -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] } set_false_path -from [get_pins {tx_pll|altpll_component|pll|clk[0]}] -to [get_ports {tx_clk}] #******************************************************************************************** # Set Multicycle Path #******************************************************************************************** if {$OP_setting > 2} { ; # ie. Edge-Aligned if {$OP_edges == $same} { set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0 } if {$OP_edges == $opp} { set_multicycle_path -setup -end -rise_from [get_clocks {data_clk}] -fall_to [get_clocks {tx_clk}] 0 set_multicycle_path -setup -end -fall_from [get_clocks {data_clk}] -rise_to [get_clocks {tx_clk}] 0 } }

ddr timing cookbook v2 - intel · source synchronous ddr interfaces are no exception. this document...

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