ddr3 reportnew bala (1)f

8/12/2019 DDR3 ReportNEW Bala (1)f

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A Project Report on

DDR3 MEMORY CONTROLLER FOR HIGH

PERFORMANCE NETWORKING PROCESSSubmitted in partial fulfillment for the award of degree ofBACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted by

CH.BALASARASWATHI(106F1A041!

G.SUNITHA(106F1A04""!

K.RO#A(106F1A043$!

SUNITHASHARMA(106F1A043!

Under the guidance of:

Mr.M.Ramesh, M.Tech

Asst. Professor

DEPARTMENTOF

ELECTRONICS AND COMMUNICATION ENGINEERING

SAI GANAPATHI ENGINEERING COLLEGE(Affiliated to Jawaharlal Nehru technological universit. !a"inada#

$idi%ala village.Ananda&uram,'isa"ha&atnam)*++*

-+-+/


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0A1 $ANAPAT21 3N$1N33R1N$ 45663$3,$171JA6A

)*++*

73PARTM3NT 58 3634TR5N140 AN7 45MMUN14AT15N

CERTIFICATE

This is to certif that the &ro%ect wor" entitled DDR3 MEMORY

CONTROLLER FOR HIGH PERFORMANCE

NETWORKING PERFORMANCEis a 9onafide wor" carried out

at 0A1 $ANAPAT21 3N$1N33R1N$ 45663$3, $171JA6A, 9

CH.BALASARASWATHI%P1NN5.(106F1A041#G.SUNITHA,P1NN5.

(106F1A04""#K.RO#A%P1NN5.(106F1A043$#;SUNITHA

SHARMA%P1NN5.(106F1A043#. uirements for the award of degree in BACHELOR OF

TECHNOLOGY affiliated to #AWAHARLAL NEHRU

TECHNOLOGICAL UNI&ERSITY% KAKINADAduring the academic

ear -+-+/.

INTERNAL GUIDE HEAD OF THE

DEPARTMENT

Mr.M.Ramesh,M.Tech Mr.!.RAM302,M.TechAsst.Professor, Asst.Professor,

7e&t of 343 7e&t of 343

E'TERNAL E'AMINER


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DECLARATION


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ACKNOWLEDGEMENT


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CONTENTS

1. DECLARATION ..1

". ACKNOWLEDGEMENT."

3. ABSTRACT....3

4. CONTENTS....4

). LIST OF FIGURES....)

CHAPTER 1.($713!

1.INTRODUCTION

1 INTRODUCTION

1.1 DDR3 SDRAM

1." DDR3BASED LOOKUP CIRCUIT.1"

1.3 DDR3 AD&ANTAGES..13

CHAPTER "(147"8! TYPES OF MEMORY CONTROLLER

-.1TYPESOFMEMORYCONTROLLER.18 ".1.1 DDR DIGITAPULSE16

"." DDR" SDRAM..16

".3 DDR3 SDRAM..1$

".4 COMPONENTS OF DDR9S1:

".8 OTHER MEMORY TYPES.."0

".8.1 &IDEO RANDOM ACCESS MEMORY"0

".8." FLASH MEMORY."0

".8.3 SHADOW RAM.."1 ".8.4 STATIC RAM.."1

".8.8 DYNAMICRAM"1

".8.6 CACHEMEMORY"3

".8.$ CONTENT ADDRESSABLEMEMORY."4

".8. HARDWARE ASSOCIATI&EMEMORY"8

CHAPTER 3.("6740!


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DESIGN OF DDR3 SDRAM CONTROLLER 3.1 INTRODUCTION"6

3." FUNCTIONAL BLOCK DIAGRAM."$

3.".1 ADDRESS FIFO"

3."." WRITE DATA FIFO...30

3.".3 CONTROLFIFO.31

3.".4 READ DATAREGISTER31

3.3 DIFFERENT STATES OF INITIALFSM.31

3.3.IDLE.34

3.3." NOOPERATION34

3.3.3PRECHARGE..38

3.3.4AUTOREFRESH.38

3.3.8 LOAD MOD REGISTER.38

3.3.6 READ;WRITECYCLE.38

CHAPTER4..(41780!

DIFFERENT STATES OF COMMAND FSM

4.1 DIFFERENT STATES OF COMMANFSM4"

4.1.1 REFRESH CYCLE4"

4.1. ACTI&E4"

4.1. READ.43

4.1.4WRITE.44

4.1.8REFRESHCYCLE46

4.1.6 DATPATHCONTROL4$

4.1.$BANKCONTROL....4$

4.1. TIMING DIAGRAM...4$

4."AD&ANTAGES..4:

4.3DISAD&ANTAGES.80

CHAPTER 8(8176"!


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RESULTS

8.1 SIMULATION RESULT8"

8.1.1 ADDRESSFIFO83

8.1." CONTROLFIFO.83

8.1.3 WRITEDATAFIFO84

8.1.4 INITIALFSM..88

8.1.8 COMMANDFSM..86

8.1.8.1 NORMALWRITE

86

8.1.8." NORMALREAD.8$

8.1.8.3 FASTREAD8

8.1.6 DATA PATHCONTROL8:

8.1.$ TOP MODULE..60

8.1.$.1 NORMAL WRITE

OPERATION...60

8.1.$." NORMAL READ OPERATION

61

8.1.$.3 FAST READ6"

CHAPTER 6(6"768!

CONCLUSION AND FUTURESCOPE63 6.1 CONCLUSION64 6." FUTURE SCOPE68

CHAPTER $.(6676!

REFRENCES.6$


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CHAPTER (6:7$:!

APPENDI'

.1 O&ER&IEW..$0

." HISTORY BEGINNING.$"

.3 DESIGN STYLES$4

.4 &ERILOG ABSTRACTION LE&ELS$6

.8 ABOUT &ERILOG HDL$$

.6 SALIENT FUTURES OF &ERILOG..$

610T 58 81$U3R0:

81$ +.+ 77R* 07RAM81$ +.- 30T1MAT15N $RAP2

81$ +.* 2A02 4AM 655!UP 41R4U1T

81$ -.+ $RAP214A6 R3PR303NTAT15N

81$ -.- 45MPAR105N 58 77R@081$ *.+ 8UN4T15NA6 =654! 71A$RAM

81$ *.- 1N1T1A6 80M 0TAT3 71A$RAM81$ *.* PR3 42AR$3 45MMAN781$ *./ 45MMAN7 80M 0TAT3 71A$RAM

85R N5RMA6 R3A7


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81$ /.*


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a&&lications.The architecture of 77R*07RAM controller consists of

1nitialiDation fsm 4ommand fsm, data &ath , 9an" control ,cloc" counter, refresh

counter, Address 8185, command 8185 ,


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CHAPTER 1

INTRODUCTION

1. INTRODUCTION

1.1 DDR3 SDRAM@

1n electronic engineering, 77R* 07RAM or dou9ledatarate three snchronous

dnamic random access memories is a random access memor technolog used for high

9andwidth storage of the wor"ing data of a com&uter or other digital electronic

devices.77R* is &art of the 07RAM famil of technologies and is one of the man

7RAM (dnamic random access memor# im&lementations. 77R* 07RAM is an

im&rovement over its &redecessor, 77R- 07RAM.


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The &rimar 9enefit of 77R* is the a9ilit to transfer 15 data at eight times the

data rate of the memor cells it contains, thus ena9ling higher 9us rates and higher &ea"

rates than earlier memor technologies. 2owever, there is no corres&onding reduction in

latenc, which is therefore &ro&ortionall higher. 1n addition, the 77R* standard allows

for chi& ca&acities of )+- mega9its to C giga9its, effectivel ena9ling a ma?imum

memor module siDe of +H giga9tes.

The 77R* 07RAM is not ver much different from the &revious generation

77R memor in terms of its design and wor"ing &rinci&les. 1n fact, it is true: 77R*

07RAM is a sort of third reincarnation of 77R 07RAM &rinci&les. Therefore, we have

ever right to com&are 77R* and 77R- 07RAM side 9 side here. Moreover, this

com&arison will hardl ta"e a lot of time.

FIG 1.1:DDR3 SDRAM


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The fre>uencies of 77R* memor could 9e raised 9eond those of 77R- due to

dou9ling of the data &refetch that was moved from the info storage device to the

in&utout&ut 9uffer. uenc of the memor chi&s, it a&&ears C times lower

than that of the e?ternal memor 9us and 77R* 9uffers (this fre>uenc was / times

lower than that of the e?ternal 9us 9 77R-# 0o, 77R* memor can almost immediatelhit higher actual fre>uencies than 77R- 07RAM, without an modifications or

im&rovements of the semiconductor manufacturing &rocess. 2owever, the a9ove

descri9ed techni>ue also has another side to it: unfortunatel, it increases not onl

memor 9andwidth, 9ut also memor latencies. As a result, we shouldn@t alwas e?&ect

77R* 07RAM to wor" faster than 77R- 07RAM, even if it o&erates at higher

fre>uencies than 77R-.

The final 77R* 07RAM s&ecification released 9 J3734 recentl descri9es a

few modifications of this memor with fre>uencies from C to +HM2D. The ta9le

9elow shows the ma%or s&ecifications of the memor modifications listed in the s&ec:


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TABLE 1.1:DDR3 SDRAM SPECIFICATIONS

4onsidering that the latenc of widel s&read 77R-C 07RAM with ///

timings e>uals +ns, we can reall >uestion the efficienc of 77R* 07RAM at this time.

1t turns out that the new 77R* can onl win due to higher 9andwidth that should ma"e

u& for worse latenc values. Unfortunatel, the transition to 77R* 07RAM is a forced

measure to some e?tent. 77R- has alread e?hausted its fre>uenc &otential com&letel.

Although we can still &ush it to +HHM2D with some allowances, further fre>uenc

increase lowers the &roduction ields dramaticall thus increasing the &rice of the 77R-

07RAM modules. That is wh J3734 didn@t standardiDe 77R- 07RAM with wor"ing

fre>uencies e?ceeding CM2D, su&&orting the transition to 77R* technolog.

2owever, 77R* 07RAM offers a few other useful im&rovements that will

encourage not onl the manufacturers 9ut also the end users to ma"e u& their minds in

favor of the new technolog. Among these advantages 1 would li"e to first of all mention

lower voltage of the 77R* 07RAM modules that dro&&ed down to +.)'. 1t is -I lower

than the voltage of 77R- 07RAM modules, which eventuall results into almost *I

reduction in &ower consum&tion com&ared with 77R- memor wor"ing at the same

cloc" s&eeds. More advanced memor chi&s manufacturing technologies also contri9ute

to this &ositive effect.

FIG 1.2:ESTIMATION GRAPH


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The =$A chi& &ac"aging also underwent a few modifications, and now it features more

&ins. This sim&lifies the chi& mounting &rocedure and increases mechanical contact.

1." DDR3 B=+< L-- C)5 /- H*7P+/-?)+ N+5-

P-)+==

ues are

9ecoming more im&ortant to deal with the massive highthrough&ut &ac"ets of the

internet. Accordingl, advances in memor architectures are re>uired to meet the

emerging 9andwidth demands. 4ontent Addressa9le Memor (4AM# 9ased techni>ues

are widel used in networ" e>ui&ment for fast ta9le loo" u&. 2owever, in com&arison to

Random Access Memor (RAM# technolog, 4AM technolog is restricted in terms of

memor densit, hardware cost and &ower dissi&ation. Recentl, a 2ash4AM circuit ,

which com9ines the merits of the hash algorithm and the 4AM function, was &ro&osed to

re&lace &ure 4AM 9ased loo"u& circuits with com&ara9le &erformance, higher memor

densit and lower cost. Most im&ortantl, offchi& high densit lowcost 77R memor

technolog has now 9ecome an attractive alternative for the &ro&osed 2ash4AM 9ased

loo"u& circuit. 2owever, 77R technolog is o&timiDed for 9urst access for cached

&rocessor &latforms. As such, efficient 77R =andwidth utiliDation is a ma%or challengefor loo"u& functions that e?hi9it short and random memor access &atterns. The e?treme

lowcost and high memor densit features of the 77R technolog allow a tradeoff

9etween memor utiliDation and memor9andwidth utiliDation 9 customiDing the

memor access. This, however, re>uires a custom &ur&ose 77R memor controller that

is o&timiDed to achieve the 9est read efficienc and highest memor 9andwidth. The

o9%ective of this wor" was to investigate advanced 77R* 07RAM controller

architectures and derive a customiDed architecture for the a9ovementioned &ro9lem.

77R* 07RAM is the *rd gener memories, featuring higher &erformance and lower

&ower consum&tion . 1n com&arison with earlier generations, 77R+- 07RAM, 77R*

07RAM is a higher densit device and achieves higher 9andwidth due to the further

increase of the cloc" rate and reduction in &ower consum&tion 9enefiting from 1.5V


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&ower su&&l at 90 nm fa9rication technolog. uest (data in&ut# for a given content is &i&elined and &rocessed 9 the 2ash

circuit to generate an address. This address value is forwarded to 77R* 07RAM

1nterface where it is translated into instructions and addresses that are recogniDed 9 the

77R* memor as an access.

The stored data ; addresses in the memor are read 9ac" to the 2ash4AM circuit in

order to validate the match. 1n the case of corres&onding reference address is reference

address is returned.

1.3 DDR3 A


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CHAPTER "

TYPES OF MEMORY CONTROLLERS


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CHAPTER7"

".1 TYPES OF MEMORY CONTROLLERS

".1.1 D->,+ D5 R5+7S2)*--=


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FIG ".1@GRAPHICAL REPRESANTATION

".1.1DDR D5, P,=+

As shown in the a9ove figure, 77R can transfer twice the amount of data &er

single digital &ulse 9 using 9oth the rising edge, and the falling edge of the

digital signal. 77R can transfer twice the data as 07RAM.

"." D->,+ D5 R5+7S2)*--=


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77R- is a -/ &in 71MM design that o&erates at +.C volts. The lower

voltage counters the heat effect of the higher fre>uenc data transfer. 7RR

o&erates at -.) volts and is a +CC &in 71MM design. 77R- uses a different

mother9oard soc"et than 77R, and is not com&ati9le with mother9oards designed

for 77R. The 77R- 71MM "e will not align with 77R 71MM "e. 1f the

77R- is forced into the 77R soc"et, it will damage the soc"et and the memor

will 9e e?&osed to a high voltage level. Also 9e aware the 77R is +CC &in 71MM

design and 77R- is a -/ &in 71MM design.

".3 D->,+ D5 R5+7S2)*--=


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memor t&es do not have this feature which means the memor state is uncertain

after a sstem re9oot. The memor reset feature insures that the memor will 9e

clean or em&t after a sstem re9oot. This feature will result in a more sta9le

memor sstem. 77R* uses the same -/&in design as 77R-, 9ut the memor

module "e notch is at a different location.


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".4 COMPARISION OF DDR1% DDR" AND DDR3

FIG "."@COMPARISION OF DDR9S


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-.) O5*+ M+?-2 T2+=:

".8.1 &


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high s&eed, dura9ilit, and low voltage re>uirements, it is ideal for digital

cameras, cell &hones, &rinters, handheld com&uters, &agers and audio recorders.

".8.3 S*


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ta"e on. uire two 4PU wait states for each e?ecution.

4an onl e?ecute either a read or write o&eration at one time. The ca&acitor in a

dnamic RAM memor cell is li"e a lea" 9uc"et. 1t needs to 9e refreshed

&eriodicall or it will discharge to . This refresh o&eration is where dnamic

RAM gets its name. 7namic RAM has to 9e dnamicall refreshed all of the

time or it forgets what it is holding. The downside of all of this refreshing is that it

ta"es time and slows down the memor.

Memor cells are etched onto a silicon wafer in an arra of columns (9it

lines# and rows (word lines#. The intersection of a 9it line and word line

constitutes the address of the memor cell. Memor cells alone would 9e

worthless without some wa to get information in and out of them. 0o the

memor cells have a whole su&&ort infrastructure of other s&ecialiDed circuits.

These circuits &erform functions such as:Memor is made u& of 9its arranged in a

twodimensional grid. 1n this figure, red cells re&resent +s and white cells


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re&resent s. 1n the animation, a column is selected and then rows are charged to

write data into the s&ecific column.

1dentifing each row and column (row address select and column address

select# !ee&ing trac" of the refresh se>uence (counter# Reading and restoring the

signal from a cell (sense am&lifier# Telling a cell whether it should ta"e a charge

or not (write ena9le# 5ther functions of the memor controller include a series of

tas"s that include identifing the t&e, s&eed and amount of memor and chec"ing

for errors. The traditional RAM t&e is 7RAM (dnamic RAM#. The other t&e is

0RAM (static RAM#. 0RAM continues to remem9er its content, while 7RAM

must 9e refreshed ever few milli seconds.

7RAM consists of micro ca&acitors, while 0RAM consists of offon

switches. Therefore, 0RAM can res&ond much faster than 7RAM. 0RAM can 9e

made with a rise time as short as / ns. 7RAM is 9 far the chea&est to 9uild.

Newer and faster 7RAM t&es are develo&ed continuousl. 4urrentl, there are at

least four t&es:

FPM (Fast Page Mode

344 (3rror 4orrecting 4ode#

375 (3?tended 7ata 5ut&ut#

07RAM (0nchronous 7namic RAM#

".8.6 C)*+ M+?-2

4ache Memor is fast memor that serves as a 9uffer 9etween the

&rocessor and main memor. The cache holds data that was recentl used 9 the

&rocessor and saves a tri& all the wa 9ac" to slower main memor. The memor

structure of P4s is often thought of as %ust main memor, 9ut its reall a five or

si? level structure: The first two levels of memor are contained in the &rocessor


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itself, consisting of the &rocessors small internal memor, or registers, and 6+

cache, which is the first level of cache, usuall contained in the &rocessor. The

third level of memor is the 6- cache, usuall contained on the mother9oard.

2owever, the 4eleron chi& from 1ntel actuall contains +-C! of 6- cache within

the form factor of the chi&. More and more chi& ma"ers are &lanning to &ut this

cache on 9oard the &rocessor itself. The 9enefit is that it will then run at the same

s&eed as the &rocessor, and cost less to &ut on the chi& than to set u& a 9us and

logic e?ternall from the &rocessor.The fourth level is 9eing referred to as 6*

cache. This cache used to 9e the 6- cache on the mother9oard, 9ut now that some

&rocessors include 6+ and 6- cache on the chi&, it 9ecomes 6* cache. Usuall, itruns slower than the &rocessor, 9ut faster than main memor. The fifth level (or

fourth if ou have no L6* cacheL# of memor is the main memor itself. The si?th

level is a &iece of the hard dis" used 9 the 5&erating 0stem, usuall called

virtual memor. Most o&erating sstems use this when the run out of main

memor, 9ut some use it in other was as well.

This si?tiered structure is designed to efficientl s&eed data to the

&rocessor when it needs it, and also to allow the o&erating sstem to function

when levels of main memor are low. 1f there were one t&e of su&erfast, su&er

chea& memor, it could theoreticall satisf the needs of this entire memor

architecture. This will &ro9a9l never ha&&en since ou dont need ver much

cache memor to drasticall im&rove &erformance, and there will alwas 9e a

faster, more e?&ensive alternative to the current form of main memor.

".8.$ C-5+57A


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as associative memor, associative storage, or associative arra, although the last

term is more often used for a &rogramming data structure.

".8. H


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CHAPTER 3

D+= -/ DDR3SDRAM

COTROLLER


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CHAPTER 3CHAPTER 3

DESIGN OF DDR3SDRAM COTROLLER

3.1 I5-


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with the registration of an A4T1'AT3 command, which is then followed 9 a

R3A7 or


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The functional 9loc" diagram of the 77R* controller is shown in 8igure

*.+. The architecture of 77R*07RAM controller consists of 1nitialiDation fsm

4ommand fsm, data &ath , 9an" control ,cloc" counter, refresh counter, Address

8185, command 8185 ,


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3."." W5+


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INITIAL FSM STATE DIAGRAM@

F. 3."@ INITIAL FSM STATE DIAGRAM


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=efore normal memor accesses can 9e &erformed, 77R* needs to 9e

initialiDed 9 a se>uence of commands. The 1N1TE80M state machine handles

this initialiDation. 8igure *.- shows the state diagram of the 1N1TE80M state

machine. 7uring reset, the 1N1TE80M is forced to the iE1763 state. After reset,

the ssEdlE-U0 signal will 9e sam&led to determine if the -s &owercloc"

sta9iliDation dela is com&leted. After the &owercloc" sta9iliDation is com&lete,

the 77R initialiDation se>uence will 9egin and the 1N1TE80M will switch from

iE1763 to iEN5P state and in the ne?t cloc" to 1EPR3.

The initialiDation starts with the PR342AR$3 A66 command. Ne?t a

65A7 M573 R3$10T3R command will 9e a&&lied for the 3?tended mode

register to ena9le the 766 inside 77R, followed 9 another 65A7 M573

R3$10T3R command to the mode register to reset the 766. Then a PR342A$3

command will 9e a&&lied to ma"e all 9an"s in the device to idle state. Then two,

AUT5 R38R302 commands, and then the 65A7 M573 R3$10T3R command

to configure 77R to a s&ecific mode of o&eration. After issuing the 65A7

M573 R3$10T3R command and the tMR7 timing dela is satisfied, 1N1TE80M

goes to iEread state and remains there for the normal memor access ccles

unless reset is asserted. Also, signal ssEinitEdone is set to high to indicate the

77R initialiDation is com&leted. The iEPR3, iEAR+, iEAR-, iE3MR0 and iEMR0

states are used for issuing 77R commands. The 65A7 M573 R3$10T3R

command configures the 77R 9 loading data into the mode register through the

address 9us. The data &resent on the address 9us (ddrEadd# during the 65A7

M573 R3$10T3R command is loaded to the mode register. The mode register

contents s&ecif the 9urst length, 9urst t&e, 4A0 latenc, etc. A

PR342AR$3AUT5 PR342AR$3 command moves all 9an"s to idle state. As

long as all 9an"s of the 77R are in idle state, mode register can 9e reloaded with

different value there9 changing the mode of o&eration. 2owever, in most


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a&&lications the mode register value will not 9e changed after initialiDation. This

design assumes the mode register stas the same after initialiDation.

As mentioned a9ove, certain timing delas (tRP, tR84, tMR7# need to 9e

satisfied 9efore another nonN5P command can 9e issued. These 07RAM delas

var from s&eed grade to s&eed grade and sometimes from vendor to vendor. To

accommodate this without sacrificing &erformance, the designer needs to modif

the 276 code for the s&ecific delas and cloc" &eriod (t4!#. According to these

timing values, the num9er of cloc"s the state machine will sta at iEtRP, iEtR84+,

iEtR84-, iEtMR7 states will 9e determined after the code is snthesiDed. 1n cases

where t4! is larger than the timing dela, the state machine doesn@t need to

switch to the timing dela states and can go directl to the command states. The

dashed lines in 8igure *.* show the &ossi9le state switching &aths.

3.3 D//++5 =55+= -/ I5, FSM@

3.3.1 I


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the =A, =A+ in&uts selects the 9an", and the A+ in&ut selects whether a single

9an" is &recharged or whether all 9an"s are &recharged.

F. 3.3@ P+ )*+ C-??uired. All

9an"s must 9e idle 9efore an AUT5 R38R302 command is issued.

3.3.8 L-< M-


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not et com&leted.5nce the initialiDation is done, ssEA70n and ssER38ER3

will 9e sam&led at the rising edge of ever cloc" ccle. A logic high sam&led on

ssER38ER3 will start a 07RAM refresh ccle. This is descri9ed in the

following section. 1f logic low is sam&led on 9oth ssER38ER3 and ssEA70n,

a sstem read ccle or sstem write ccle will 9egin. These sstem ccles are

made u& of a se>uence of 07RAM commands

3.3.$ COMMAND FSM STATE DIAGRAM@

F. 3.4@ COMMAND FSM STATE DIAGRAM FOR NORMAL WRITE

AND READ


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The figure /.+ shows the state diagram of 4M7E80M, which handles

read, write and refresh of the 77R. The 4M7E80M state machine is initialiDed to

cEidle during reset. After reset, 4M7E80M stas in cEidle as long as

ssEinitEdone is low which indicates the 77R initialiDation se>uence is not et

com&leted. 8rom this state, a R3A7AEduringErefEre> signals as shown in the state

diagram.

All rows are in the closedK status after the 77R initialiDation. The rows

need to 9e o&enedK 9efore the can 9e accessed. 2owever, onl one row in the

same 9an" can 9e o&ened at a time. 0ince there are four 9an"s, there can 9e at

most four rows o&ened at the same time. 1f a row in one 9an" is currentl o&ened,

it needs to 9e closed 9efore another row in the same 9an" can 9e o&ened.

A4T1'3 command is used to o&en the rows and PR342AR$3 (or the AUT5

PR342AR$3 hidden in the uired for

readwrite ccle are fi?ed and the access can 9e random over the full address

range. Read or write is determined 9 the ssErEwn status sam&led at the rising

edge of the cloc" 9efore the tR47 dela is satisfied. 1f logic high is sam&led, the

state machine switches to cER3A7A. 1f a logic low is sam&led, the state machine

switches to cE


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8or read ccles, the state machine switches from, cER3A7A to cEcl for

4A0 latenc, then switches to crate for transferring data from 77R to &rocessor.

The 9urst length determines the num9er of cloc"s the state machine stas in

cErdata state. After the data is transferred, it switches 9ac" to cEidle.

8or write ccles, the state machine switches from cEuence, no commands other than

N5P can 9e issued to 77R 9efore t7A6 is satisfied.

The dashed lines indicate &ossi9le state switching &aths when the t4!

&eriod is larger than the timing dela s&ecification.

C-??< FSM 5* /=5 +< -+5-@

8ast read can 9e achieved 9 switching 9an"s. =an" control logic is used

to issue desired 9an" addresses at each ccle when a 9an" active command or

read command is issued. The state machine for this method is given in 8igure

/(9#. The &ro&osed controller &rovides the control interface for switching 9etween

normal writeread mode and fast read mode. Unli"e other data &rocessing

techni>ues, the distinct characteristic of the random data loo"u& is the uncertaint

of the incoming data. 1n this wor", address 8185s are a&&lied to 9uffer the

rowcolumn addresses se&aratel for each read re>uest. The em&tK flag of the

row address 8185 (addr!fifo!empt"# is chec"ed in order to evaluate whether the

ne?t command is active (#$%# or read (&'##


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COMMAND FSM

FIG 3.8 COMMAND FSM FAST READ WITH AUTO PRECHARGE


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CHAPTER 4

DIFFERENT STATES OF

COMMAND FSM


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CHAPTER74

4.1 DIFFERENT STATES OF COMMAND FSM

4.1.1 R+/+=* C2),+@

77R memor needs a &eriodic refresh to hold the data. This &eriodic

refresh is done using AUT5 R38R302 command. All 9an"s must 9e idle 9efore

an AUT5 R38R302 command is issued. 1n this design all 9an"s will 9e in idle

state, as ever readwrite o&eration uses auto &re charge.

4.1." A)5+ (ACT!@

The A4T1'3 command is used to o&en (or activate# a row in a &articular

9an" for a su9se>uent access, li"e a read or a write, as shown in 8igure /.-. The

value on the =A, =A+ in&uts selects the 9an", and the address &rovided on

in&uts AQAn selects the row.

F. 4.1@ A)55 S+)/) R- S+)/) B.


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4.1.3 R+


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F. 4.3@ W5+ C-??uired to &in&oint the memor cell location of the 07RAM access. 0ince

07RAM is com&osed of four 9an"s, 9an" address needs to 9e &rovided as well.

The 07RAM can 9e considered as a four 9 N arra of rows. All rows are

in the closedK status after the 07RAM initialiDation. The rows need to 9e

o&enedK 9efore the can 9e accessed. 2owever, onl one row in the same 9an"

can 9e o&ened at a time. 0ince there are four 9an"s, there can 9e at most four rows

o&ened at the same time. 1f a row in one 9an" is currentl o&ened, it must 9e

closed 9efore another row in the same 9an" can 9e o&ened.A4T1'3 command is

used to o&en the rows and PR342AR$3 (or the AUT5 PR342AR$3 hidden in

the


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will not fit the general a&&lications.Therefore, this 07RAM controller design does

not im&lement these custom features to achieve the highest &erformance through

these techni>ues.

1n this design, the A4T1'3 command will 9e issued for each read or write

access to o&en the row. After a tR47 dela is satisfied, R3A7 or


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cloc" rising edge of the last data in the 9urst se>uence, no commands otherthan

N5P can 9e issued to 07RAM 9efore t7A6 is satisfied.

As mentioned in the 1N1TE80M section a9ove, the dash lines indicates

&ossi9le state switching &aths when t4! &eriod is larger than timing dela s&ec.

4.1.8 R+/+=* C2),+@

0imilar to the other 7RAMs, memor refresh is re>uired. A 07RAM

refresh re>uest is generated 9 activating sdrER38ER3 signal of the controller.

The sdrER38EA4! signal will ac"nowledge the recognition of sdrER38ER3and will 9e active throughout the whole refresh ccle. The sdrER38ER3 signal

must 9e maintained until the sdrER38EA4! goes active in order to 9e recogniDed

as a refresh ccle. Note that no sstem readwrite access ccles are allowed when

sdrER38EA4! is active. All sstem interface ccles will 9e ignored during this

&eriod. The sdrER38ER3 signal assertion needs to 9e removed u&on recei&t of

sdrER38EA4! ac"nowledge,otherwise another refresh ccle will again 9e

&erformed.U&on recei&t of sdrER38ER3 assertion, the state machine

4M7E80M enters the cEAR state to issue an AUT5 R38R302 command to the

07RAM. After tR84 time dela is satisfied, 4M7E80M returns to idle.


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4.1.6. D5 P5* C-5-,

7ata &ath module &erforms the data latching and dis&atching 9ased on the

command fsm states. 1t &rovides interface 9etween the Read data register and the

memor 9an"s

4.1.$. B )-5-,

The 9an" control controls the all the eight 9an"s effectivel de&ending

u&on the istate and cstate 9 sending the re>uired control signals.

4.1. T? D?=@

The figures /.) and /.H are the read ccle and write ccle timing diagrams

of the reference design with the two 4A0 latenc ccles and the 9urst length of

four. The timing diagrams ma 9e different due to the values of the timing delas

tMR7tRPtR84tR47tR47t


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F. 4.4@ R+< C2),+ T? D?.

F. 4.8@ W5+ C2),+ T? D?.

)


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4." AD&ANTAGES

+. 2igher 9andwidth &erformance increase, effectivel u& to -/M2D.

-. Performance increase at low &ower (longer 9atter life in la&to&s#.

*. 3nhanced low &ower features with im&roved thermal design (cooler#.

/. 4om&ared w+th 77R07RAM the voltage of 77R* 07RAM was

lowered from -.)' to +.)'. This im&roves &ower consum&tion and heat

generation, as well as ena9ling more dense memor configurations for higher

ca&acities

). 77R* 07RAM achieves nearl twice the 9andwidth of the &receding

single data rate 77R- 07RAM 9 dou9le &um&ing (transferring data on the

rising and falling edges of the cloc" signal# without increasing the cloc"

fre>uenc.

H. 77R 07RAM is a &articularl e?&ensive alternative to 77R* 07RAM,

and most manufacturers have dro&&ed its su&&ort from their chi&sets.

. 4A0 latenc is less com&ared to 77R07RAM.

C. 07RAM can acce&t one command and transfer one word of data &er cloc"

ccle. T&ical cloc" fre>uencies are ) and +** M2D.ddr two commands n

su&&orts u&to-MhD.

G. 6ow &ower consum&tion.

+. 6ow manufacturing cost.

++. 6owvoltage, +.)' 77R* reduced chi& count &rovides significant &ower

savings.

)+


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4.3 DISAD&ANTAGES@

4ommonl higher 4A0 6atenc 9ut com&ensated 9 higher 9andwidth,

there9 increasing overall &erformance under s&ecific a&&lications generall costs

much more than e>uivalent 77R- memor.

)-


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CHAPTER 8

RESULTS

)*


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CHAPTER 8CHAPTER 8

RESULTS

8.1SIMULATION RESULTS@

TOP MODULE OUTPUT

)/


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8.1.1 A


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8.1." C-5-, //-

8.1.3 W5+


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8.1.4 I5,5- FSM

8.1.8 C-??< FSM

8.1.8.1 N-?, W5+ -+5-

)


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8.1.8." N-?, R+< -+5-

8.1.8.3 F=5 R+< -+5-

)C


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8.1.6 D5 5* )-5-,

8.1.$ T- ?-


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8.1.$." N-?, R+< -+5- (!

8.1.$.3 F=5 R+< -+5- (!

H


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CHAPTER 6

CONCLUSION AND FUTURE

SCOPE

H+


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CHAPTER 6CHAPTER 6

CONCLUSION AND FUTURESCOPE

6.1 CONCLUSION@

1n this &ro%ect we have designed a 2igh s&eed 77R* 07RAM 4ontroller

with H/9it data transfer which snchroniDes the transfer of data 9etween 77R

RAM and 3?ternal &eri&heral devices li"e host com&uter, la&to&s and so on. The

advantages of this controller com&ared to 07R 07RAM , 77R+ 07RAM and

77R- 07RAM is that it snchroniDes the data transfer, and the data transfer is

twice as fast as &revious, the &roduction cost is also ver low.

H-


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6." FUTURE SCOPE

+. 77R/ 07RAM is the /th generation of 77R 07RAM.

-. 77R* 07RAM im&roves on 77R 07RAM 9 using differential

signaling and lower voltages to su&&ort significant &erformance advantages over

77R 07RAM.

*. 77R* 07RAM standards are still 9eing develo&ed and im&roved.

77R 07RAM 0tandard 8re>uenc (M2D# 'oltage

77R /)** -.)

77R- HHC +.C

77R* +HH to ... +.)

/. 2igher fre>uencies ena9le higher rates of data transfer.

). 77R* 07RAM (7ou9le 7ata Rate Three 0nchronous 7namic Random

Access Memor# is the third generation of 77R 07RAM.

H. Reduced &ower consum&tion due to Gmm fa9rication technolog.

. Prefetch 9uffer is dou9led to C 9its to further increase &erformance.

.

H*


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CHAPTER $

REFRENCES

CHAPTER $CHAPTER $

REFERENCES

H/


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+. A. J. McAule, et al, 8ast Routing Ta9le 6oo"u& Using 4AMsK, Proeedings

on 1)th #nnual *oint $onferene of the+,,, $omputer and $ommuniations

Soieties (+-F$M, 'ol.*, March +GG*, &&.+*C- Q +*G+.

-. F. Bang, et al, 2igh Performance 1P 6oo"u& 4ircuit Using 77R 07RAMK,

+,,, +nternational S$ $onferene (S$$/0e&t. -C, &&. *+*/.

*. $. Allan, The 6ove2ate Relationshi& with 77R 07RAM 4ontrollersK,

MS#+' %ehnologies hitepaper, -H.

/. 2. !im, et al, 2ighPerformance and 6owPower Memor 1nterface

Architecture for 'ideo Processing A&&licationK, +,,, %ransations on $iruit

and S"stems for Video %ehnolog", 'ol. ++, Nov. -+, &&. ++H++.). 3. $. T. Jas&ers, et al, =andwidth Reduction for 'ideo Processing in

4onsumer 0stemsK, 1333 Transactions on 4onsumer 3lectronics, 'ol. /, No. /,

Nov. -+, &&. CC) CG/.

H. N. Vhang, et al, 2igh Performance and 2igh 3fficienc Memor Management

0stem for 2.-H/A'4 A&&lication in the 7ual4ore PlatformK, +$#S,, 5ct.

-H, &&. )+G)--.

. J. Vhu, et al, K2igh Performance 0nchronous 7RAMs 4ontroller in 2. -H/

27T' 7ecoderK, Proceedings of 1nternational 4onference on 0olid0tate and

1ntegrated 4ircuts Technolog, 'ol. *, 5ct. -/, &&. +H-++H-/.

C. 2ighPerformance 77R* 07RAM 1nterface in 'irte?) 7evicesK, ilin2/

#PP834 (1.0, 0e&t -/, -.

G. T. Mladenov, =andwidth, Area 3fficient and Target 7evice 1nde&endent 77R

07RAM 4ontrollerK, Proceedings of


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++. www.altera.comliteratureugugEaltmem&h.&df, 3?ternal 77R Memor

P2B 1nterface Megafunction User $uide (A6TM3MP2B# accessed on -* 8e9.

-G.

HH


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CHAPTER

APPENDI'

CHAPTER

H


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APPENDI'

&ERILOG HDL

8.1 Overview

2ardware descri&tion languages, such as 'erilog , differ from software

&rogramming languages 9ecause the include was of descri9ing the &ro&agation

of time and signal de&endencies (sensitivit#. There are two assignment o&erators,

a 9loc"ing assignment (W#, and a non9loc"ing (XW# assignment. The non

9loc"ing assignment allows designers to descri9e a statemachine u&date without

needing to declare and use tem&orar storage varia9les. 0ince these conce&ts are

&art of the 'erilog language semantics, designers could >uic"l write descri&tions

of large circuits, in a relativel com&act and concise form. At the time of 'erilog

introduction (+GC/#, 'erilog re&resented a tremendous &roductivit im&rovement

for circuit designers who were alread using gra&hical schematicca&ture, and

s&eciallwritten software &rograms to document and simulate electronic circuits.

The designers of 'erilog wanted a language with snta? similar to the 4

&rogramming language, which was alread widel used in engineering software

develo&ment. 'erilog is casesensitive, has a 9asic &re&rocessor (though less

so&histicated than AN01 44YY#, and e>uivalent control flow "ewords (ifelse,

for, while, case, etc.#, and com&ati9le language o&erators &recedence. 0ntactic

differences include varia9le declaration ('erilog re>uires 9itwidths on netreg

t&es#, demarcation of &rocedural9loc"s (9eginend instead of curl 9races #,and man other minor differences.

HC


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A 'erilog design consists of a hierarch of modules. Modules enca&sulate

design hierarch, and communicate with other modules through a set of declared

in&ut, out&ut, and 9idirectional &orts. 1nternall, a module can contain an

com9ination of the following: netvaria9le declarations concurrent and se>uential

statement 9loc"s and instances of other modules. 0e>uential statements are &laced

inside a 9eginend and e?ecuted in se>uential order within the 9loc". =ut the

9loc"s themselves are e?ecuted concurrentl, >ualifing 'erilog as a 7ataflow

language.

'erilog conce&t of wire consists of 9oth signal values (/state: L+, ,

floating, undefinedL#, and strengths (strong, wea", etc.# This sstem allows

a9stract modeling of shared signallines, where multi&le sources drive a common

net.


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7esign Automation in +GC)# as a hardware modeling language. $atewa 7esign

Automation was later &urchased 9 4adence 7esign 0stems in +GG. 4adence

now has full &ro&rietar rights to $atewas 'erilog and the 'erilogF6

simulator logic simulators.

&+,-7:8

uired an e?&licit

descri&tion of the 9ooleanalge9ra to determine its correct value.# The same

function under 'erilog-+ can 9e more succinctl descri9ed 9 one of the 9uilt

in o&erators: Y, , , Z, [[[. A generateend generate construct (similar to '276s


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generateend generate# allows 'erilog-+ to control instance and statement

instantiation through normal decisiono&erators (caseifelse#. Using generateend

generate, 'erilog-+ can instantiate an arra of instances, with control over the

connectivit of the individual instances. 8ile 15 has 9een im&roved 9 several

new sstemtas"s. And finall, a few snta? additions were introduced to im&rove

codereada9ilit (eg. alwas \Z, named&arameter override, 4stle

functiontas"module header declaration.# 'erilog-+ is the dominant flavor of

'erilog su&&orted 9 the ma%orit of commercial 37A software &ac"ages.

&+,- "008

Not to 9e confused with 0stem'erilog, 'erilog -) (1333 0tandard

+*H/-)# consists of minor corrections, s&ec clarifications, and a few new

language features (such as the uwire "eword.# A se&arate &art of the

'erilog standard, 'erilogAM0, attem&ts to integrate analog and mi?ed signal

modelling with traditional 'erilog.

.3 D+= S52,+=

'erilog, li"e an other hardware descri&tion language, &ermits a design in

either =ottomu& or To&down methodolog.

B-55-?7U D+=

The traditional method of electronic design is 9ottomu&. 3ach design is

&erformed at the gatelevel using the standard gates (refer to the 7igital 0ection

for more details#.


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These traditional 9ottomu& designs have to give wa to new structural,

hierarchical design methods.


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'erilog su&&orts designing at man different levels of a9straction. Three of

them are ver im&ortant:

=ehavioral level

RegisterTransfer 6evel

$ate 6evel

B+*-, ,++,

This level descri9es a sstem 9 concurrent algorithms (=ehavioral#. 3ach

algorithm itself is se>uential, that means it consists of a set of instructions that are

e?ecuted one after the other. 8unctions, Tas"s and Alwas 9loc"s are the main

elements. There is no regard to the structural realiDation of the design.

R+=5+7T=/+ L++,

7esigns using the RegisterTransfer 6evel s&ecif the characteristics of a

circuit 9 o&erations and the transfer of data 9etween the registers. An e?&licit

cloc" is used. RT6 design contains e?act timing 9ounds: o&erations are scheduled

to occur at certain times. Modern RT6 code definition is LAn code that is

snthesiDa9le is called RT6 codeL.

G5+ L++,


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is generated 9 tools li"e snthesis tools and this net list is used for gate level

simulation and for 9ac"end.

.8 A>-5 &+,- HDL

7igital sstems are highl com&le?. At their most detail level, the ma

consist of millions of elements li"e transistors or logic gates. Therefore, for large

digital sstems, gate level design is dead. To avoid that, 'erilog 276 was

introduced.

'erilog 276 is a 2ardware 7escri&tion 6anguage (276#. 1t is a

language used to descri9e a digital sstem, which ma 9e a com&uter or a

com&onent of a com&uter. 5ne ma descri9e a digital sstem at several levels.

8or e?am&le, an 276 might descri9e the laout of the wires, resistors and

transistors on an 1ntegrated 4ircuit (14# chi&, i.e. the switch level. 5r, it might

descri9e the logical gates and fli&flo&s in a digital sstem, i.e. the gate level.

An even higher level descri9es the registers and the transfers of vectors of

information 9etween registers. This is called the Register Transfer 6evel

(RT6#. 'erilog su&&orts all of these levels. 1t is ver much li"e the 4

language.

.6S,+5 F+5+= -/ &+,-@

Primitive logic gates such as AN7, 5R and NAN7 gates are 9uiltin

into this language.

8le?i9ilit of creating a userdefined &rimitive (U7P#. 0uch a&rimitive could either 9e a com9inational logic &rimitive or a

se>uential logic &rimitive.

/


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0witchlevel modeling &rimitive gates, such as PM50 and NM50 are

also 9uiltin into this language.

3?&licit language constructs are &rovided for s&ecifing &into&in

delas, &ath delas and timing chec"s of a dela.

A design can 9e modeled in three different stles or in a mi?ed stle.

These stles are 9ehavioral stle modeled using continuous

assignments, stlemodeled using gate and module instantiations.

There are two data t&es in verilog 276, the net data t&e and register

data t&e. The net t&e re&resents a &hsical connection 9etween

structural elements while a register t&e re&resents an a9stract data

storage element.

A design can 9e of ar9itrar siDe the language does not im&ose a limit.

+. 'erilog 276 is non&ro&rietar and is an 1333 standard.

1t is 9oth human and machine reada9le. Thus it can 9e used as an

e?change

anguage 9etween tools and designers.

The ca&a9ilit of the 'erilog 276 language can 9e further e?tended

9 using the &rogramming language interface (P61# mechanism. P61 is

a collection of routines that allow foreign functions to access

information within a verilog module and allows for designer

interaction with the simulator.

At the 9ehaviorallevel, 'erilog 276 can 9e used to descri9e a design

not onl at the RT6level, 9ut also at the architecturallevel and its

algorithmiclevel 9ehavior. At the structurallevel, gate and module instantiations can 9e used.

'erilog 276 also has 9uiltin logic functions such as ; (9it wise

AN7# ^ (9it wise 5R#.

)


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Notion of concurrenc and time can 9e e?&licitl modeled.

Powerful file read and write ca&a9ilities are &rovided

'erilog 276 can 9e used to &erform res&onse monitoring of the design

under test, that is, the values of a design under test can 9e monitored and

dis&laed. These values can also 9e com&ared with e?&ected values, and

in case of a mismatch, a re&ort message can 9e &rinted.

The language is nondeterministic under certain situations, that is, a model

ma &roduce different results on different simulators for e?am&le, the

ordering of events on an event >ueue is not defined 9 the standard.

ddr3 reportnew bala (1)f

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