ddr4 bus level signal integrity insight

DDR4 Bus Level Signal Integrity Insight

Stephen Slater

HSD Design and Simulation

Product Manager

Keysight EEsof EDA

January 20, 2016

Jennie Grosslight

Logic Analyzer Memory Solutions

Product Manager

Agenda

– Overview: Tools for DDR4 Design, Debug, and Validation

– Simulation

• Basic design tools

• Predicting Cross talk

• JEDEC compliance for data valid windows

– Insight Gained from Logic Analyzer

• Navigating DDR Eye Scans for Bus Level Signal Integrity Insight

- Crosstalk on DDR4 Address example

- Further DDR4 Eye Scan Insight examples

– Summary, Equipment, Resources, and Q&A

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DesignCon 2016

© Keysight Technologies

Tools for DDR4 Design, Debug, and Validation

Design

Simulation Measurement

Correlation

Signal Integrity

Infiniium V-Series Scope

Software Compliance

Applications for all

generations of DDR and

LPDDR memory

M8020 High-Performance

JBERT

Protocol/Bus Level SI

U4164 Logic

Module

Bus level signal

integrity insight

using

B4661A

Memory

Analysis SW

Custom & Standard

Probing & Interposer

Solutions

3

Keysight ADS

Agenda


– Simulation









Simulation: A practical design methodology for DDR4

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DesignCon 2016


Practical Design Methodology for DDR4

– IBIS model for Driver and Receiver

• Alternatively On-Die Termination, and On-Die RLC model.

– Package

– Socket for CPU (if applicable)

– Vias and Swizzles

– Pin-field breakout traces

– Motherboard traces

– Pin-field and Vias for DIMM Connector

– DIMM Connector

– DIMM Raw Card traces up to Data Buffer

Modeling an LR-DIMM Server for Pre-Layout Design Exploration

Create Individual

Schematics for:

• Data

• Command/Address

• Control

• Post Data Buffer

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Practical Simulation Methodology for DDR4Pre-layout exploration in Advanced Design System

(ADS)SPICE

models

IBIS

models

S-param

models

Parameters

to sweep

View

waveform

at any node

Data Lines:

8 DQ

1 DQS

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DesignCon 2016


Practical Simulation Methodology for DDR4Pre-layout exploration in Advanced Design System (ADS)

Command/Address for LR-DIMM:

Challenging Configuration for SI

Performance (0r0r1r)Capturing

waveform

here

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Practical Simulation Methodology for DDR4Pre-layout exploration in Advanced Design System (ADS)

Command/Address for LR-DIMM:

Post-Register

Register

on

DIMM

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Basic Design Tools

– Troubleshooting/Optimizing

• ISI (Inter Symbol Interference) in the channel

• Frequency dependent Loss

• Impedance mismatch (discontinuities) causing reflections

• Random Jitter (e.g. thermal noise in ICs)

• Deterministic Jitter (e.g. Cross Talk)

• Degradation due to VCC bounce (synchronous switching noise and the

the Power Delivery network)

• Optimizing On Die Termination (ODT) settings

– Compliance

• Traditional Timing measurements on Data, CMD/ADD, and Clk lines

• New Bit Error Rate (BER) Receive Mask Spec on Data DQ lines

What are we looking to measure?

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Basic Design Tools

- Linear Simulator [Frequency Domain]

• S-parameter frequency response of the channel

• Magnitude and frequency dependency of

Crosstalk

– TDR/TDT

• Can be calculated directly from the bandlimited

S-parameter data or stimulated from a pulsed

source, using transient convolution.

• Shows where in the channel impedance

mismatches occur, whether it is capacitive or

inductive, and if it’s a stub or series resonance.

– Transient Convolution [Time Domain]

• Calculate the voltage and current waveforms at

any node in the channel.

• Accurately handles cascades of S-parameter

blocks, transmission lines, SPICE models and

IBIS blocks

Which tool do I use?

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Basic Design Tools

- DDR Bus Simulator [Time Domain]

• Fast statistical channel simulation across multiple

parallel lines

• Provides BER contours down to really low BERs

• Correctly handles single-ended signals with

asymmetric rising and falling edges

– Electromagnetic Simulation [Frequency Domain]

• Once a layout is ready, it can be characterized

with an EM simulator to provide a higher-fidelity

representation of the channel.

• S-parameter model is returned for circuit

simulation

• PDN can be characterized as well as the signal

traces in one simulation.

– Power-aware SI [Time Domain]

• Specific IBIS models that support a fluctuating

voltage on the supply pin. Voltage provided

through EM characterized PDN. Transient Sim.

Which tool do I use? DDR Bus Sim

Noise on PDN

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Basic Design ToolsEvaluating simulation results

– DC and AC measurements in Transient (top)

– Aperture Measurements DDR Bus Simulator (inset)

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Basic Design ToolsCompliance Tests – Traditional Timing Measurements

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Basic Design ToolsDesign of Experiments – Automated Parameter Configurations

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Agenda


– Simulation









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Predicting Crosstalk: EM Characterization of PCBADS 2016 SIPro & PIPro released at DesignCon 2016

– High-capacity

– High-frequency

accuracy

– PDN and Signals

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DesignCon 2016


Predicting CrosstalkAnalyzing ISI contributions

DQ10

(Victim)

DQ12

(Aggressor )

DQ124

(Aggressor )

Near-end

Crosstalk

(NEXT)

19 mV

Far-end Crosstalk

(FEXT)

21 mV

On Static Low Victim vs

Time (3 Aggressors) 18

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DesignCon 2016


Predicting CrosstalkCompliance Test for Final Design Sign-Off

DC output

Simulated Waveforms saved as .h5 files for

Infiniium Offline

Real test benchInfiniium oscilloscope

• Before committing the board to prototype,

a final test can be performed simulating

the transient waveforms for DQ, CA, CTL

lines.

• The waveforms are then used within the

Infiniium Offline software, where the

DDR4 Compliance Application is

launched to performs compliance tests.

• This is the same compliance test that is

used with the final board under test on the

bench, so there is no argument as to

whether the simulation compliance test

has missed anything critical.

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Agenda


– Simulation









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JEDEC Compliance for Data Valid Windows

– Ultra low 1e-16 BER mask

– Simpler definition of DRAM requirements and system design

– Not practical for Transient Simulation (too many bits!)

– Requires new simulation methodology

New Rx BER Mask Test

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JEDEC Compliance for Data Valid Windows

DDR Bus Simulator in ADS 2016

• Calculates BER contours at 1e-16

• Measures margin from contour to

mask

• New in ADS 2016, support for EQ

in Receiver model (CTLE, FFE, n-

tap DFE)

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Agenda


– Simulation









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Connect Acquire View & Analyze

Mid-Bus &

specialty Probing

Memory Analysis SW

Listing with Decoders

Traffic Overview

Protocol Compliance

across Speed changes

Performance Analysis

WaveformsBus Level Signal

Integrity Insight

Capture highest data rates! Address and command for DDR4

or LPDDR4 up to 5000 Mb/sData up to 4000 Mb/s

Capture smallest eyes!100mV x 100ps at probe point.

Sequential Triggers up to 2.5GHz or 4000 Mb/s!

12.5GHz Timing Zoom 256k deep

Up to 400M deep traces

DIMM

SODIMM

Interposers

U4164A Logic Analyzer

Module

New

B4661A Memory

Analysis SW

New

New

BGA Interposers

New

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Insight Gained from a Logic Analyzer

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DesignCon 2016


Accelerate DDR4 Debug & Validation with a Logic Analyzer

Logic Analyzer

Rapid Navigation* Traffic Overview

Accelerated Insight * See when events happened.* Follow signal flow and understand, “What happened?”* Compliance Testing to locate potential failures

Bus Level Signal Integrity Insight

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Signal Integrity

Measurements

Functional Analysis and Validation

Plus


Design

Infiniium V Series Scope

InfiniiMax Probes

U4164A Logic Analyzer System

Bus Level

Signal Integrity

Insight

View all signals

relative to each other.

EEsof EDA

Bus Level Signal Integrity InsightBridging a measurement gap

Pag

e 26

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Example: Rapidly Compare all DDR4 ADDRESS EyesSymptom: Random intermittent data corruption on DDR4 system

Eye Scan Insight:

Excessive Crosstalk on

ADDR 3-9. Could cause

DRAM to store and retrieve

data from incorrect

addresses. 27

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© Keysight Technologies 28

Signal Integrity Insight: Cross Talk on Some ADDRESS

January 2014

Next Steps:

• Check routing for crosstalk

threats. (missing ground

planes, traces too close to

each other or to noise

source….)

• Use LA triggers, traces,

and DDR Eye Scan to

create additional scans for

further insight.

• Use scope to view victim

and aggressor signals at

different locations on the

bus.

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DesignCon 2016


Increase Insight Into Crosstalk ConditionsUsing DDR Eye Scan Qualification

Eye Scan Insight:

Activate, READ, and Write (not shown) all

result in crosstalk on ADDR3. Precharge

and Refresh do not.

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DDR4 Eye Scan Qualifications Settings to observe affects of adjacent signals on victim.

Victim, ADDR3, must be “x”

(care) in scan qualification,

since it is being scanned.

Eye Scan Insight:

When adjacent signals (ADDR1, 5,12 and BA1) are

transitioning low, crosstalk is seen on ADDR3.

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DesignCon 2016


Scan Qualification on Logic AnalyzerProvides Additional Insight into Cross Talk Issue

ADDR3 transitioning low one clock

cycle after the other ADDR bits

transition low creates the upper

signal path in the scan

ADDR3 transitioning low

simultaneous with other ADDR bits

creates lower signal path.

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DesignCon 2016


Check Crosstalk on Victim ADDR with Scope

32

Probe at different locations along the DDR4 bus

Scope probe

placed before

inductive

coupling on

ADDR 3

Scope probe

placed after

inductive

coupling on

ADDR 3

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DesignCon 2016


Scope Results Confirm Eye Scan Results

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ADDR3 Scope traces triggered on Activate Command

Scope probe placed

before inductive

coupling on ADDR3,

during Activate

command.

Scope probe placed

after inductive coupling

on ADDR3, during

Activate command.

Agenda


– Simulation









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DesignCon 2016


Signal Integrity Insight: Incorrect Signal Transition

Eye Scan Insight

DDR4 Bank group 1

Transitioning incorrectly

Symptom: Data Corruption on DDR4 system

Next Steps:

• SW work around:

– Do not use BG1 = 1

– Limits address space

• Long term: HW fix required

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2 modes for DDR / LPDDR Data - multiple views

• Required to set State mode sampling positions

• Rapid Bus level signal integrity insight

Overlay Mode

• Unique qualified scan views

• Simultaneous views of all DQ and DQS

Signal Trace Mode

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Signal Integrity Insight: DDR4 3500 Mb/s Read Scans

Next Steps:

• Take trace to inspect ODT operation

• Cross trigger scope to check for ISI

Eye Scan Insight:

• Potential ODT setting

issue. Threshold of first

bit in burst has less swing

than remainder of burst.

• Could also be ISI

(inter-symbol interference)

• Overdriving DDR4 DRAM

to 1.4V could cause

damage.

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DesignCon 2016


Signal Integrity Insight: Inter-symbol Interference (ISI)Symptom: READ Data Corruption on DDR4 1600 system

Next Steps:

• Check for ISI with scope

• Review simulations of

READ data. Look closely

at DRAM drivers and

termination.

Eye Scan Insights:

• DDR4 2400 system looks good, no ISI

• DDR4 1600 system exhibits ISI on READ DQ

and DQS.

Eye Scan Settings: Signal trace mode

DDR4 2400 DDR4 1600

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Signal Integrity Insight: Weak DQSDDR4 > 3100 Mb/s DIMM system

Eye Scan Insight:

• DQS2 has less swing

than other DQS

Next Steps:

• Check DQS2 DRAM

drive strength,

termination and trace

routing

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Complementary Solutions - Logic Analyzer and MSO

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Use complementary solutions to debug fasterFeatures Logic Analyzer MSO (Mixed Signal Oscilloscope)

Functional

validation

Complete View all ADD/CMD/DQ/DQS

• Functional Compliance Tests

• Address/command/control and data validation

Partial view

• 16 command and address

(depending on number of digital

channels connected).

Eye diagram

display

• Qualitative bus level signal integrity insight

• Simultaneous eye diagram displays to view all

signals relative to each other.

• No measurement on eye

• Quantitative measurements

• Parametric Compliance Tests

• Eye height and eye width

measurements

Agenda


– Simulation









Page

DesignCon 2016


Tools for DDR4 Design, Debug, and Validation

Design

Simulation Measurement

Correlation

Signal Integrity

Infiniium V-Series Scope

Software Compliance

Applications for all

generations of DDR and

LPDDR memory

M8020 High-Performance

JBERT

Protocol/Bus Level SI

U4164 Logic

Module

Bus level signal

integrity insight

using

B4661A

Memory

Analysis SW

Custom & Standard

Probing & Interposer

Solutions

42

Keysight ADS

Page

DesignCon 2016


Visit Keysight Booth #725 to learn more!

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DesignCon 2016


DDR4 DIMM Interposers

Ease of connection

Direct connect to U4164A

Low profile - Minimal loading

Support UDIMM or RDIMM

Timing and State analysis

Support DDR Setup Assistant and

DDR Eye Scan

FS2514: DDR4 DIMM satellite interposer for signals unique

to 2nd DIMM in a channel (not shown)

FS2510AB

Proven DDR4 4 Gb/s simultaneous Read

and Write capturewith FS1070 conversion kit

FS2512: DDR4 SODIMM interposer

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U4164A Logic Analysis System Solution for DDR4 DIMM

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• U4164A logic analyzer modules • Qty (3) with option -02G for all

ADD/CMD/DQ above 2500 Mb/s.

• Qty (2) with option -01G for all

ADD/CMD/DQ below 2500 Mb/s.

• M9505A chassis

• M9536A embedded controller

• FS2510AB DDR4 DIMM

Interposer (with FS1070 kit for

DDR4 > 2.5Gb/s)

• B4661A Memory Analysis SW• B4661A -1XX DDR Decoder

• B4661A -3XX Compliance Analysis

• B4661A -4XX Performance Analysis

Proven DDR4 capture of all ADD/CMD/DQ at 4 Gb/s

U4164A system configuration for

DDR4 DIMM debug and validation

LA system configurations vary for DDR2/3/4 and LPDDR/2/3/4

technologies and probing use models.

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U4164A System Solution for DDR4 x4/x8 or x16 DRAM systems

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• U4164A logic analyzer module• Qty(1) with option -01G up to 2500 Mb/s

• Qty (1) with option -02G > 2500 Mb/s

• M9502A chassis

• PC host with PCI express adapter

and cable

• U4208A left ZIF probe/cable

• U4209A right ZIF probe /cable

• W4641A DDR4 x16 BGA Interposer

(shown on left)

Or

• W4643A x4/x8 BGA interposer

(not shown)

• B4661A Memory Analysis SW• B4661A -1XX DDR Decoder

• B4661A -3XX Compliance Analysis

• B4661A -4XX Performance Analysis

U4164A system configuration for DDR4 BGA probing and trace capture.

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U4164A State Speed Options

Required state speed optionU4164A Base: 350 MHz Clock

Option -700: 700 MHz

Clock

Option -01G: 1.4GHz Clock,

Option -02G: 2.5 GHz clock

DDR/DDR2 < 700 Mb/s

DDR3

< 1400 Mb/s

< 2500 Mb/s

> 2500Mb/s

DDR4 < 2500 Mb/s

> 2500Mb/s

LPDDR < 700 Mb/s

LPDDR2 < 1400 Mb/s

LPDDR3< 1400 Mb/s

< 2500 Mb/s

LPDDR4< 2500 Mb/s

> 2500Mb/s

For Capture of DDR/LPDDR Memory ADD/CMD/DATA

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Benchtop 16854A Logic Analyzer State Speed Options

Required state speed option16854A:

350 MHz Clock Option -700:

700 MHz Clock

DDR/DDR2 < 700 Mb/s

DDR3 < 1400 Mb/s

LPDDR < 700 Mb/s

LPDDR2 < 1400 Mb/s

LPDDR3 < 1400 Mb/s

Capture of DDR/LPDDR Memory ADD/CMD/DATA

Requires SW version 6.20 or higher for DQ capture.

Refer to 16850A series logic analyzer data sheet for channel count. 48

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Contact Keysight

MemCon Aug 6, 2013

Product Selection and Configuration Assistance,

Education and Training

US phone: 1 800 829-4444 Press # then 2

Hours: 8:00am – 8:00pm ET, Mon - Fri

For more information on Keysight Technologies’ products, applications or

services, please contact your local Keysight office. The complete list is

available at:

www.Keysight.com/find/contactus

49

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ddr4 bus level signal integrity insight

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