dead time pwm
DESCRIPTION
TRANSCRIPT
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ELIMINATION OF DEAD TIME IN PWM CONTROLLED INVERTERS
Presented by:Priyambada priyadarshini sahooReg.No:0901106039Branch: Electrical Engineering
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OUT LINE 1.what is dead time. 2.effect of dead time
3.principle of dead time elimination
4.implementation method
5.conclusion
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WHAT IS DEAD TIME
• To avoid shoot through in pwm controlled vsi a blank time is
introduced
• In this period both upper and lower switches in a phase leg are off
• So that short circuit can be avoided and switches are not damaged due to high current
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single phase half bridge vsi
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Dead time varies with 1.devices 2.output current 3.temperature
which makes the compensation less effective at low output Current & low frequency
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EFFECT OF DEAD TIME
one leg of the inverter single phase full bridge
inverter
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Considering one leg of the inverter the effect of blanking time is given in below figure.
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Comparing the ideal waveform of VAN without blanking time to actual waveform with blank time the difference between ideal & actual output voltage is Vϵ=(VAN)ideal-(VAN)actual
By averaging Vϵ over one time period Ts change in output voltage due to t∆(drop is taken positive)
In leg B of the inverter recognizing that iA= -iB
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Since Vo=VAN-VBN & io=iA the instantaneous average value of the voltage difference that is the average value during one period of the idealized waveform minus the actual waveform is
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Plot of instantaneous average value Vo as a function of Vref
effect of blank time on sinusoidal output
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PRINCIPLE OF DEAD TIME ELIMINATION
A generic phase leg of VSIs.
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•Current flowing out of the phase leg is considered as
positive here
• Dead time is not required for p or N switch cells because
both the cells are configured with a controllable switch in
series with a uncontrollable diode
•Gate control signal is selected to gate on or gate off upper
device Kp or lower device Kn only
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CONTROL SCHEMES
Dead-time elimination control schemes
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• Determination of load current direction is key for dead time
elimination
• It can be detected by operating status of switches & their anti parallel diodes instead of expensive current sensors
• Gate signal level is for determination of operating status of switches
• Diode-conducting detection(DCD) circuit is for determination of status of anti parallel diode
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•If D1 is ON the comparator o/p is low, D0 light up otherwise it is OFF
Diode-conducting detection(DCD) circuit
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SIMULATION RESULTS
H-bridge voltage source inverter
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•Load is 8mH inductor & 2.4 ohm resistor
•Vdc is 250v
•Inverter is controlled by unipolar sinusoidal pwm
•Switching frequency 10KHz
•Fundamental frequency of o/p voltage is set to 60Hz
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Simulated output current waveforms with MI=0.2
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Comparison of o/p current with 2 usec dead time & without dead time
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IMPLEMENTATION METHODS
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•Two IGBT modules with a load of 8mH &2.4 ohms resistor
•Four DCD ckts to detect anti-parallel diodes Dap,Dan,Dbp & Dbn diode
•Output signals of diodes Cap,Can,Cbp,Cbn are fed back to a complex programmable logic device(CPLD)
•DSP sends two PWM signals Sa & Sb CPLD
•gate signals are achieved by optic electrical interface unit
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conclusion
•Compared to conventional PWM control with dead time this method reduces output distortion
•Regains rms value
•Low cost DCD circuits ,simple logic & flexible implementation
•Avoids using expensive current sensors
•Attractive option for VSI applications
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REFERNCES
1.http://www.ee.bgu.ac.il/~pedesign/Graduate_problem_papers/papers2007/PWM_Deadtime.pdf
2.Power electronics converters, applications & design Ned Mohan Tore M. Undeland William P. Robbins
3.Power electronics Dr. P.S. Bimbhra
4.Power electronics Principles & applications Joseph Vithayathil
5.Power electronics M.H.Rashid
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THANK YOU