dealing with igbt modules

1

Dealing with IGBT ModulesDealing with IGBT Modules

2

Table of Contents

Motivation

Low inductive DC-link design

Choice of right Snubber

Gate Clamping

Thermal management

Paralleling – Application of driver circuit

Paralleling – Low inductive AC-Terminal connection

Usage of single switch “GA” type modules

Conclusion

Dealing with IGBT Modules

3

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


4

Dependence of VCE, IC, Pv, Eswitch

vCE(t)

iC(t) VCC

IO

0t

0

t1

0t

pv(t)iC

vCE

( )∫ ⋅=

t2

t1

vswitch

dt

tpEt2

CE

Cv vip ⋅=

5

Influence of switching speeds

Increased switching speed, decreases the switching losses Eswitch

But, leads to increased di/dt and therewith to higher over voltages

vCE(t)

iC(t) VCC

IO

0t

t1

0t

pv(t)

t2

Eswitch

vCE(t)

iC(t) VCC

IO

0t

t1

0t

pv(t)

t2

Eswitch

dt

diLv s

tray

×−=

di/dt

6

Porsche 911 - 2004

Porsche Diesel - 1960

Would you use these different vehicles with

the same driver and in the same environment?

Motivation

7

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


8

Why low inductive DC-link design?

Due to stray inductances in the DC link, voltage overshoots occur

during switch off of the IGBT:

These voltage overshoots may destroy the IGBT module because they are added to the DC-link voltage and may lead to VCE > VCEmax

With low inductive DC-Link design (small Lstray) these voltage overshoots can be reduced significantly.

Motivation

dt

diLv strayovershoot ×=

linkDCovershootCE vvv −+=

9

Lstray = 100 nH

Low Inductance DC-link Design

The comparison of stray inductances show Inside the module SEMIKRON reduced the inductances significantly

Outside the module the reduction of stray inductances is necessary, too

Lstray = 20 nH

10


The mechanical design has a significant influence on the stray inductance of the DC-link The conductors must be paralleled

Lstray = 100 %

Lstray < 20 %

loop

1 cm² ≈ 10 nH

11


The mechanical design has a significant influence on the stray inductance of the DC-link The connections must be in line with the main current flow

Lstray = 100 %

Lstray = 30 %

remaining loop

12


The mechanical design has a significant influence on the stray inductance of the DC-link Also the orientation must be taken into regard

Lstray = 100 %

Lstray = 80 %

+-

+-

13


+ bus bar - bus bar

Simulation of current distribution for the case of Lstray = 80 %

14

The mechanical design has a significant influence on the stray inductance of the DC-link A paralleling of the capacitors reduces the inductance further


Lstray = 100 %

Lstray = 50 %

15

For paralleling standard modules a minimum requirement is DC-link design with two paralleled bars


16


17

Paralleled half bridge IGBT modules


++

--~

18

SEMIKRON 3 Phase and Low Inductance Inverter

DC-link

Snubber

Capacitor

3 x

2 x IGBT parallel

Heat Sink

Fan

Driver

Apple

19

-+

-+

-+

-+

-+-+

2 IGBT Moduls

Capacitor

Low inductive solution


Comparison of different designs Two capacitors in series

Two serial capacitors in parallel

-+

-+-+

-+

-+-+

2 IGBT Moduls

Capacitor

+

+-

-

+++

Typical solution

loop

parallel

current paths

20

Low Inductance DC-link Capacitors

Lstray = ?

Ask your supplier!

Also the capacitors have to be decided Capacitors with different internal stray inductance are available

Choose a capacitor with very low stray inductance!

Further: low “ESR” Equivalent Series Resistance

High “IR” Ripple Current Capability

21

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


22

Motivation

Why use a snubber?

Due to stray inductances in the DC link, voltage overshoots occur

during switch off of the IGBT:

These voltage overshoots may destroy the IGBT module because they are added to the DC-link voltage and may lead to VCE > VCEmax

The snubber works as a low pass filter and “takes over” the voltage overshoot (caused by the energy which is stored in the stray inductances)

dt

diLv strayovershoot ×=

linkDCovershootCE vvv −+=

23

Snubber Networks

Different snubber networks are in use

a) b) c) d)

24

Snubber Networks

SEMIKRON recommends for IGBT applications: Fast and high voltage film capacitor (“MKP” / “MFP”) as snubber

parallel to the DC terminals

Not to increase Lstray, the snubber must be located directly at terminals of the IGBT module

DC-link Snubber

25

Not Sufficient Snubber Capacitors

But still: the snubber networks need to be optimised The wrong snubber does not reduce the voltage overshoots

Together with the stray inductance of the DC-link oscillations can occur

IGBT switch off

(raise of VCE )

before optimisation

Voltage overshoot

Oscillation

26

Determination of a snubber capacitor

Influence of DC-link stray inductance and snubber capacitor stray inductance

0

0

IGBT-switch-of f .xls

VCE

t

∆V1

VDC

∆V2

dtdiLΔV Csnubberstray1 ×= −

dtdiΔVLC

1snubberstray =

−

iC = operating current

diC/dt = turn off

snubber

2CbusDCstray2

2 CiL

ΔV×

=−−

2C

snubber22

busDCstray iCΔVL ×

=−−

27

Not Sufficient Snubber Capacitors

These capacitors did not work satisfactory as snubber:

28

Available Snubber Capacitors

good

From different suppliers different snubber capacitors are available.

In a “trial and error” process the optimum can be find, based on measurements.

The different snubber capacitors have different stray inductance values. Again it is necessary to find one with lowest inductance.

better

29

Optimal Snubber Capacitor

After introduction of optimised snubber capacitor: Significantly reduced voltage overshoots

No oscillations

IGBT switch off

(raise of VCE )

after optimisation

Voltage overshoot

No oscillation

30

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


31

Gate Clamping

Over voltages at the gate VGE > +/- 20 V can occur due to Induction at stray inductances

Burst impulses by EMC

The introduction of an additional gate clamping is necessary Close to the gate terminals, what means ≤ 5 cm

Use twisted pair wiring

-20 V ≤ VGE ≤ +20 V

32

Gate Clamping

Gate clamping with “RGE” from gate to emitter potential Keeps gate potential always on defined level – also when supply

voltage of the driver drops

Prevents charging of the gate, for highly resistive driver outputs

Only RGE is not sufficient for gate clamping. (See the following charts.)

VGE

33

Gate Clamping

Gate clamping with “Schottky Diode” from gate to supply voltage of driver On driver board (distance to module ≤ 5 cm, twisted pair wires)

Additional “RGE“ is recommended

VGEV+ supply

34

Gate Clamping

Gate clamping with “Zener Diode” or “Avalanche Diode” from gate to emitter potential On driver board (distance to module ≤ 5 cm, twisted pair wires)

Or on auxiliary PCB

Parallel “RGE“ is recommended

VGE

35

Gate Clamping

Auxiliary PCB directly at the IGBT module The additional RGE ensures off-state of IGBT in case of failed wiring

RGoff

RGon

RGE

Z-diode

RGoff

RGon

RGE

Z-diode

36

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


37

Thermal Management

Taking thermal management into regard No space between the paralleled modules lead to low stray

inductances and minimum space

But the thermal stacking makes a current derating necessary

38

Thermal Management

20 – 30 mm space between the modules increase the inductances but

reduces the thermal resistance to the heat sink significantly

Optimised thermal management leads to maximum possible current ratings

39

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


40

Worst Case: All Contacts Shorted

Different IGBT modules with different Switching speeds ton and toff

Gate thershold voltages VGE(th)

Gate charge characteristic VGE = f(QG) and „Miller Capacity“ Cres

Transfer characteristic IC = f(VGE)

C

AE

G

EVGE VGE VGE

Due to hard connected gates, all IGBTs must have the same VGE

This means: all IGBTs do not switch independently from each other

41

Hard Connected Gate with Common Resistor

VGE

t

∆∆∆∆t1

∆∆∆∆VGE(th)

Hard connected Gates

All IGBTs have different gate threshold voltages ∆∆∆∆ VGE(th)

IGBT1, with the lowest VGE(th) turns on first.

The gate voltage is clamped to the Miller-Plateau. Therefore IGBT’s

with higher VGE(th) can not turn on. They turn on only after ∆∆∆∆t1.

The IGBT1 with low VGE(th) takes all the current and switching losses during turn on.

On going process by negative thermal coefficient of VGE(th)

VGE

t

∆∆∆∆t1

∆∆∆∆VGE(th)

VGE

t

∆∆∆∆t1 1

∆∆∆∆VGE(th)

∆∆∆∆t1 n

42

C

AE

G

E

Introduction of Gate Resistors

Separated by gate resistors The gate voltage of each IGBT can rise independent from the other

one.

Note: The gate resistors must be tolerated < 1 %

VGE 1

With individual gate resistors all IGBTs are independent from each other

VGE 2 VGE n

43

Introduction of Gate Resistors

VGE

t

∆∆∆∆t2

∆∆∆∆t1

∆∆∆∆VGE(th)

Separated by gate resistors All IGBTs still have different gate threshold voltages ∆∆∆∆VGE(th)

But: The gate voltage of each IGBT can rise independently from the other ones.

The higher Miller-Plateau will be reached after a short time ∆t1. Only small

differences in current sharing and switching losses between paralleled IGBTs.

44

Worst Case: All Contacts Shorted

Taking stray inductances into regard Due to hard connected gates and varying transfer characteristics, all IGBTs

have different switching times and speeds; dix/dt varies in each leg

The circuit also has different stray inductances; Lx

Therewith vx = Lx x dix/dt varies in each leg (e.g.: 1000 A/µs x 10 nH = 10 V)

Nearly unlimited equalising currents i flow also via the thin connecting wires

Oscillations between parasitic capacitances (semiconductors) and -inductances are not damped.

V1 V2 Vn

i = ∞

C

AE

G

E

45

C

AE

E

G

Introduction of Auxiliary Emitter Resistors

The introduction of REx (≈ 10 % of RGx but min. 0,5 Ω) leads to Limitation of equalising currents i ≤ 10 A

Damping of oscillations

V1 V2 Vn

i ≤ 10 A

RE1

RE2REn

46

C

AE

E

G


The introduction of REx leads also to a negative feedback: The equalising current i leads to a voltage drop VREx at the Emitter

resistors REx

i

VRE1VRE2

fast IGBT slow IGBT

47

C

AE

E

G


The introduction of REx leads also to a negative feedback: The voltage drop VRE1 reduces the gate voltage of the fast IGBT and

decreases therewith its switching speed.

The voltage drop VRE2 increases the gate voltage of the slow IGBT and

makes it faster.

During switch off: vice versa.

i

fast IGBT slow IGBT

VRE1 VRE2

48

Additional Proposals

The introduction of Shottky-Diodes parallel to REx

helps to balance the emitter voltage during short circuit case.

Dimensioning ≈ 100V, 1A.

This circuit is patented by SEMIKRON,

but SEMIKRON customers are allowed to use it together with SEMIKRON power semiconductor modules.

49

Additional Proposals

The introduction of clamping diodes prevents over voltages at the gate contacts.

Therefore these clamping diodes must be placed very close to the module connectors

C

AE

E

G

50

Conclusion

Balanced switching behaviour Independent switching due to introduction of RGx

Balanced switching speeds due to negative feedback be introduction of REx

Limitation of equalising currents

Damping of oscillations

Prevention of gate over voltages

Refer also to “SEMIKRON Application Manual - Power Modules” German

English

Chinese

Korean

Japanese

Russian (on internet only)

51

Additional Parallel Board

PCB for paralleling IGBT close to the module connectors

Same track length on the board

Short, twisted pair wires from the board to the modules (≤ 5 cm)

RGon

RGoff

RERGon

RGoff

RE RGoff

RGon

RE RGoff

RGon

RE

52

Additional Parallel Board

Top Bot

IGBT Driver

53

Auxiliary Printed Circuit Board

Auxiliary PCB directly at the IGBT module The additional RGE ensures off-state of IGBT in case of failed wiring

Same track length on the board

Short, twisted pair wires from the main driver to the auxiliary PCB at the IGBT module

RGoff

RGon

RGE

Z-diode

RERGoff

RGon

RGE

Z-diode

RE

54

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


55

Motivation

Why symmetrical AC terminal connection for paralleled IGBTs? When the connection between the AC terminals have high inductance and

different inductances, the current sharing of IC (output current) will be

inhomogeneous and oscillations may occur.

This would make a current derating necessary.

0 50.00u10.00u 20.00u 30.00u 40.00u

-50.0

200.0

0

50.0

100.0

150.0

Simulation of 4

paralleled IGBT modules with

inhomogeneous current sharing

leads to oscillations

IC

t

56

Why symmetrical AC terminal connection for paralleled IGBTs? The sketch shows that Lstray,DC and Lstray,AC are connected in series

This makes clear why both have to be reduced and both have to be

symmetric in each leg

to ensure even current distribution

to avoid oscillations

Symmetrical AC Connection

C

G

E

57

AC link design Short connections with identical current path length for each module

Wide and thick bars

Flexible interconnections for large systems might be necessary to compensate differences in thermal expansion

‘Long hole drillings' can compensate mechanical tolerances

Symmetrical AC Connection

Look for a symmetric AC-connection so that the current sharing will be even over all modules

Isolated supporting poles

take over vibrations and forces from heavy AC cables

58

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


59

Optimisation problem In order to optimise the thermal management it seems to be be useful

splitting the current of one half bridge topology into two modules.

The question is: what is better – use two paralleled half bridges, or two single switches in series connection?

Motivation

-

~

+1

2

3

1

2

3

-

+

~

1

1

2

2

?

60

How to parallel half bridge IGBT modules

Paralleling of GB modules

-

~

+1

2

3

1

2

3-

+

~

1 1

2 2

3 3

61

How to use single switch IGBT modules as half bridge

Paralleling of GA modules

-+

~

1

2

2

1

-

+

~

1

1

2

2

62

Influence of switching speeds

Increased switching speed, decreases the switching losses Eswitch

But, leads to increased di/dt and therewith to higher over voltages

vCE(t)

iC(t) VCC

IO

0t

t1

0t

pv(t)

t2

Eswitch

vCE(t)

iC(t) VCC

IO

0t

t1

0t

pv(t)

t2

Eswitch

dt

diLv s

tray

×−=

di/dt

63

Comparison For GB modules the diodes for commutation are placed in the same

module. Therewith the stray inductance is as low as possible.

Paralleled GB modules allow higher switching speeds

GA or GB?

-+

~

1

2

2

1

-

~

+1

2

3

1

2

3

64

Comparison In half bridge modules the snubber capacitors can be placed closed to

the terminals with short - and therewith low inductive connections. So that the snubbers work very efficient.

Paralleled GB modules allow higher switching speeds

GA or GB?

65

Advantages of paralleled half bridges

The current per module is only 50 % of the maximum current

The di/dt is much reduced, therewith the voltage overshoot is small (v = - L x di/dt)

The half bridge module has much lower stray inductances, what reduces the voltage overshoot again

Snubber capacitors can be placed very close to the terminals, so that they work very efficient

The switching speed can be increased and therewith the switching losses are reduced

SEMIKRON recommends the use of paralleled half bridge modules instead of single switch modules

Conclusion

66

SEMIKRONs recommended solution

67

Table of Contents

Motivation



Gate Clamping

Thermal management




Conclusion


68

Conclusion

When using latest generations of IGBT modules it is recommended and advantageous to

Do a low inductive (“sandwich”) DC-link

design

Decide for low inductive DC-link capacitors

Optimise the snubber capacitors

Optimise thermal management which leads to maximum possible current ratings


69

Conclusion

For paralleled modules The driver must be powerful enough

Some additional components are necessary (e.g. REx) and must be

located close to every single module

The DC- and AC connection must be symmetric and low inductive


70

Thank you very much for your attention

Refer also to “SEMIKRON Application Manual - Power Modules”

71

Document status: preliminary

Date of publication: 2006-04-04

Revision: 1.3

Prepared by:Christian Daucher

With assistance from

Dr. Arendt Wintrich

Norbert Pluschke

Information furnished in this document is believed to be accurate and reliable. However, no representation or warranty isgiven and no liability is assumed with respect to the accuracy or use of such information. Furthermore, this technicalinformation specifies semiconductor devices but promises no characteristics. No warranty or guarantee expressed orimplied is made regarding delivery, performance or suitability. Specifications mentioned in this document are subject tochange without notice. This document supersedes and replaces all information previously supplied and may besupersede by updates.

72

IGBT modules are ESD sensitive devices.

Thus they will delivered with a short circuit connection between gate terminal and auxiliary emitter terminal

Remove this connection and handle the modules only when it is assured, that the environment is ESD proof

Additional

dealing with igbt modules

Documents

dclink voltage

dc terminals dclink

low stray inductance

dclinkthe conductors

dclinkthe connections

lstray dt

snubber parallel

paralleled lstray