dell d430 la-3741p service manual

AA

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title

Size Document Number Rev

Date: Sheet o fLA-3741P 0.1Cover Sheet

1 53Friday, January 26, 2007

Compal Electronics, Inc.

COMPAL P/N :PCB NO :

COMPAL CONFIDENTIALMODEL NAME : JAU00 Carson Schematics Document

uFCBGA Mobile Merom-ULV

REV : 0.1 (DELL: X00)

DELL CONFIDENTIAL/PROPRIETARY

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOTBE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRDPARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.

LA-3741PDA800008W0L

Intel Calistoga-GMS + ICH7M2007-01-24

330 uf Poly Cap ; P/N : SGA00001P0L220 uf Poly Cap ; P/N : SGA00002D0L

POP 2@ ; 220 uf for Dual core220 uf Poly Cap ; ( P/N : SGA00002D0L)

POP 2@ ; 10 uf for Dual core10 uf MLCC Cap ; P/N (SE160106M8L)

HW POP option control table

10 uf MLCC Cap ; P/N (SE00000110L)22 uf MLCC Cap ; P/N (SE160106M8L)

BOM No.

01 BOM 02 BOM

Speed/power 1.06G , 9W1.2G ,9W

CPU Type

CPU P/N

Dual core

10 uf

C694,C697,C37,C39,C22C698,C693,C25,C40,C35C699,C700,C30,C33,C27C703,C704,C38

C41,C44 220 uf 220 uf

C42,C43

10 uf

POP 4@ ; For with TAA Board

Location: U2

C21,C26,C29,C31C34,C36,C28,C23

JP3

Dual core

SA00001MA1L SA00001ND0L

U50 POP 1@ ; For without TAA Board

SA00001ND0L

Pop

Depop

Pop Pop

Pop Pop

45148731L01 45148731L02 45148731L03 45148731L04

SA00001MA1L

Dual core Dual core

1.06G , 9W1.2G ,9W

03 BOM 04 BOM

220 uf 220 uf

Pop Pop

10 uf 10 uf

Pop Pop

Depop

Depop DepopPop

Pop Pop

Part Number DescriptionDA800008W0L PCB 02F LA-3741P REV0 M/B

MB PCB

AA

B

B

C

C

D

D

E

E

1 1

2 2

3 3

4 4

Title


Date: Sheet o fLA-3741P 0.1Block Diagram



Clock Generator

uFCBGA CPU

INTEL

DMI

H_D#(0..63)H_A#(3..31)

Compal confidentialModel : HAU30

AMP & INT.Speaker

Pentium-M

Block Diagram

Azalia Codec

Power On/OffSW & LED

System Bus

INTEL

Memory BUS(DDR2)

FSB 400/533 MHz

+1.5V_RUN 100MHz

+1.8V_SUS 400/533MHz

48MHz

ATA100

MDC

998pin BGA

SLG84450VTR

STAC9200

Azalia I/F

Calistoga-GMS

ICH7-M

RJ11

HeadPhone &MIC Jack

PATA HDD+3.3V_HDD +VDDA

+5V_SUS +3.3V_RUN

+1.8V_SUS+1.5V_RUN

+1.05V_VCCP

+VCC_CORE+1.05V_VCCP

+3.3V_RUN

BANK 2, 3DDRII-DIMM X1

+0.9V_DDR_VTT+1.8V_SUS

Cable

+3.3V_SUS

479pin

DC/DC Interface

CPU ITP Port

+FAN1_VOUT Merom-2M ULV

+3.3V_RUN+2.5V_RUN

+3.3V_RUN

VCORE (IMVP-6)

1.5V/1.05V

CHARGER

1.8V/0.9VBATT IN

DC IN

3V/5V/15V

GUARDIANEMC4000

Thermal

+3.3V_SUS

FAN

Power Sequence


652pin BGA

pg 7,8pg 18

pg 18pg 6pg 7

pg 10,11,12,13,14

pg 22,23,24,25

pg 48

pg 26 pg 27

pg 34

pg 49

pg 50

pg 45

pg 46

pg 47pg 42,43pg 44

pg 45

pg 28 pg 28

pg 15

+3.3V_ALWpg 41

Int.KBD &Stick

SMSC KBC

+3.3V_ALW+RTC_CELLMEC5004

pg 40

pg 41

SPI

LPC BUS+3.3V_RUN33MHz

SMSC SIO

+5V_RUN

+3.3V_ALW

Touch Pad

ECE5018pg 39

USB[1]

USB Ports X1+5V_SUS pg 33USB[6] REAR

HUB USB[1]

HUB USB[2]

pg 40pg 37FIR

DOCKINGBUFFER

pg 37

DOCKING PORT

pg 38 pg 31,32

PCI BUS

CardBus & 1394 & SDR5C843 CSP208

+3.3V_RUN 33MHzIDSEL:AD17(PIRQB,C,D#,GNT2#,REQ2#)

+3.3V_RUN+3.3V_SUS

HUB USB[2]USB[0]

Mini Card2+3.3V_RUN

WLANMini Card 1+3.3V_RUN

PCI Express BUS

+1.5V_RUN+1.5V_RUN pg 29

GIGA Enthernet

+3.3V_LAN

+3.3V_RUN/ +1.5V_RUN 100MHz

pg 36

BCM5752WWANpg 36

HUB USB[1]

USB[7]

Bluetooth+3.3V_RUN

HUB USB[4]

Stick

INT MIC+5V_SUS

+1.05V_VCCP

+3.3V_RUN+3.3V_SUS+1.5V_RUN

pg 34

SPI

+5V_RUN

+3.3V_RUN

pg 16,17

DDRII 1GB on Board+0.9V_DDR_VTT+1.8V_SUS

pg 19LVDSLVDS CONNRGB

pg 20DVODVI Bridge SI1362

CRT CONNpg 21

TV

DVI

PWR USB X1+5V_SUSUSB[5] REAR

SD card SLOT

1394 CONNCard Bus SLOT

IDSEL:AD24(PIRQA#,GNT0#,REQ0#)

pg 30

RJ45

LAN SWITCHPI3L500E

pg 30

Transformerpg 30

+3.3V_LAN

+2.5V_LOMpg 30

+3.3V_LAN+3.3V_LAN

SIM Cardpg 36+SIM_PWR

+DOCK_PWR_SRC+3.3V_RUN+2.5V_LOMpg 32+SD_VCC

pg 31pg 32

+3.3V_RUN+1.8V_RUN

+LCDVDD+GFX_PWR_SRC

pg 33DH_PORT_PWRSRC

USB Ports X1+5V_SUS pg 33

USB[4] REAR

ST M25P80

+2.5V_RUNpg 18

Smart Card+5V_RUN pg 35OZ77C6

HUB_USB[3]

SLOT

pg 51

pg 35pg 41Fingerprint

+3.3V_RUN

USB_BIO

+5V_RUN

+1.05V_VCCP

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet o fLA-3741P 0.1Index and Config.



PIRQ

B,C,D

+1.05V_VCCP

PM TABLE

ON

ON

AD17

OFF

PCI DEVICE

TABLE

CARD BUS

IDSEL

S0

TABLE

2

PCI

ON

ON

S3

USB

ON

OFF

ON

+3.3V_SUS

OFF

+5V_SUS+5V_ALW

S1

S5 S4/AC don't exist

+1.8V_RUN

+VCC_CORE

REQ#/GNT#

+5V_RUN

ON

powerplane

+3.3V_RUN

S5 S4/AC

ON

ON

+3.3V_ALW

State

OFFOFF

OFF

+1.5V_RUN

0

4,6

7

USB PORT# DESTINATION

PWR USB

1 USB Hub (5018)

Docking

Blue tooth2

Tolerance0.1U_0402_6.3VXX

Ceramic Capacitors :

Temperature CharacteristicsRated VoltagePackage SizeValue

CHA

Capacitor Spec Guide:

1

SL

CODE

COG SJ9

B

+-3%

CODE

Symbol F

+40,-20%+-20%

4

G

+20,-10%

X

UK

5

B

Z

C

+-0.05PF

Y5V

Temperature Characteristics:

Y5P

CK

V

+-0.1PF

X5R

A

Z5U

BJ

+100,-0%

Y5U X7R

P

+-30%

C

SH8

H

CJ

+30,-10%

K

+-5%

7

Q

+80,-20%

6

+-0.5PF +-1PF

Z5V

+-10%

J

+-0.25PF

Tolerance:

+-2%

N

D

Z5P2

UJ

D E F G

H I J

30Symbol

X6SNPO

KX5S

M

ValuePackage SizeRated VoltageToleranceLow ESR Mark : 45 m ohm

10U_D2_10VX_R45

Tantalum or Polymer Capacitors :+0.9V_DDR_VTT

@XX : Depop componentNOTE1:

+1.8V_SUS



1

2

USB HUB DESTINATION

4

3

PC Card BayMini 1(WWAN)

Mini 2(WLAN)

N/A

+2.5V_RUN

REAR

SMART CARD

5

DOCKING AD24 0 A

USB HUB onOZ77C6LN

DESTINATION

DP_HUB Fingerprint

+15V_SUS

3 N/A

+3.3V_SRC

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet o fLA-3741P 0.1Power Rail



+5V_ALW

+5V_SUS

BATTERY

+PWR_SRC

+3.3V_SRC

+3.3V_ALW

+3.3V_RUN

ADAPTER

S

U

S

_

O

N

R

U

N

_

O

N

+5V_RUN VDDA

A

U

D

I

O

_

A

V

D

D

_

O

N

(

O

p

t

i

o

n

)

+15V_SUS

+2.5V_RUN

TPS51120

EMC4000

R

U

N

_

O

N

PL8

L47

793475

FDS4435 +GFX_PWR_SRCRUN_ON

SI4800



SI3456

E

N

A

B

_

3

V

L

A

N

+3.3V_LAN

ALWON

ALWON

SI4800

S

U

S

_

O

N

+VCC_CORE

R

U

N

P

W

R

O

K

+VCCP

SI3456

+1.5V_RUN

R

U

N

_

O

N

SC483

+1.8V_SUS

R

U

N

_

O

N

R

U

N

P

W

R

O

K

AD3207 SC480

+1.8V_RUN

R

U

N

P

W

R

O

K

S

U

S

P

W

R

O

K

_

5

V

+0.9V_DDR_VTT

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Title


Date: Sheet o fLA-3741P 0.1SMBUS TOPOLOGY



CLK GEN.

Macallan IV

ICH7-M

DAT_SMB +3.3V_ALW

CLK_SMB

GUARDIAN

ICH_SMBDATA

+3.3V_SUSICH_SMBCLK

SIO

PBAT_SMBCLK

PBAT_SMBDAT +3.3V_ALWBATTERYCONN

CHARGER


DIMM1

DDR II 1G ON Board


+3.3V_SUS

2N7002

2N7002

+3.3V_RUN

2.2K 2.2K 2.2K 2.2K

CLK_SCLK

CLK_SDATA

10K

SMBUS Address [A0]

SMBUS Address [A2]

195

197

B22

C22

17

16

5

6

7

8

SMBUS Address [D2]

SMBUS Address [2F]

+3.3V_ALW

8.2K8.2K

100

100

SMBUS Address [16]

SMBUS Address [12]

3

4

910

8

7

WWAN

SMBUS Address [TBD]

3032

WLAN

3032

SMBUS Address [TBD]

SBAT_SMBDAT111

112+3.3V_ALW

+3.3V_ALW

SMBUS Address [58]5

6SBAT_SMBCLKInverter INV

8.2K 8.2K

10K 10K

SMBUS Address [C4, 72, 70, 48]DOCK_SMB_CLK

+5V_ALW10

+5V_ALW

DOCKING9 DOCK_SMB_DAT39

40

5752MLOM

C8C7

SMBUS Address [C8]

SMBUS Address [5A]Power USBDOG house

10K

+3.3V_ALW

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CPU_ITP#

CLK_CPU_ITP

CLK_CPU_ITP#

CPU_ITP

H_STP_CPU#

H_STP_PCI#

CLK_MCH_BCLK#MCH_BCLK#

CPU_BCLK

CLK_CPU_BCLK#CPU_BCLK#

CLK_CPU_BCLK

+CK_VDD_A

+CK_VDD_MAIN

CLK_XTAL_IN

FSA

CLK_CPU_BCLK#

CLK_CPU_BCLK

CLK_MCH_BCLK

CLK_MCH_BCLK#

CLK_CPU_ITP#

CLK_CPU_ITP

CLK_PCIE_LOM#

CLK_PCIE_LOM

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_PCIE_ICH#

CLK_PCIE_ICH

ICH_SMBDATA

ICH_SMBCLK

CLK_SDATA

CLK_SCLK

FSC

CLK_ICH_48M FSA

CLK14M_REFCLK_ICH_14MCLK_SIO_14M

CLK_ENABLE#

CLKIREF

CLK_SDATA

CLK_SCLK

FCTSEL1

FCTSEL1

CLK_PCIE_MINI2#

CLK_PCIE_MINI2

CLK_MCH_BCLKMCH_BCLK

PCIE_MINI2

CLK_PCIE_MINI2#

CLK_PCIE_MINI2

PCIE_MINI2#

CLK_PCI_SIO

CLK_PCI_ICH PCI_ICH

CLK_SMCARD_48M

CLK_PCI_5004

PCIE_ICH

PCIE_ICH#

CLK_PCIE_ICH

CLK_PCIE_ICH#

PCIE_MINI1

PCIE_MINI1#

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

+CK_VDD_REF

+CK_VDD_48

+CK_VDD_48+CK_VDD_A +CK_VDD_REF

CLK_XTAL_OUT

MCH_DREFCLK# DOT96#

DOT96MCH_DREFCLK

DOT96_SSC

DOT96_SSC#

DREF_SSCLK#

DREF_SSCLK

MCH_DREFCLK#

MCH_DREFCLK

CLK_PCIE_LOMPCIE_LOM

CLK_PCIE_LOM#PCIE_LOM#

MCH_3GPLL CLK_MCH_3GPLL

CLK_MCH_3GPLL#MCH_3GPLL#

CLK_PCI_LOM PCI_LOM

CLK_PCI_PCCARD PCI_PCCARD

PCI_DOCKCLK_PCI_DOCK

CLK_SD_48M

+CK_VDD_MAIN

+CK_VDD_MAIN2

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

H_STP_CPU#

H_STP_PCI#

CLK_MCH_BCLK#

CLK_MCH_BCLK

CLK_CPU_BCLK#

CLK_CPU_BCLK

CLK_CPU_ITP

CLK_CPU_ITP#

CLK_ICH_14MCLK_SIO_14M

CLK_PCIE_MINI2

CLK_PCIE_MINI2#

CLK_PCI_SIO

CLK_PCI_ICH

CLK_SMCARD_48M

CLK_PCI_5004

CLK_ICH_48M

CLK_PCIE_ICH#

CLK_PCIE_ICH

CLK_PCIE_MINI1

CLK_PCIE_MINI1#

MINI2CLK_REQ#

MINI1CLK_REQ#

MCH_DREFCLK

MCH_DREFCLK#

CPU_MCH_BSEL1CPU_MCH_BSEL2

CLK_PCIE_LOM

CLK_PCIE_LOM#

CLK_MCH_3GPLL

CLK_MCH_3GPLL#

CLK_3GPLLREQ# CLK_PCI_LOM

CLK_PCI_PCCARD

CLK_PCI_DOCK

LOM_CLKREQ#

CLK_SD_48M

ICH_SMBDATA CLK_SDATA

CPU_MCH_BSEL0

CLK_ENABLE#

DREF_SSCLK

DREF_SSCLK#

ICH_SMBCLK CLK_SCLK

Title


Date: Sheet o fLA-3741P 0.1Clock Generator



Place crystal within500 mils of CK410

31

G S

2N7002

2

D

1

*

CLKSEL2 CLKSEL0CLKSEL1FSC FSB FSA CPU

MHzSRCMHz

PCIMHz

266133200166333100400

100100100100100100100

33.333.333.333.333.333.333.3

0 0 000

00

0

000

0

111 1

1111 1

11

CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB)

133

166

0

0

0

1

Place near each pinW>40 milPlace near CK410+



Reserve

FCTSEL1 PIN43 PIN44 PIN47 PIN48

0

1

DOT96T DOT96C 96/100M_T 96/100M_C

27M_out 27M SSout SRCT0 SRCC0

60ohm,500mA,0.1ohm

60ohm,500mA,0.1ohm

R30 0_0402_5%~D

1 2

R13 49.9_0402_1%~D 1 2

R605 39_0402_5%~D

12

R28 33_0402_5%~D

1 2

X114.31818MHz_20P_1BX14318CC1A~D

1

2

R20 49.9_0402_1%~D

1 2

C20.1U_0402_16V4Z~D

1

2

R29 33_0402_5%~D

1 2

C40.1U_0402_16V4Z~D

1

2

R27 2.2_0603_5%~D

1 2

R22 49.9_0402_1%~D 1 2

R62 33_0402_5%~D

1 2

R50 33_0402_5%~D

1 2

R70 33_0402_5%~D 1 2

R51 475_0402_1%~D

1 2

C110U_0805_10V4Z~D

1

2

C80.1U_0402_16V4Z~D

1

2

R

4

2

.

2

K

_

0

4

0

2

_

5

%

~

D

1

2

R1 49.9_0402_1%~D

12

R43 33_0402_5%~D

1 2

R39 56_0402_5%~D

1 2

R41 15_0402_5%~D

1 2

R56 8.2K_0402_5%~D

12

C6430.1U_0402_16V4Z~D

1

2

R23 49.9_0402_1%~D 1 2

R48 56_0402_5%~D

1 2

R44 33_0402_5%~D

1 2

U1

SLG84450VTR_QFN72~D

VDDSRC1VDDSRC49

VDDSRC65

VDDPCI30VDDPCI36

VDD4840

VDDCPU12

VDDREF18

USB_48MHz/FSLA41

FSLB/TEST_MODE45

X219

X120

GNDPCI31

PCICLK232

REF0/FSLC/TEST_SEL23

SMBDAT17

SMBCLK16

ITP_EN/PCICLK_F037

IREF9

CPU_STOP# 24

CPUT1 11

CPUC1 10

CPUT_ITP/SRCT10 6

PCICLK333

PCICLK4/FCTSEL134

CPUC0 13

CPUT0 14

PCI_SRC_STOP# 25

GNDA 8

VDDA 7

GNDPCI35

CPUC_ITP/SRCC10 5

GNDREF21

GNDCPU15

GNDSRC4

GND4842

GNDSRC68

DOTT_96MHz/27MHz43

DOTC_96MHz/27MHz(SS)44

Vtt_PwrGd#/PD39

REF122SRCT7 66

SRCC7 67

SRCT8 70

SRCC8 69

SRCT9 3

SRCC9 2

SRCC1 51

LCD100/96/SRC0_T 47

SRCT2 52

SRCT4 58

SRCT1 50

CLKREQ4# 57

SRCC2 53

SRCC5 61

SRCC4 59

SRCT5 60

LCD100/96/SRC0_C 48

SRCC3 56

SRCT3 55

SRCT6 63

SRCC6 64

CLKREQ6# 62

CLKREQ8# 71

CLKREQ9# 72

CLKREQ1# 46

CLKREQ5# 29

CLKREQ3# 28

CLKREQ2# 26

CLKREQ7# 38

VDDSRC54

PCICLK127

THRM_PAD73

THRM_PAD76

THRM_PAD74THRM_PAD75

R53 33_0402_5%~D

1 2

R66 10K_0402_5%~D

1 2

R49 33_0402_5%~D

1 2

C50.1U_0402_16V4Z~D

1

2

R6710K_0402_5%~D@

1

2

R33 33_0402_5%~D

1 2

R16 49.9_0402_1%~D

1 2

R68 33_0402_5%~D 1 2

R37 56_0402_5%~D

1 2

R38 56_0402_5%~D

1 2

C90.1U_0402_16V4Z~D

1

2

R15 2.2_0603_5%~D

1 2

R32 39_0402_5%~D

12

G

D S

Q22N7002W-7-F_SOT323~D

2

1 3

R8 49.9_0402_1%~D

12

R31 33_0402_5%~D

1 2

R21 49.9_0402_1%~D

1 2

R46 10K_0402_5%~D

1 2

R561 8.2K_0402_5%~D@12

C1627P_0402_50V8J~D

12

R35 39_0402_5%~D

12

R52.2K_0402_5%~D

1

2

R54 33_0402_5%~D

1 2

L1BLM18PG600SN1_0603~D

1 2R2 49.9_0402_1%~D

12

C

1

0

4

.

7

U

_

0

6

0

3

_

6

.

3

V

6

M

~

D

1

2

R34 39_0402_5%~D

1 2

C1527P_0402_50V8J~D

12

R12 49.9_0402_1%~D

1 2

C

1

2

4

.

7

U

_

0

6

0

3

_

6

.

3

V

6

M

~

D

1

2

R9 49.9_0402_1%~D

1 2

G

D S

Q12N7002W-7-F_SOT323~D

2

1 3

R52 10K_0402_5%~D

1 2

C

1

1

0

.

0

4

7

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2R17 49.9_0402_1%~D

1 2

L2BLM18PG600SN1_0603~D

1 2

R3 49.9_0402_1%~D

12

C

1

4

0

.

0

4

7

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2

R65 33_0402_5%~D

1 2

R55 10K_0402_5%~D

1 2

R11 49.9_0402_1%~D

1 2

R6 49.9_0402_1%~D

12

R40 15_0402_5%~D

1 2

R7210K_0402_5%~D@

1

2

R6910K_0402_5%~D

1

2

R47 10K_0402_5%~D

1 2

R7110K_0402_5%~D

1

2

C

1

3

0

.

0

4

7

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2

R42 33_0402_5%~D

1 2

R19 49.9_0402_1%~D

1 2

R26 33_0402_5%~D

1 2

R64 33_0402_5%~D

1 2

R18 49.9_0402_1%~D

1 2

R61 33_0402_5%~D

1 2

C6

0.1U_0402_16V4Z~D

1

2

R36 39_0402_5%~D

12

R25 1_0603_5%~D

1 2 R24 33_0402_5%~D

1 2

R45 33_0402_5%~D

1 2

C30.1U_0402_16V4Z~D

1

2

R14 49.9_0402_1%~D 1 2

C710U_0805_10V4Z~D

1

2

R63 10K_0402_5%~D

1 2

R7 49.9_0402_1%~D

12

R10 49.9_0402_1%~D

1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_FERR#

H_ADSTB#0

H_D#52

H_D#20

H_REQ#2

H_D#10

H_D#5

H_D#49

H_D#3

H_REQ#0

H_D#39

H_D#57

H_D#29

H_IGNNE#

H_D#34

H_D#14

H_BNR#

H_DSTBP#0

H_D#51

H_D#22

H_DEFER#

H_INIT#

H_REQ#1

H_D#50

H_D#48

H_D#0

H_RS#0

H_DSTBN#1

H_D#58

H_D#28

ITP_BPM#2

H_BPRI#

H_ADS#

ITP_BPM#3

H_RS#1

H_DSTBP#1

H_D#46

H_D#41

H_D#12

H_IERR#H_HITM#

H_DSTBN#0

H_D#47

H_D#37

H_INTR

H_DSTBN#2

H_D#9

H_D#7

H_REQ#4

H_D#31

H_D#13

ITP_DBRESET#

H_DRDY#

H_A20M#

H_D#27

H_D#25

H_D#4

H_DSTBP#2

H_D#56

H_D#35

H_D#59

H_D#63

H_D#45

H_D#24

H_D#30

H_D#55

H_D#40

H_D#19

H_D#62

H_D#44

H_D#23

H_D#2

H_D#8

H_D#6

H_D#54

H_D#33

H_D#18

H_D#16

H_D#61

H_D#43

H_D#1

H_D#26

H_DSTBN#3

H_D#53

H_D#32

H_D#11

H_DSTBP#3

H_D#38

H_D#36

H_D#17

H_D#15

H_NMI

H_D#60

H_D#42

H_D#21

H_BR0#

H_LOCK#

H_DPSLP#

H_HIT#

H_ADSTB#1

H_THERMTRIP#

H_DBSY#

H_RS#2

H_RESET#

ITP_BPM#1

H_REQ#3

H_SMI#H_STPCLK#

ITP_TCK

ITP_TRST#

TEST1TEST2ITP_TMS

H_CPUSLP#

ITP_TDOITP_TDI

ITP_BPM#5

H_DPWR#ITP_BPM#4

CPU_PROCHOT#

H_THERMTRIP#

H_TRDY#

CLK_CPU_BCLKCLK_CPU_BCLK#

ITP_BPM#0

ITP_TDO

ITP_TDO

ITP_TDI

ITP_TRST#

ITP_TCK

ITP_DBRESET#

H_RESET#

H_RESET#

H_THERMDAH_THERMDC

TEST2

H_DPRSTP#

ITP_BPM#5

ITP_TMS

ITP_TCK

ITP_TCK

ITP_DBRESET#

ITP_BPM#0

CLK_CPU_ITP#CLK_CPU_ITP

ITP_TRST#ITP_TMSITP_TDI

ITP_BPM#5

ITP_BPM#4

ITP_BPM#2

ITP_BPM#3

ITP_BPM#1

CPU_PROCHOT#TEST1

H_A#26

H_A#14

H_A#24

H_A#16

H_A#11

H_A#18

H_A#3

H_A#8

H_A#27

H_A#30

H_A#20

H_A#12

H_A#28

H_A#22

H_A#7

H_A#13

H_A#17

H_A#6H_A#5

H_A#10

H_A#15

H_A#31

H_A#9

H_A#19

H_A#25

H_A#21

H_A#23

H_A#4

H_A#29

+1.05V_VCCP

+3.3V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_THERMTRIP#

H_THERMDA

H_THERMDC

H_ADS#

H_REQ#[0..4]

H_BPRI#H_BNR#

H_HITM#

H_BR0#

H_HIT#

H_D#[0..63]

H_DPSLP#

H_RESET#

H_DRDY#

H_ADSTB#0

H_DSTBP#[0..3]

H_ADSTB#1

H_DSTBN#[0..3]

H_DINV#0

H_DINV#2

H_DBSY#

H_DINV#1

H_IGNNE#

H_INTR H_NMI

H_DINV#3

H_INIT#

ITP_DBRESET#

H_A20M#

H_STPCLK# H_SMI#

H_CPUSLP#

H_DPWR#H_DPRSTP#

H_TRDY#

CLK_CPU_BCLKCLK_CPU_BCLK#

CLK_CPU_ITP#CLK_CPU_ITP

H_DEFER#

H_LOCK#

H_RS#[0..2]

CPU_PROCHOT#

H_PWRGOOD

H_FERR#

H_A#[3..31]

Title


Date: Sheet o fLA-3741P 0.1

Yonah-ULV in mFCPGA479



H_THERMDA, H_THERMDC routing together.Trace width / Spacing = 10 / 10 mil



This shall place near CPU

For Yonah B0

Link CIS

R74 51_0402_5%~D

1 2

R75 54.9_0402_1%~D 1 2

C182200P_0402_50V7K~D

@

1

2

R579 1K_0402_5%~D@1 2

R78 150_0402_1%~D

1 2

R73 150_0402_1%~D

1 2

R7722.6_0402_1%~D

1 2

R8256_0402_5%~D

1 2

R79 680_0402_5%~D

1 2

R76 39_0402_5%~D

1 2

ADDR GROUP

CONTROL

HOST CLK

MISC

DATA GROUP

THERMALDIODE

LEGACY CPU

YONAH-ULVU2A

Yonah-ULV_1.06G SC_UFCBGA479~D

A3#J4A4#L4A5#M3A6#K5A7#M1A8#N2A9#J1A10#N3A11#P5A12#P2A13#L1A14#P4A15#P1A16#R1A17#Y2A18#U5A19#R3A20#W6A21#U4A22#Y5A23#U2A24#R4A25#T5A26#T3A27#W3A28#W5A29#Y4A30#W2A31#Y1

REQ0#K3REQ1#H2REQ2#K2REQ3#J3REQ4#L5

ADSTB0#L2ADSTB1#V4

BCLK0A22BCLK1A21

ADS#H1BNR#E2BPRI#G5BR0#F1DEFER#H5DRDY#F21HIT#G6HITM#E4IERR#D20LOCK#H4RESET#B1

RS0#F3RS1#F4RS2#G3TRDY#G2

BPM0#AD4BPM1#AD3BPM2#AD1BPM3#AC4

DBR#C20DBSY#E1DPSLP#B5

DPWR#D24PRDY#AC2PREQ#AC1PROCHOT#D21

PWRGOODD6SLP#D7TCKAC5TDIAA6TDOAB3TEST1C26TEST2D25TMSAB5TRST#AB6

THERMDAA24THERMDCA25THERMTRIP#C7

D0# E22D1# F24D2# E26D3# H22D4# F23D5# G25D6# E25D7# E23D8# K24D9# G24

D10# J24D11# J23D12# H26D13# F26D14# K22D15# H25D16# N22D17# K25D18# P26D19# R23D20# L25D21# L22D22# L23D23# M23D24# P25D25# P22D26# P23D27# T24D28# R24D29# L26D30# T25D31# N24D32# AA23D33# AB24D34# V24D35# V26D36# W25D37# U23D38# U25D39# U22D40# AB25D41# W22D42# Y23D43# AA26D44# Y26D45# Y22D46# AC26D47# AA24D48# AC22D49# AC23D50# AB22D51# AA21D52# AB21D53# AC25D54# AD20D55# AE22D56# AF23D57# AD24D58# AE21D59# AD21D60# AE25D61# AF25D62# AF22D63# AF26

DINV0# J26DINV1# M26DINV2# V23DINV3# AC20

DSTBN0# H23DSTBN1# M24DSTBN2# W24DSTBN3# AD23DSTBP0# G22DSTBP1# N25DSTBP2# Y25DSTBP3# AE24

A20M# A6FERR# A5

IGNNE# C4INIT# B3

LINT0 C6LINT1 B4

STPCLK# D5SMI# A3

DPRSTP#E5

J2

MOLEX_52435-2891_28P~D@

TDI1TMS2TRST#3NC14TCK5NC26TDO7BCLKN8BCLKP9GND010FBO11RESET#12BPM5#13

BPM4#15

BPM3#17

BPM2#19

BPM1#21

BPM0#23DBA#24DBR#25VTAP26VTT027VTT128

GND114

GND216

GND318

GND420

GND522

G

N

D

7

3

0

R80 22.6_0402_1%~D

1 2

C

1

7

0

.

1

U

_

0

4

0

2

_

1

6

V

4

Z

~

D

1

2

R81 27.4_0402_1%~D

1 2

R468 75_0402_5%~D

1 2

R575 54.9_0402_1%~D@1 2

R84 51_0402_5%~D1 2

R83 56_0402_5%~D 1 2

C

6

3

3

0

.

1

U

_

0

4

0

2

_

1

6

V

4

Z

~

D

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSSSENSE

VCCSENSE

VSSSENSE

COMP0

VID3

VID6VID5

VID2

VID4

VID1

VCCSENSE

COMP1

H_PSI#

COMP2

VID0

COMP3

+1.05V_VCCP

+VCC_CORE

+1.05V_VCCP

V_CPU_GTLREF

V_CPU_GTLREF

+1.5V_RUN

+VCC_CORE

+VCC_CORE

H_PSI#

VID0VID1VID2VID3VID4VID5VID6

VCCSENSEVSSSENSE

CPU_MCH_BSEL0CPU_MCH_BSEL1CPU_MCH_BSEL2

Title



Yonah-ULV in mFCBGA479



Resistor placed within0.5" of CPU pin.Traceshould be at least 25mils away from anyother toggling signal.

R_B

R_A

Layout close CPU PIN AD26



0.5 inch (max)

CPU_BSEL CPU_BSEL2 CPU_BSEL1

133

166

0 0

0 1

CPU_BSEL0

1

1

Length match within 25 mils

Layout close CPUVCCSENSE/VSSSENSEtrace width 18mil,space 7mil, forother signal 15mil

Close to U2.B26

Link CISLink CIS

P

O

W

E

R

,

G

R

O

U

N

G

,

R

E

S

E

R

V

E

D

S

I

G

N

A

L

S

A

N

D

N

C

YONAH-ULV

U2B


PSI#AE6

GTLREFAD26

VCCSENSEAF7

VCCAB26

VCCAB20VCCAA20VCCAF20VCCAE20VCCAB18VCCAB17VCCAA18VCCAA17VCCAD18VCCAD17VCCAC18VCCAC17VCCAF18VCCAF17

RSVDT22

RSVDV3RSVDB2RSVDC3

VSS AB26VSS AA25VSS AD25VSS AE26VSS AB23VSS AC24VSS AF24VSS AE23VSS AA22VSS AD22VSS AC21VSS AF21VSS AB19VSS AA19VSS AD19VSS AC19VSS AF19VSS AE19VSS AB16VSS AA16VSS AD16VSS AC16VSS AF16VSS AE16VSS AB13VSS AA14VSS AD13VSS AC14VSS AF13VSS AE14VSS AB11VSS AA11VSS AD11VSS AC11VSS AF11VSS AE11VSS AB8VSS AA8VSS AD8VSS AC8VSS AF8VSS AE8VSS AA5VSS AD5VSS AC6VSS AF6VSS AB4VSS AC3VSS AF3VSS AE4VSS AB1VSS AA2VSS AD2VSS AE1VSS B6VSS C5VSS F5VSS E6VSS H6VSS J5VSS M5VSS L6VSS P6VSS R5VSS V5VSS U6VSS Y6VSS A4VSS D4VSS E3VSS H3VSS G4VSS K4VSS L3VSS P3VSS N4VSS T4VSS U3VSS Y3VSS W4VSS D1VSS C2VSS F2VSS G1RSVDB25

VSSSENSEAE7

VCCPK6VCCPJ6VCCPM6VCCPN6VCCPT6VCCPR6VCCPK21VCCPJ21VCCPM21VCCPN21VCCPT21VCCPR21VCCPV21VCCPW21VCCPV6VCCPG21

VID0AD6VID1AF5VID2AE5VID3AF4VID4AE3VID5AF2VID6AE2

BSEL0B22BSEL1B23BSEL2C21

COMP0R26COMP1U26COMP2U1COMP3V1

RSVDC23RSVDC24RSVDAA1RSVDAA4RSVDAB2RSVDAA3RSVDM4RSVDN5RSVDT2

RSVDD2RSVDF6RSVDD3RSVDC1RSVDAF1RSVDD22

VCCE7

R

9

1

2

7

.

4

_

0

4

0

2

_

1

%

~

D

1

2

R

9

4

5

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

R

9

3

2

7

.

4

_

0

4

0

2

_

1

%

~

D

1

2

POWER, GROUND

YONAH-ULV

U2C


VCCAE18VCCAE17VCCAB15VCCAA15VCCAD15VCCAC15VCCAF15VCCAE15VCCAB14VCCAA13VCCAD14VCCAC13VCCAF14VCCAE13VCCAB12VCCAA12VCCAD12VCCAC12VCCAF12VCCAE12VCCAB10VCCAB9VCCAA10VCCAA9VCCAD10VCCAD9VCCAC10VCCAC9VCCAF10VCCAF9VCCAE10VCCAE9VCCAB7VCCAA7VCCAD7VCCAC7VCCB20VCCA20VCCF20VCCE20VCCB18VCCB17VCCA18VCCA17VCCD18VCCD17VCCC18VCCC17VCCF18VCCF17VCCE18VCCE17VCCB15VCCA15VCCD15VCCC15VCCF15VCCE15

VSS K1VSS J2VSS M2VSS N1VSS T1VSS R2VSS V2VSS W1VSS A26VSS D26VSS C25VSS F25VSS B24VSS A23VSS D23VSS E24VSS B21VSS C22VSS F22VSS E21VSS B19VSS A19VSS D19VSS C19VSS F19VSS E19VSS B16VSS A16VSS D16VSS C16VSS F16VSS E16VSS B13VSS A14VSS D13VSS C14VSS F13VSS E14VSS B11VSS A11VSS D11VSS C11VSS F11VSS E11VSS B8VSS A8VSS D8VSS C8VSS F8VSS E8VSS G26VSS K26VSS J25VSS M25VSS N26VSS T26VSS R25VSS V25VSS W26VSS H24VSS G23VSS K23VSS L24VSS P24VSS N23VSS T23VSS U24VSS Y24VSS W23VSS H21VSS J22VSS M22VSS L21VSS P21VSS R22VSS V22VSS U21VSS Y21

VCCB14VCCA13VCCD14VCCC13VCCF14VCCE13VCCB12VCCA12VCCD12VCCC12VCCF12VCCE12VCCB10VCCB9VCCA10VCCA9VCCD10VCCD9VCCC10VCCC9VCCF10VCCF9VCCE10VCCE9VCCB7

VCCF7VCCA7

R89 100_0402_1%~D 1 2 C

2

0

1

0

U

_

0

8

0

5

_

6

.

3

V

6

M

~

D

1

2

C

1

9

0

.

0

1

U

_

0

4

0

2

_

1

6

V

7

K

~

D

1

2

R871K_0402_1%~D

1

2

R88 100_0402_1%~D 1 2

R

9

2

5

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

R902K_0402_1%~D

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+VCC_CORE

+VCC_CORE

+VCC_CORE

+1.05V_VCCP

+VCC_CORE

+VCC_CORE

Title



CPU Bypass



High Frequence Decoupling

7mOhmPS CAP

ESR

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

H_SWNG1

H_SWNG0

H_VREF

V_DDR_MCH_REF

H_A#28

H_A#15

H_SWNG1

H_XRCOMP

H_D#16

H_D#10

H_A#16

H_D#62

H_D#60

H_D#19

H_D#7

H_D#0

H_A#20

H_A#17

H_A#13

H_SWNG0

H_D#53

H_D#39H_D#38

H_D#32

H_D#13

M_OCDOCMP0

H_A#8

H_D#59

H_D#27

H_D#20

H_A#26

H_A#19

H_D#58

H_D#48

H_D#46

H_D#40

H_D#8

H_D#44

H_D#12

H_D#3

H_D#1

H_A#7

H_YSCOMP

H_D#43

H_D#35

H_D#31

H_D#25H_D#24

H_A#22

H_D#61

H_D#56

H_D#21

H_D#11

H_D#6

H_A#27

H_A#6

H_A#3

H_D#37

H_D#33

H_D#30

H_D#63

H_D#51

H_D#9

H_D#2

SMRCOMPN

H_A#25

H_D#50

H_D#41

H_D#36

H_D#23

H_D#4

H_A#12H_A#11

H_D#54

H_D#42

M_OCDOCMP1

H_A#18

H_A#10

H_D#52

H_D#45

H_D#28

H_D#22

H_A#14

H_XSCOMP

H_D#29

H_A#21

H_D#47

H_D#34

H_D#18

H_A#31H_A#30H_A#29

H_A#24H_A#23

H_D#55

H_D#49

H_D#17

H_D#15

M_ODT0

H_A#9

H_A#5H_A#4

H_D#57

H_D#26

H_D#14

H_D#5

H_YRCOMP

M_CLK_DDR1M_CLK_DDR0

M_CLK_DDR#0M_CLK_DDR#1

PM_EXTTS#0

ICH_PWRGD



M_ODT3M_ODT2

PM_EXTTS#1

PM_EXTTS#0

H_DSTBP#0

H_DSTBP#2H_DSTBP#3

H_DSTBN#3

H_DSTBP#1

H_DSTBN#1H_DSTBN#0

H_DSTBN#2

H_DBSY#H_DEFER#

H_DPWR#H_DRDY#

H_HIT#H_HITM#H_LOCK#

H_RS#0

H_RS#2H_RS#1

H_REQ#0

H_REQ#4

H_REQ#2H_REQ#3

H_REQ#1

H_CPUSLP#H_TRDY#

H_RESET#H_VREF

H_BNR#H_BPRI#H_BR0#

H_VREFH_ADSTB#1H_ADSTB#0H_ADS#

V_DDR_MCH_REF

SMRCOMPP

CPU_MCH_BSEL0CPU_MCH_BSEL1CPU_MCH_BSEL2CFG3CFG5

CFG5

CPU_MCH_BSEL0

THERMTRIP_MCH#

DMI_MTX_IRX_N0DMI_MTX_IRX_N1

DMI_MRX_ITX_N0DMI_MRX_ITX_N1

DMI_MTX_IRX_P0DMI_MTX_IRX_P1

DMI_MRX_ITX_P0DMI_MRX_ITX_P1

PLTRST_R#

DDR_CKE0DDR_CKE1DDR_CKE2_DIMMADDR_CKE3_DIMMA

DDR_CS3_DIMMA#DDR_CS2_DIMMA#DDR_CS1#

M_OCDOCMP1M_OCDOCMP0

CFG6

PM_EXTTS#1

M_ODT1

DDR_CS0#

+1.8V_SUS

+3.3V_RUN

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

H_D#[0..63]

CLK_MCH_BCLK# CLK_MCH_BCLK

H_CPUSLP#

V_DDR_MCH_REF

MCH_DREFCLK MCH_DREFCLK#

ICH_PWRGD

MCH_ICH_SYNC#

CLK_3GPLLREQ#

PM_BMBUSY#

THERMTRIP_MCH#

PLTRST#

H_REQ#[0..4]

H_DPWR# H_DRDY#

H_DSTBP#[0..3]

H_DSTBN#[0..3]

H_HIT# H_HITM# H_LOCK#

H_RS#[0..2]

H_BPRI#

CFG19

CPU_MCH_BSEL0 DMI_MRX_ITX_N0DMI_MRX_ITX_N1DMI_MRX_ITX_P0DMI_MRX_ITX_P1

CPU_MCH_BSEL1 CPU_MCH_BSEL2

DDR_CKE0

DDR_CKE3_DIMMADDR_CKE2_DIMMA

DDR_CS3_DIMMA#DDR_CS2_DIMMA#

DDR_CS0#

H_A#[3..31]

H_ADS# H_ADSTB#0 H_ADSTB#1

H_BNR#

H_BR0# H_RESET#

H_DBSY# H_DEFER# H_DINV#0

H_DINV#2 H_DINV#1

H_DINV#3

H_TRDY#

DMI_MTX_IRX_N0DMI_MTX_IRX_N1DMI_MTX_IRX_P0DMI_MTX_IRX_P1





M_ODT0

M_ODT2M_ODT3

DREF_SSCLK# DREF_SSCLK

PM_EXTTS#0 PM_EXTTS#1

Title



Calistoga(1 of 5)



Layout Note:H_XRCOMP & H_YRCOMP trace widthand spacing is 10/20

Layout Note:Route as shortas possible



Stuff R111 & R112 for A1 Calistoga

(DMI Lane Reversal)CFG19

Calistoga-GMS not have CFG4,CFG[7..18],CFG[20]Need to double check

*Low = DMI x 2High = DMI x 4CFG5

Strap Pin Table

Low = NormalOperation (Default):Lane number in OrderHigh = Reverse Lane

H

O

S

T

Calistoga-GMS_FCBGA998~D

U3A

H_XRCOMPA10H_XSCOMPA6H_XSWINGC15H_YRCOMPJ1H_YSCOMPK1H_YSWINGH1

H_D#_0C4H_D#_1F6H_D#_2H9H_D#_3H6H_D#_4F7H_D#_5E3H_D#_6C2H_D#_7C3H_D#_8K9H_D#_9F5H_D#_10J7H_D#_11K7H_D#_12H8H_D#_13E5H_D#_14K8H_D#_15J8H_D#_16J2H_D#_17J3H_D#_18N1H_D#_19M5H_D#_20K5H_D#_21J5H_D#_22H3H_D#_23J4H_D#_24N3H_D#_25M4H_D#_26M3H_D#_27N8H_D#_28N6H_D#_29K3H_D#_30N9H_D#_31M1H_D#_32V8H_D#_33V9H_D#_34R6H_D#_35T8H_D#_36R2H_D#_37N5H_D#_38N2H_D#_39R5H_D#_40U7H_D#_41R8H_D#_42T4H_D#_43T7H_D#_44R3H_D#_45T5H_D#_46V6H_D#_47V3H_D#_48W2H_D#_49W1H_D#_50V2H_D#_51W4H_D#_52W7H_D#_53W5H_D#_54V5H_D#_55AB4H_D#_56AB8H_D#_57W8H_D#_58AA9H_D#_59AA8H_D#_60AB1H_D#_61AB7H_D#_62AA2H_D#_63AB5

H_A#_3 F8H_A#_4 D12H_A#_5 C13H_A#_6 A8H_A#_7 E13H_A#_8 E12H_A#_9 J12

H_A#_10 B13H_A#_11 A13H_A#_12 G13H_A#_13 A12H_A#_14 D14H_A#_15 F14H_A#_16 J13H_A#_17 E17H_A#_18 H15H_A#_19 G15H_A#_20 G14H_A#_21 A15H_A#_22 B18H_A#_23 B15H_A#_24 E14H_A#_25 H13H_A#_26 C14H_A#_27 A17H_A#_28 E15H_A#_29 H17H_A#_30 D17H_A#_31 G17

H_ADS# F10H_ADSTB#_0 C12H_ADSTB#_1 H16

H_VREF0 E2H_BNR# B9H_BPRI# C7

H_BREQ0# G8H_CPURST# B10

HCLKN AA6HCLKP AA5

H_DBSY# C10H_DEFER# C6H_DINV#_0 H5H_DINV#_1 J6H_DINV#_2 T9H_DINV#_3 U6H_DPWR# G7H_DRDY# E6

H_DSTBN#_0 F3H_DSTBN#_1 M8H_DSTBN#_2 T1H_DSTBN#_3 AA3H_DSTBP#_0 F4H_DSTBP#_1 M7H_DSTBP#_2 T2H_DSTBP#_3 AB3

H_HIT# C8H_HITM# B4H_LOCK# C5

H_REQ#_0 G9H_REQ#_1 E9H_REQ#_2 G12H_REQ#_3 B8H_REQ#_4 F12

H_RS#_0 A5H_RS#_1 B6H_RS#_2 G10

H_SLPCPU# E8H_TRDY# E10

H_VREF1 E1

C

F

G

/

R

S

V

D

D

M

I

P

M

D

D

R

2

M

U

X

I

N

G

C

L

K


U3B

DMI_RXN_0Y29DMI_RXN_1Y32DMI_RXP_0Y28DMI_RXP_1Y31

DMI_TXN_0V28DMI_TXN_1V31DMI_TXP_0V29DMI_TXP_1V32

SM_CK_0AF33SM_CK_1AG1

SM_CK_2AJ1SM_CK_3AM30

SM_CK#_0AG33SM_CK#_1AF1

SM_CK#_2AK1SM_CK#_3AN30

SM_CKE_0AN21SM_CKE_1AN22SM_CKE_2AF26SM_CKE_3AF25

SM_CS#_0AG14SM_CS#_1AF12SM_CS#_2AK14SM_CS#_3AH12

SM_OCDCOMP_0AJ21SM_OCDCOMP_1AF11

SM_ODT_0AE12SM_ODT_1AF14SM_ODT_2AJ14SM_ODT_3AJ12

SM_RCOMPNAN12SM_RCOMPPAN14SM_VREF_0AA33SM_VREF_1AE1 D_REFCLKN A27

D_REFCLKP A26D_REFSSCLKN J33D_REFSSCLKP H33

THRMTRIP# J15PWROK AB29RSTIN# W27

PM_BMBUSY# G21PM_EXTTS#_0 F26

CFG_0 C18CFG_1 E18CFG_2 G20

CFG_5 J20CFG_6 J18

PM_EXTTS#_1 H26

RESERVED8 F18

CLKREQ# J22

CFG_3 G18

PM_ICHSYNC# E31

RESERVED9 A3

RESERVED7 C17

RESERVED1 K32RESERVED2 K31

T14 PAD~D

R109 10K_0402_5%~D@12

R

9

6

1

0

0

_

0

4

0

2

_

1

%

~

D

1

2

R

1

0

2

1

0

0

_

0

4

0

2

_

1

%

~

D

1

2

R108 10K_0402_5%~D

12

R

1

0

3

5

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

T2PAD~D

R110 1K_0402_5%~D @1 2

R

9

5

2

2

1

_

0

4

0

2

_

1

%

~

D

1

2

R100100_0402_1%~D

1 2R99 80.6_0402_1%~D

1 2

R

1

0

6

2

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

C

5

4

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

R101 80.6_0402_1%~D

1 2

R

1

0

4

5

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

R113 1K_0402_5%~D @1 2

C

5

2

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

R

1

0

7

2

4

.

9

_

0

4

0

2

_

1

%

~

D

1

2

R

1

1

1

4

0

.

2

_

0

4

0

2

_

1

%

~

D

@

1

2

R

1

0

5

2

0

0

_

0

4

0

2

_

1

%

~

D

1

2

R

9

8

1

0

0

_

0

4

0

2

_

1

%

~

D

1

2

T3PAD~D

R114 75_0402_5%~D

1 2

C

5

5

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

@

1

2

T15 PAD~D

R115 2.2K_0402_5%~D1 2

R

1

1

2

4

0

.

2

_

0

4

0

2

_

1

%

~

D

@

1

2

C

5

3

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

T13 PAD~D

R

9

7

2

2

1

_

0

4

0

2

_

1

%

~

D

1

2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A_D58

DDR_A_D43

DDR_A_D39

DDR_B_MA9DDR_B_MA8

DDR_A_D61

DDR_A_D52

DDR_A_D27

DDR_A_D13

DDR_A_D3

DDR_B_MA2

DDR_A_D56

DDR_A_D45

DDR_A_D42

DDR_A_D37

DDR_A_D31

DDR_A_D26

DDR_A_D49

DDR_A_D38

DDR_A_D15

DDR_A_D11

DDR_A_D8

DDR_B_MA6DDR_B_MA5DDR_B_MA4

DDR_B_RAS#

DDR_A_D47

DDR_A_D23

DDR_A_D20

DDR_B_MA12

DDR_A_BS0

DDR_A_D62

DDR_A_D54

DDR_A_D50

DDR_A_D18

DDR_A_D9

DDR_A_D5

DDR_A_D48

DDR_A_D4

DDR_A_D17

DDR_A_D14

DDR_A_D10

DDR_B_MA1

DDR_A_D46

DDR_A_D41

DDR_B_MA11DDR_B_CAS#

DDR_A_D36

DDR_A_D25

DDR_B_MA0DDR_A_D55

DDR_A_D32

DDR_A_D30

DDR_B_WE#

DDR_A_D59

DDR_A_D51

DDR_A_D34

DDR_A_D12

DDR_A_D6

DDR_A_BS1

DDR_A_D44

DDR_A_D35

DDR_A_D21

DDR_A_D19

DDR_A_D40

DDR_A_D28

DDR_A_D24

DDR_B_MA10

DDR_A_D60

DDR_A_D33

DDR_A_D2DDR_A_D1DDR_A_D0

DDR_B_MA7 DDR_A_D63

DDR_A_D53

DDR_A_D16

DDR_B_MA3

DDR_A_D57

DDR_A_D29

DDR_A_D22

DDR_A_D7

DDR_A_DM0

DDR_A_DM3

DDR_A_DM1

DDR_A_DM4

DDR_A_DM6

DDR_A_DM2

DDR_A_DM5

DDR_A_DM7

DDR_A_DQS0

DDR_A_DQS2DDR_A_DQS1

DDR_A_DQS6

DDR_A_DQS3

DDR_A_DQS7

DDR_A_DQS4DDR_A_DQS5

DDR_A_DQS#1

DDR_A_DQS#4DDR_A_DQS#3

DDR_A_DQS#6

DDR_A_DQS#2

DDR_A_DQS#5

DDR_A_DQS#7

DDR_A_DQS#0

DDR_A_MA0DDR_A_MA1DDR_A_MA2DDR_A_MA3

DDR_A_MA7DDR_A_MA6

DDR_A_MA4DDR_A_MA5

DDR_A_MA9DDR_A_MA8

DDR_A_MA11DDR_A_MA10

DDR_A_MA12

DDR_A_CAS#DDR_A_RAS#

SA_RCVENIN#SA_RCVENOUT#

DDR_A_WE#

DDR_B_BS0DDR_B_BS1

DDR_B_MA13

DDR_B_BS2

DDR_A_MA13

DDR_A_BS2

DDR_A_D[0..63]

DDR_A_BS1DDR_A_BS0

DDR_B_MA[0..13]

DDR_B_WE#

DDR_B_CAS# DDR_B_RAS#

DDR_A_DM[0..7]

DDR_A_MA[0..13]

DDR_A_CAS#DDR_A_RAS#

DDR_A_WE#

DDR_B_BS1DDR_B_BS0

DDR_B_BS2

DDR_A_DQS#[0..7]

DDR_A_DQS[0..7]

DDR_A_BS2

Title



Calistogo(2 of 5)


Compal Electronics, Inc.DELL CONFIDENTIAL/PROPRIETARY


D

D

R

2

S

Y

S

T

E

M

M

E

M

O

R

Y


U3C

SA_DQ_0 AC31SA_DQ_1 AB28SA_DQ_2 AE33SA_DQ_3 AF32SA_DQ_4 AC33SA_DQ_5 AB32SA_DQ_6 AB31SA_DQ_7 AE31SA_DQ_8 AH31SA_DQ_9 AK31

SA_DQ_10 AL28SA_DQ_11 AK27SA_DQ_12 AH30SA_DQ_13 AL32SA_DQ_14 AJ28SA_DQ_15 AJ27SA_DQ_16 AH32SA_DQ_17 AF31SA_DQ_18 AH27SA_DQ_19 AF28SA_DQ_20 AJ32SA_DQ_21 AG31SA_DQ_22 AG28SA_DQ_23 AG27SA_DQ_24 AN27SA_DQ_25 AM26SA_DQ_26 AJ26SA_DQ_27 AJ25SA_DQ_28 AL27SA_DQ_29 AN26SA_DQ_30 AH25SA_DQ_31 AG26SA_DQ_32 AM12SA_DQ_33 AL11SA_DQ_34 AH9SA_DQ_35 AK9SA_DQ_36 AM11SA_DQ_37 AK11SA_DQ_38 AM8SA_DQ_39 AK8SA_DQ_40 AG9SA_DQ_41 AF9SA_DQ_42 AF8SA_DQ_43 AK6SA_DQ_44 AF7SA_DQ_45 AG11SA_DQ_46 AJ6SA_DQ_47 AH6SA_DQ_48 AN6SA_DQ_49 AM6SA_DQ_50 AK3SA_DQ_51 AL2SA_DQ_52 AM5SA_DQ_53 AL5SA_DQ_54 AJ3SA_DQ_55 AJ2SA_DQ_56 AG2SA_DQ_57 AF3SA_DQ_58 AE7SA_DQ_59 AF6SA_DQ_60 AH5SA_DQ_61 AG3SA_DQ_62 AG5SA_DQ_63 AF5

SB_CAS# AG19SB_RAS# AG21SB_WE# AG20

SB_MA_0AN20SB_MA_1AL21SB_MA_2AK21SB_MA_3AK22SB_MA_4AL22SB_MA_5AH22SB_MA_6AG22SB_MA_7AF21SB_MA_8AM21SB_MA_9AE21SB_MA_10AL20SB_MA_11AE22SB_MA_12AE26SB_MA_13AE20

SA_CAS#AJ17SA_RAS#AK18SA_RCVENIN#AN28SA_RCVENOUT#AM28SA_WE#AH17

SA_MA_0AJ15SA_MA_1AM17SA_MA_2AM15SA_MA_3AH15SA_MA_4AK15SA_MA_5AN15SA_MA_6AJ18SA_MA_7AF19SA_MA_8AN17SA_MA_9AL17SA_MA_10AG16SA_MA_11AL18SA_MA_12AG18SA_MA_13AL14

SA_DQS#_0AC29SA_DQS#_1AK30SA_DQS#_2AJ33SA_DQS#_3AM25SA_DQS#_4AN8SA_DQS#_5AJ8SA_DQS#_6AM3SA_DQS#_7AE2

SA_DQS_0AC28SA_DQS_1AJ30SA_DQS_2AK33SA_DQS_3AL25SA_DQS_4AN9SA_DQS_5AH8SA_DQS_6AM2SA_DQS_7AE3

SA_DM_0AB30SA_DM_1AL31SA_DM_2AF30SA_DM_3AK26SA_DM_4AL9SA_DM_5AG7SA_DM_6AK5SA_DM_7AH3

SA_BS_0AK12SA_BS_1AH11SA_BS_2AG17

SB_BS_0AH21SB_BS_1AJ20SB_BS_2AE27

T4 PAD~DT5 PAD~D

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DAT_DDC2

CLK_DDC2

LCTLA_CLK

LCTLB_DATA

G_DAT_DDC2

VGA_RED

VGA_GRN

VGA_BLU

LCD_A2+

LCD_A2-

SDVO_CTRLDATA

L_IBG

LCD_A1-LCD_A0-

LCD_A0+LCD_A1+

G_CLK_DDC2

DVO_BLUE_C

SDVO_CTRLCLK+PEGCOMP

TVIREF

G_CLK_DDC2G_DAT_DDC2

CRT_IREF

BIA_PWMPANEL_BKEN

LCTLB_DATALCTLA_CLK

LCD_DDCDATALCD_DDCCLK

DVO_RED#_C

DVO_RED_C

DVO_GREEN#_C

DVO_GREEN_C

DVO_BLUE#_CDVO_CLK#_C

DVO_CLK_C

LCD_DDCDATA

LCD_DDCCLK

LCD_ACLK-LCD_ACLK+

LCD_ACLK-

LCD_A1-

LCD_A2+

LCD_ACLK+

LCD_A0+

LCD_A1+

LCD_A2-

LCD_A0-

+1.5VRUN_PCIE

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

DAT_DDC2

SDVOB_BLUE+

LCD_A0+LCD_A1+LCD_A2+

LCD_A0-LCD_A1-LCD_A2-

CLK_MCH_3GPLL#CLK_MCH_3GPLL

BIA_PWM

LCD_DDCDATA

LCD_ACLK-

SDVOB_RED-

SDVOB_RED+

SDVOB_GREEN-

SDVOB_GREEN+

SDVOB_BLUE- SDVOB_CLK-

SDVOB_CLK+

LCD_ACLK+

SDVOB_INT-

SDVOB_INT+

TV_CVBS TV_Y TV_C

SDVO_CTRLDATA

VGA_BLU

VGA_GRN

VGA_RED

VGA_VSYNCVGA_HSYNC

PANEL_BKEN

ENVDD

SDVO_CTRLCLK

LCD_DDCCLK

CLK_DDC2

Title



Calistoga(3 of 5)




Close to U3.H25

Close to U3.G23

R123 10K_0402_5%~D

1 2

R127 150_0402_1%~D

12

R124 10K_0402_5%~D

1 2

R11624.9_0402_1%~D 1 2

C57 0.1U_0402_10V6K~D

1 2

R581 2.2K_0402_5%~D

1 2

R580 2.2K_0402_5%~D

1 2

R126 150_0402_1%~D

12

G

DS

Q32N7002W-7-F_SOT323~D

2

13

R117 255_0402_1%~D

12

C59 0.1U_0402_10V6K~D

1 2

C7123.3P_0402_50VJ~D

1

2

C58 0.1U_0402_10V6K~D

1 2

R

1

2

1

1

5

0

_

0

4

0

2

_

1

%

~

D

1

2

S

D

V

O

L

V

D

S

V

G

A

T

V

M

I

S

C


U3F

SDVO_CTRLCLKJ27G_CLKNY26G_CLKPAA26

SDVO_CTRLDATAH27

TV_DACA A21TV_DACB C20TV_DACC E20TV_IREF G23

TV_IRTNA B21TV_IRTNB C21TV_IRTNC D21

CRT_DDC_CLKH20CRT_DDC_DATAH22CRT_BLUEA24CRT_BLUE#A23CRT_GREENE25CRT_GREEN#F25CRT_REDC25CRT_RED#D25CRT_VSYNCF27CRT_HSYNCD27CRT_IREFH25

L_BKLTCTLH30L_BKLTENG29L_CLKCTLAF28L_CTLBDATAE28L_DDC_CLKG28L_DDC_DATAH28L_VDDENK30L_IBGK27L_VBGJ29L_VREFHJ30L_VREFLK29

LA_CLKND30LA_CLKPC30

LA_DATAN_0G31LA_DATAN_1F32LA_DATAN_2D31

LA_DATAP_0H31LA_DATAP_1G32LA_DATAP_2C31

SDVO_RED N28SDVO_GREEN M32

SDVO_BLUE P33SDVO_CLKP R32

SDVO_RED# P28SDVO_GREEN# N32

SDVO_BLUE# P32SDVO_CLKN T32

SDVO_TVCLKIN M30SDVO_INT P30

SDVO_FLDSTALL T30

SDVO_TVCLKIN# N30SDVO_INT# R30

SDVO_FLDSTALL# T29

EXP_A_COMPI R28EXP_A_ICOMPO M28

LB_DATAN_0F33LB_DATAN_1D33LB_DATAN_2F30

LB_DATAP_0E33LB_DATAP_1D32LB_DATAP_2F29

LB_CLKNA30LB_CLKPA29

TV_DCONSEL0 G26TV_DCONSEL1 J26

R118 1.5K_0402_1%~D

12

C56 0.1U_0402_10V6K~D

1 2

R

1

2

9

2

.

2

K

_

0

4

0

2

_

5

%

~

D

1

2

C61 0.1U_0402_10V6K~D

1 2C62 0.1U_0402_10V6K~D

1 2

R128 150_0402_1%~D

12

R

1

2

0

1

5

0

_

0

4

0

2

_

1

%

~

D

1

2

R

1

1

9

1

5

0

_

0

4

0

2

_

1

%

~

D

1

2

G

DS

Q42N7002W-7-F_SOT323~D

2

13

R

1

3

0

2

.

2

K

_

0

4

0

2

_

5

%

~

D

1

2

R

1

2

2

4

.

9

9

K

_

0

4

0

2

_

1

%

~

D

1

2

C7118.2P_0402_50V8J~D

1

2

C7133.3P_0402_50VJ~D

1

2

C60 0.1U_0402_10V6K~D

1 2

C7143.3P_0402_50VJ~D

1

2

C63 0.1U_0402_10V6K~D

1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CFG19

+1.5V_RUN+1.05V_VCCP

+1.05V_VCCP

CFG19

Title



Calistoga(4 of 5)




CRB 270uF

C

6

5

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

+

C

7

0

2

2

0

U

_

D

2

_

4

M

_

R

4

5

~

D

1

2

C

6

7

1

0

U

_

0

8

0

5

_

6

.

3

V

6

M

~

D

1

2

+

C

7

1

2

2

0

U

_

D

2

_

4

M

_

R

4

5

~

D

1

2

V

S

S


U3E

VSS_1AH33VSS_2Y33VSS_3V33VSS_4R33

VSS_6AK32VSS_7AG32VSS_8AE32VSS_9AC32VSS_10AA32VSS_11U32VSS_12H32VSS_13E32VSS_14C32VSS_15AM31VSS_16AJ31VSS_17AA31VSS_18U31VSS_19T31VSS_20R31VSS_21P31VSS_22N31VSS_23M31VSS_24J31VSS_25F31VSS_26AL30VSS_27AG30VSS_28AE30VSS_29AC30VSS_30AA30VSS_31Y30VSS_32V30VSS_33U30VSS_34G30VSS_35E30VSS_36B30VSS_37AA29VSS_38U29VSS_39R29VSS_40P29VSS_41N29VSS_42M29VSS_43H29VSS_44E29VSS_45B29VSS_46AK28VSS_47AH28VSS_48AE28VSS_49AA28VSS_50U28VSS_51T28VSS_52J28VSS_53D28VSS_54AM27VSS_55AF27VSS_56AB27VSS_57AA27VSS_58Y27VSS_59U27VSS_60T27VSS_61R27VSS_62P27VSS_63N27VSS_64M27VSS_65G27

VSS_67C27VSS_68B27VSS_69AL26

VSS_71W26VSS_72U26VSS_73AN25VSS_74AK25

VSS_77J25VSS_78G25VSS_79A25VSS_80H23VSS_81F23

VSS_111 J16VSS_112 AL15VSS_113 AG15VSS_114 W15VSS_115 R15VSS_116 F15VSS_117 D15VSS_118 AM14VSS_119 AH14VSS_120 AE14VSS_121 H14VSS_122 B14VSS_123 F13VSS_124 D13VSS_125 AL12VSS_126 AG12VSS_127 H12VSS_128 B12VSS_129 AN11VSS_130 AJ11VSS_131 AE11VSS_132 AM9

VSS_134 AB9VSS_135 W9VSS_136 R9VSS_137 M9VSS_138 J9VSS_139 F9VSS_140 C9VSS_141 A9VSS_142 AL8VSS_143 AG8VSS_144 AE8VSS_145 U8VSS_146 AA7VSS_147 V7VSS_148 R7VSS_149 N7VSS_150 H7VSS_151 E7VSS_152 B7VSS_153 AL6VSS_154 AG6VSS_155 AE6VSS_156 AB6VSS_157 W6VSS_158 T6VSS_159 M6VSS_160 K6VSS_161 AN5VSS_162 AJ5VSS_163 B5VSS_164 AA4VSS_165 V4VSS_166 R4VSS_167 N4VSS_168 K4VSS_169 H4VSS_170 E4VSS_171 AL3VSS_172 AD3VSS_173 W3VSS_174 T3

VSS_5G33

VSS_133 AJ9

VSS_175 B3VSS_176 AK2VSS_177 AH2VSS_178 AF2VSS_179 AB2VSS_180 M2VSS_181 K2VSS_182 H2VSS_183 F2VSS_184 V1VSS_185 R1

VSS_66E27

VSS_70AH26

VSS_75AG25VSS_76AE25

VSS_82B23

VSS_84AJ22VSS_85AF22VSS_86G22

VSS_83AM22

VSS_87E22VSS_88J21VSS_89H21VSS_90F21VSS_91AM20

VSS_100AF18VSS_99AH18VSS_98AM18

VSS_96W19VSS_95D20VSS_94AF20

VSS_92AK20VSS_93AH20

VSS_97R19

VSS_101U18VSS_102H18VSS_103D18VSS_104AK17VSS_105V17VSS_106T17VSS_107F17VSS_108B17VSS_109AH16VSS_110U16

NCTF


U3H

VCC_NCTF1T25VCC_NCTF2R25VCC_NCTF3P25VCC_NCTF4N25VCC_NCTF5M25VCC_NCTF6P24VCC_NCTF7N24VCC_NCTF8M24VCC_NCTF9Y22VCC_NCTF10W22VCC_NCTF11V22VCC_NCTF12U22VCC_NCTF13T22VCC_NCTF14R22VCC_NCTF15P22VCC_NCTF16N22VCC_NCTF17M22VCC_NCTF18Y21VCC_NCTF19W21VCC_NCTF20V21VCC_NCTF21U21VCC_NCTF22T21VCC_NCTF23R21VCC_NCTF24P21VCC_NCTF25N21VCC_NCTF26M21VCC_NCTF27Y20VCC_NCTF28W20VCC_NCTF29V20VCC_NCTF30U20VCC_NCTF31T20VCC_NCTF32R20VCC_NCTF33P20VCC_NCTF34N20VCC_NCTF35M20VCC_NCTF36Y19VCC_NCTF37P19VCC_NCTF38N19VCC_NCTF39M19VCC_NCTF40Y18VCC_NCTF41P18VCC_NCTF42N18VCC_NCTF43M18VCC_NCTF44Y17VCC_NCTF45P17VCC_NCTF46N17VCC_NCTF47M17VCC_NCTF48Y16VCC_NCTF49P16VCC_NCTF50N16VCC_NCTF51M16VCC_NCTF52Y15VCC_NCTF53P15VCC_NCTF54N15VCC_NCTF55M15VCC_NCTF56Y14

VCCAUX_NCTF1 AD25VCCAUX_NCTF2 AC25VCCAUX_NCTF3 AB25VCCAUX_NCTF4 AD24VCCAUX_NCTF5 AC24VCCAUX_NCTF6 AD22VCCAUX_NCTF7 AD21VCCAUX_NCTF8 AD20VCCAUX_NCTF9 AD19

VCCAUX_NCTF10 AD18VCCAUX_NCTF11 AD17VCCAUX_NCTF12 AD16VCCAUX_NCTF13 AD15VCCAUX_NCTF14 AD14VCCAUX_NCTF15 K14VCCAUX_NCTF16 AD13VCCAUX_NCTF17 Y13VCCAUX_NCTF18 W13VCCAUX_NCTF19 V13VCCAUX_NCTF20 U13VCCAUX_NCTF21 T13VCCAUX_NCTF22 R13VCCAUX_NCTF23 P13VCCAUX_NCTF24 N13VCCAUX_NCTF25 M13VCCAUX_NCTF26 AD12VCCAUX_NCTF27 Y12VCCAUX_NCTF28 W12

VSS_NCTF1 AN33VSS_NCTF2 AA25VSS_NCTF3 V25VSS_NCTF4 U25VSS_NCTF5 AA22VSS_NCTF6 AA21VSS_NCTF7 AA20VSS_NCTF8 AA19VSS_NCTF9 AA18

VSS_NCTF10 AA17VSS_NCTF11 AA16VSS_NCTF12 AA15VSS_NCTF13 AA14

VTT_NCTF1T10VTT_NCTF2R10VTT_NCTF3P10VTT_NCTF4N10VTT_NCTF5L10

VCC_NCTF57W14VCC_NCTF58V14VCC_NCTF59U14VCC_NCTF60T14VCC_NCTF61R14

VCCAUX_NCTF29 V12VCCAUX_NCTF30 U12VCCAUX_NCTF31 T12VCCAUX_NCTF32 R12VCCAUX_NCTF33 P12VCCAUX_NCTF34 N12VCCAUX_NCTF35 M12VCCAUX_NCTF36 AD11VCCAUX_NCTF37 AD10VCCAUX_NCTF38 K10

VCC_NCTF62P14VCC_NCTF63N14VCC_NCTF64M14

VTT_NCTF6D1

VSS_NCTF14 AA13VSS_NCTF15 A4VSS_NCTF16 A33VSS_NCTF17 B2VSS_NCTF18 AN1VSS_NCTF19 C1

RSVD_3M10RSVD_4A18RSVD_5AB10RSVD_6AA10

CFG_19 K28

RESERVED10 K25RESERVED11 K26RESERVED12 R24RESERVED13 T24RESERVED14 K21RESERVED15 K19RESERVED16 K20RESERVED17 K24RESERVED18 K22RESERVED19 J17RESERVED20 K23RESERVED21 K17RESERVED22 K12RESERVED23 K13RESERVED24 K16RESERVED25 K15

C

6

8

1

0

U

_

0

8

0

5

_

6

.

3

V

6

M

~

D

1

2

C

6

6

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

C

6

4

0

.

1

U

_

0

4

0

2

_

1

0

V

6

K

~

D

1

2

N

C


U3G

NC1W33NC2AM33NC3AL33NC4C33NC5B33NC6AN32NC7A32NC8AN31NC9W28NC10V27NC11W29NC12J24NC13H24NC14W32NC15G24NC16F24NC17E24NC18D24NC19K33NC20A31NC21E21NC22C23NC23AN19NC24AM19NC25AL19

NC29AN3NC30Y9NC31J19NC32H19NC33G19NC34F19NC35E19NC36D19NC37C19NC38B19

NC41G16NC42F16NC43E16NC44D16NC45C16NC46B16NC47AN2

NC49Y7NC50AM4NC51AF4NC52AD4NC53AL4NC54AK4

NC57AH4NC58AG4NC59AE4NC60AM1

NC64 Y5NC63 AL1NC62 Y6NC61 W30

RESERVED26 Y25RESERVED27 Y24RESERVED28 AB22RESERVED29 AB21RESERVED30 AB19RESERVED31 AB16RESERVED32 AB14RESERVED33 AA12RESERVED34 W24RESERVED35 AA24RESERVED36 AB24RESERVED37 AB20RESERVED38 AB18RESERVED39 AB15RESERVED40 AB13RESERVED41 AB12

NC28AH19

NC26AK19NC27AJ19

NC39A19NC40Y8

NC48A16

NC55W31NC56AJ4

RESERVED42 AB17

NC65 Y10NC66 W10NC67 W25NC68 V24NC69 U24NC70 V10NC71 U10NC72 K18

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VSSA_TVBG

U3_F1

U3_AB33

U3_AH1

VSSA_TVBG

+

3

V

R

U

N

_

A

T

V

+3.3V_TV+2.5V_CRT

+3GPLL_R

U3_AM32

U3_AN4

U3_AN18

U3_AA1

U3_A14

U3_A7

+2.5V_CRTDAC

+3GPLL_L

+VCC3G_R

+2.5V_RUN

+2.5V_RUN +1.5VRUN_PCIE

+2.5V_RUN

+1.5VRUN_QTVDAC

+2.5V_RUN

+3VRUN_ATVBG

+3VRUN_TVDACC

+3VRUN_TVDACB

+3VRUN_TVDACA

+2.5V_RUN

+1.5VRUN_MPLL+1.5VRUN_HPLL+1.5VRUN_DPLLA+1.5VRUN_DPLLB

+1.5VRUN_3GPLL+2.5V_RUN

+3VRUN_TVDACA

+3VRUN_TVDACB

+3V_TVDAC

+3VRUN_ATVBG

+3VRUN_TVDACC

+1.5VRUN_3GPLL

+1.5VRUN_HPLL +1.5VRUN_DPLLA

+1.5VRUN_MPLL

+1.5VRUN_DPLLB

+1.5VRUN_QTVDAC

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+2.5V_RUN

+2.5V_RUN

+2.5V_RUN

+1.8V_SUS

+1.05V_VCCP

+1.05V_VCCP

+1.05V_VCCP

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

+1.05V_VCCP

+1.5V_RUN

+1.5V_RUN

Title



Calistoga(5 of 5)




close pin B31

Route VSSA_TVBG GND from GMCH todecoupling cap ground lead and thenconnect to the GND plane.

CRB 270uF

Route VSSA_TVBG GND from GMCH todecoupling cap ground lead and thenconnect to the GND plane.

CRTDAC: Route FBwithin 3" of Calistoga

Route VSSACRTDAC gnd from GMCH todecoupling cap ground lead and thenconnect to the gnd plane.

Route +2.5VRUN from GMCH pinN33 todecoupling cap (C66)

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_B_MA11

V_DDR_MCH_REF

DDR_CKE3_DIMMA

M_CLK_DDR3

M_CLK_DDR2

M_CLK_DDR#3

M_CLK_DDR#2

DDR_CKE3_DIMMA

DDR_CS2_DIMMA#

CLK_SCLK

DDR_B_MA1

DDR_B_MA10

DDR_B_MA3

DDR_B_MA9 DDR_B_MA7DDR_B_MA12

DDR_B_MA5

DDR_B_WE#

DDR_A_D9

DDR_A_D3

DDR_A_D13

DDR_A_D5DDR_A_D6

DDR_A_D7

DDR_A_D15

DDR_A_D24

DDR_A_D21

DDR_A_D23

DDR_A_D17

DDR_A_D19

DDR_A_D14

DDR_A_D28

DDR_A_D27

DDR_A_D36

DDR_A_D60

DDR_A_D43

DDR_A_D49DDR_A_D48

DDR_A_D63DDR_A_D62

DDR_A_D61

DDR_A_DQS1

DDR_A_DQS0

DDR_A_DQS2

DDR_A_DM3

DDR_A_DM1

DDR_A_DM2

DDR_A_DQS4

DDR_A_DQS6

DDR_A_DQS7

CLK_SDATA

DDR_CKE2_DIMMA

DDR_B_MA8

DDR_CS3_DIMMA#

DDR_B_MA11

DDR_B_MA2DDR_B_MA0

DDR_B_MA4

DDR_B_MA6

DDR_B_CAS#

DDR_B_BS1DDR_B_RAS#

DDR_A_D1

DDR_A_D0

DDR_A_D2

DDR_A_D4

DDR_A_D11

DDR_A_D16

DDR_A_D10

DDR_A_D20

DDR_A_D22

DDR_A_D12DDR_A_D8

DDR_A_D29

DDR_A_D31

DDR_A_D18

DDR_A_D25

DDR_A_D34

DDR_A_D45

DDR_A_D53DDR_A_D52

DDR_A_D56

DDR_A_D58

DDR_A_D57

DDR_A_D59

DDR_A_DM6

DDR_A_DM4

DDR_A_DM5

DDR_A_DM7

DDR_B_MA13

DDR_A_DQS5

DDR_B_BS0

DDR_B_BS2

DDR_A_DQS#0

DDR_A_DQS#1

DDR_A_DQS#2

DDR_A_DQS3DDR_A_DQS#3

DDR_A_DQS#4

DDR_A_DQS#5

DDR_A_DQS#6

DDR_A_DQS#7

DDR_B_MA0

DDR_B_MA4

DDR_B_BS1

DDR_B_MA6

DDR_B_MA2

M_ODT2

M_ODT3

M_ODT2DDR_B_MA13

DDR_B_MA7

DDR_A_DM0

DDR_A_D47

DDR_CS2_DIMMA#DDR_B_RAS#

DDR_A_D46DDR_A_D44

DDR_A_D42

DDR_A_D35

DDR_A_D39DDR_A_D38

DDR_A_D32DDR_A_D37DDR_A_D33

DDR_A_D26 DDR_A_D30

M_ODT3

DDR_B_BS2

DDR_B_BS0DDR_B_MA10

DDR_B_CAS#DDR_B_WE#

DDR_CKE2_DIMMA

DDR_B_MA9

DDR_B_MA5

DDR_B_MA12

DDR_B_MA8

DDR_A_D41DDR_A_D40

DDR_B_MA3DDR_B_MA1

DDR_CS3_DIMMA#

PM_EXTTS#0

DDR_A_D54DDR_A_D55

DDR_A_D50DDR_A_D51

+0.9V_DDR_VTT

+0.9V_DDR_VTT

+3.3V_RUN

+1.8V_SUS

+1.8V_SUS +1.8V_SUS

+3.3V_RUN

DDR_A_DQS[0..7]

DDR_B_MA[0..13]

M_CLK_DDR3

M_CLK_DDR2

M_CLK_DDR#3

M_CLK_DDR#2

DDR_CKE3_DIMMA

DDR_CS2_DIMMA#

DDR_CKE2_DIMMA

DDR_CS3_DIMMA#

DDR_A_DQS#[0..7]

M_ODT2

M_ODT3

DDR_B_BS1

DDR_B_WE#DDR_B_RAS#

DDR_B_CAS#

DDR_B_BS0

DDR_B_BS2

V_DDR_MCH_REF

PM_EXTTS#0

DDR_A_DM[0..7]

CLK_SDATACLK_SCLK

DDR_A_D[0..63]

Title



DDRII-SODIMM SLOT1


Compal Electronics, Inc.Layout Note:Place these resistorclosely DIMM0,alltrace lengthMax=1.3"

Layout Note:Place near JDIM1

Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT

Layout Note:Place these resistorclosely DIMM0,alltrace length

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DDR_A_D5DDR_A_D6

DDR_SDQ5DDR_SDQ6

DDR_A_D2DDR_A_D1

DDR_A_D4DDR_A_D0

DDR_A_D3DDR_A_D7

DDR_A_D8DDR_A_D12

DDR_A_D14DDR_A_D15

DDR_A_D13DDR_A_D9

DDR_A_D11DDR_A_D10

DDR_A_D20DDR_A_D16

DDR_A_D18DDR_A_D22

DDR_A_D21DDR_A_D17

DDR_A_D23DDR_A_D19

DDR_A_D29DDR_A_D25

DDR_A_D27DDR_A_D26

DDR_A_D24DDR_A_D28

DDR_A_D31DDR_A_D30

DDR_SDQ2DDR_SDQ1

DDR_SDQ4DDR_SDQ0

DDR_SDQ3DDR_SDQ7

DDR_SDQ8DDR_SDQ12

DDR_SDQ14DDR_SDQ15

DDR_SDQ13DDR_SDQ9

DDR_SDQ11DDR_SDQ10

DDR_SDQ20DDR_SDQ16

DDR_SDQ18DDR_SDQ22

DDR_SDQ21DDR_SDQ17

DDR_SDQ23DDR_SDQ19

DDR_SDQ29DDR_SDQ25

DDR_SDQ27DDR_SDQ26

DDR_SDQ24DDR_SDQ28

DDR_SDQ31DDR_SDQ30

DDR_A_D35DDR_A_D38

DDR_A_D36DDR_A_D32

DDR_A_D37DDR_A_D33

DDR_A_D34DDR_A_D39

DDR_A_D40DDR_A_D42

DDR_A_D47DDR_A_D46

DDR_A_D41DDR_A_D45

DDR_A_D43DDR_A_D44

DDR_A_D49DDR_A_D48

DDR_A_D55DDR_A_D54

DDR_A_D53DDR_A_D52

DDR_A_D51DDR_A_D50

DDR_A_D57DDR_A_D56

DDR_A_D63DDR_A_D62

DDR_A_D61DDR_A_D60

DDR_A_D58DDR_A_D59

DDR_SDQ35DDR_SDQ38

DDR_SDQ36DDR_SDQ32

DDR_SDQ37DDR_SDQ33

DDR_SDQ34DDR_SDQ39

DDR_SDQ40DDR_SDQ42

DDR_SDQ47DDR_SDQ46

DDR_SDQ41DDR_SDQ45

DDR_SDQ43DDR_SDQ44

DDR_SDQ49DDR_SDQ48

DDR_SDQ55DDR_SDQ54

DDR_SDQ53DDR_SDQ52

DDR_SDQ51DDR_SDQ50

DDR_SDQ57DDR_SDQ56

DDR_SDQ63DDR_SDQ62

DDR_SDQ61DDR_SDQ60

DDR_SDQ58DDR_SDQ59


DDR_SDQS0DDR_SDQS#0

DDR_A_DQS1DDR_A_DQS#1 DDR_SDQS#1


DDR_SDQS1

DDR_SDQS2

DDR_SDQS#3DDR_A_DQS3DDR_A_DQS#3

DDR_SDQS3

DDR_A_DQS5

DDR_A_DQS4

DDR_SDQS5

DDR_SDQS4

DDR_SDQS#2

DDR_A_DQS#4

DDR_A_DQS#5

DDR_A_DQS#6DDR_A_DQS6

DDR_A_DQS#7DDR_A_DQS7

DDR_SDQS6

DDR_SDQS7

DDR_SDQS#5

DDR_SDQS#4

DDR_SDQS#6

DDR_SDQS#7

DDR_A_DM0 DDR_SDM0

DDR_A_DM1 DDR_SDM1

DDR_A_DM2 DDR_SDM2

DDR_A_DM3 DDR_SDM3

DDR_A_DM4 DDR_SDM4

DDR_A_DM5 DDR_SDM5

DDR_A_DM6 DDR_SDM6

DDR_A_DM7 DDR_SDM7

V_DDR_MCH_REF

DDR_A_MA0DDR_A_MA1DDR_A_MA2DDR_A_MA3DDR_A_MA4DDR_A_MA5DDR_A_MA6DDR_A_MA7DDR_A_MA8DDR_A_MA9DDR_A_MA10DDR_A_MA11DDR_A_MA12DDR_A_MA13

M_CLK_DDR#0M_CLK_DDR0M_ODT0

DDR_CKE0DDR_A_BS0

DDR_CS0#

DDR_A_WE#DDR_A_CAS#DDR_A_RAS#

V_DDR_MCH_REF

V_DDR_MCH_REF


M_CLK_DDR#1DDR_CKE0DDR_A_BS0

M_CLK_DDR1M_ODT0

DDR_A_MA0DDR_A_MA1DDR_A_MA2DDR_A_MA3DDR_A_MA4

DDR_A_MA8DDR_A_MA9DDR_A_MA10DDR_A_MA11DDR_A_MA12DDR_A_MA13

DDR_CS0#


V_DDR_MCH_REF


M_CLK_DDR#1DDR_CKE0DDR_A_BS0

M_CLK_DDR1M_ODT0

DDR_CS0#


DDR_CKE0M_CLK_DDR#0M_CLK_DDR0

DDR_A_BS0

DDR_CS0#


DDR_SDQS#2DDR_SDQS2

DDR_SDM2

DDR_SDQS#4DDR_SDQS4

DDR_SDM4DDR_SDQS#6DDR_SDQS6

DDR_SDM6

DDR_A_BS1 DDR_A_BS1

DDR_A_BS1 DDR_A_BS1

M_ODT0

DDR_SDM0DDR_SDQS#0DDR_SDQS0

DDR_SDQ0

DDR_SDQ2

DDR_SDQ1

DDR_SDQ5

DDR_SDQ4

DDR_SDQ7

DDR_SDQ3

DDR_SDQ6

DDR_SDQ16

DDR_SDQ17DDR_SDQ18

DDR_SDQ19DDR_SDQ20

DDR_SDQ22

DDR_SDQ23

DDR_SDQ21

DDR_SDQ32

DDR_SDQ33

DDR_SDQ34

DDR_SDQ35

DDR_SDQ36

DDR_SDQ37DDR_SDQ38

DDR_SDQ39DDR_SDQ48

DDR_SDQ49

DDR_SDQ50

DDR_SDQ51DDR_SDQ52

DDR_SDQ53

DDR_SDQ54

DDR_SDQ55

DDR_A_MA5DDR_A_MA6DDR_A_MA7

DDR_A_BS2

DDR_A_BS2 DDR_A_BS2

DDR_A_BS2

+1.8V_SUS +1.8V_SUS

+1.8V_SUS +1.8V_SUS+1.8V_SUS

DDR_A_D[0..63]

DDR_A_DQS[0..7]

DDR_A_MA[0..13]

DDR_A_DQS#[0..7]

DDR_SDQS#[0..7]

DDR_SDQ[0..63]

DDR_SDQS[0..7]

V_DDR_MCH_REF M_CLK_DDR0 M_CLK_DDR#0

M_ODT0

DDR_CKE0 DDR_A_BS0

DDR_A_WE#

DDR_A_RAS# DDR_A_CAS#

DDR_CS0#

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1

DDR_A_DM[0..7]

DDR_SDM[0..7]

DDR_A_BS2

Title



DDRII-ON BOARD I




Place clost to each VREF pin

Layout Note:Place near U4,U5,U6,U7

U7

K4T1G084QA-ZCD5_FBGA68~D

DQS#E8DM/RDQSF3DQ0G8DQ1G2DQ2H7DQ3H3DQ4H1DQ5H9DQ6F1DQ7F9

DQSF7

VREFJ2

A0M8A1M3A2M7A3N2A4N8A5N3A6N7A7P2A8P8A9P3A10M2A11P7A12R2A13R8

NCA1

NCR3NCR7

NU/RDQSE2

NCA2NCA8NCA9

VDDQ E9VDDQ G1VDDQ G3VDDQ G7VDDQ G9

VDD E1VDD J9VDD M9VDD R1

VDDL J1

ODT K9CK J8

CK# K8CKE K2BA0 L2BA1 L3BA2 L1CS# L8

RAS# K7CAS# L7WE# K3

VSSQ E7VSSQ F2VSSQ F8VSSQ H2VSSQ H8

VSS E3VSS J3VSS N1VSS P9

VSSDL J7

NC W8NC W9NC W1NCW2

RN36

10_0404_4P2R_5%~D

1 42 3

RN15

10_0404_4P2R_5%~D

1 42 3

R571 10_0402_5%~D1 2

RN30

10_0404_4P2R_5%~D

1 42 3

RN62

10_0404_4P2R_5%~D

1 42 3

RN60

10_0404_4P2R_5%~D

1 42 3

C662

0.1U_0402_16V4Z~D

1

2

RN19

10_0404_4P2R_5%~D

1 42 3

RN48

10_0404_4P2R_5%~D

1 42 3

C654

2.2U_0603_6.3V6K~D

1

2

C658

2.2U_0603_6.3V6K~D

1

2

R569 10_0402_5%~D1 2

RN17

10_0404_4P2R_5%~D

1 42 3

RN39

10_0404_4P2R_5%~D

1 42 3

C672

2700P_0402_50V7K~D

1

2

C668

2700P_0402_50V7K~D

1

2

C664

0.1U_0402_16V4Z~D

1

2

R568 10_0402_5%~D1 2

RN51

10_0404_4P2R_5%~D

1 42 3

C670

2700P_0402_50V7K~D

1

2

C666

2700P_0402_50V7K~D

1

2

RN24

10_0404_4P2R_5%~D

1 42 3

RN44

10_0404_4P2R_5%~D

1 42 3

RN41

10_0404_4P2R_5%~D

1 42 3

RN21

10_0404_4P2R_5%~D

1 42 3

RN54

10_0404_4P2R_5%~D

1 42 3

RN27

10_0404_4P2R_5%~D

1 42 3

C669

2700P_0402_50V7K~D

1

2

RN66

10_0404_4P2R_5%~D

1 42 3

U5



DQSF7

VREFJ2


NCA1

NCR3NCR7

NU/RDQSE2

NCA2NCA8NCA9



VDDL J1

ODT K9CK J8





VSSDL J7

NC W8NC W9NC W1NCW2

C629

0.1U_0402_16V4Z~D

1

2RN26

10_0404_4P2R_5%~D

1 42 3

C656

2.2U_0603_6.3V6K~D

1

2

RN47

10_0404_4P2R_5%~D

1 42 3

RN59

10_0404_4P2R_5%~D

1 42 3

R572 10_0402_5%~D1 2

RN32

10_0404_4P2R_5%~D

1 42 3

R567 10_0402_5%~D1 2

C157

0.1U_0402_16V4Z~D

1

2

RN23

10_0404_4P2R_5%~D

1 42 3

RN68

10_0404_4P2R_5%~D

1 42 3

C655

2.2U_0603_6.3V6K~D

1

2

RN65

10_0404_4P2R_5%~D

1 42 3

C657

2.2U_0603_6.3V6K~D

1

2

RN63

10_0404_4P2R_5%~D

1 42 3

C663

0.1U_0402_16V4Z~D

1

2

RN18

10_0404_4P2R_5%~D

1 42 3

C665

2700P_0402_50V7K~D

1

2

R573 10_0402_5%~D1 2

C661

0.1U_0402_16V4Z~D

1

2

RN53

10_0404_4P2R_5%~D

1 42 3

RN16

10_0404_4P2R_5%~D

1 42 3

R566 10_0402_5%~D1 2

U6



DQSF7

VREFJ2


NCA1

NCR3NCR7

NU/RDQSE2

NCA2NCA8NCA9



VDDL J1

ODT K9CK J8





VSSDL J7

NC W8NC W9NC W1NCW2

RN14

10_0404_4P2R_5%~D

1 42 3

RN35

10_0404_4P2R_5%~D

1 42 3

C160

0.1U_0402_16V4Z~D

1

2

U4



DQSF7

VREFJ2


NCA1

NCR3NCR7

NU/RDQSE2

NCA2NCA8NCA9



VDDL J1

ODT K9CK J8





VSSDL J7

NC W8NC W9NC W1NCW2

C158

2.2U_0603_6.3V6K~D

1

2

RN56

10_0404_4P2R_5%~D

1 42 3

R570 10_0402_5%~D1 2

RN33

10_0404_4P2R_5%~D

1 42 3

RN42

10_0404_4P2R_5%~D

1 42 3

RN45

10_0404_4P2R_5%~D

1 42 3

C671

2700P_0402_50V7K~D

1

2

C659

0.1U_0402_16V4Z~D

1

2

C660

0.1U_0402_16V4Z~D

1

2

RN29

10_0404_4P2R_5%~D

1 42 3

RN38

10_0404_4P2R_5%~D

1 42 3

C159

0.1U_0402_16V4Z~D

1

2

RN69

10_0404_4P2R_5%~D

1 42 3

RN20

10_0404_4P2R_5%~D

1 42 3

RN50

10_0404_4P2R_5%~D

1 42 3

C667

2700P_0402_50V7K~D

1

2

RN57

10_0404_4P2R_5%~D

1 42 3

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

CLK_SCLKCLK_SDATA

M_CLK_DDR0

DDR_A_MA10

DDR_A_WE#

DDR_A_MA0

DDR_A_MA1

DDR_A_MA3

DDR_A_MA8

DDR_A_BS0

DDR_CS0#

DDR_A_CAS#

DDR_A_BS1

DDR_A_MA12DDR_A_MA7

DDR_A_MA6

DDR_A_MA5

DDR_A_MA4DDR_A_MA2

DDR_A_MA9

M_CLK_DDR#0

DDR_A_MA11DDR_A_RAS#

DDR_CS0#

DDR_CKE0M_CLK_DDR#0M_CLK_DDR0M_ODT0

DDR_A_BS0


V_DDR_MCH_REF


V_DDR_MCH_REF


DDR_CKE0M_CLK_DDR#0M_CLK_DDR0M_ODT0

DDR_A_BS0

DDR_CS0#


DDR_A_MA0DDR_A_MA1DDR_A_MA2DDR_A_MA3DDR_A_MA4DDR_A_MA5DDR_A_MA6DDR_A_MA7DDR_A_MA8DDR_A_MA9DDR_A_MA10DDR_A_MA11DDR_A_MA12

V_DDR_MCH_REF

DDR_A_MA13

M_CLK_DDR#1

M_CLK_DDR#1

M_ODT0

DDR_A_BS0

M_CLK_DDR1

M_CLK_DDR1

DDR_CS0#


DDR_SDQS1DDR_SDQS#1DDR_SDM1

DDR_SDQS#3DDR_SDQS3

DDR_SDM3

DDR_SDQ40

DDR_SDQ41

DDR_SDQ42DDR_SDQ43

DDR_SDQ44

DDR_SDQ45

DDR_SDQ46

DDR_SDQ47

DDR_SDQS#5DDR_SDQS5

DDR_SDM5

DDR_SDQ56

DDR_SDQ57

DDR_SDQ58

DDR_SDQ59

DDR_SDQ60

DDR_SDQ61

DDR_SDQ62

DDR_SDQ63

DDR_SDQS#7DDR_SDQS7

DDR_SDM7

DDR_A_MA0DDR_A_MA1DDR_A_MA2DDR_A_MA3DDR_A_MA4DDR_A_MA5DDR_A_MA6DDR_A_MA7DDR_A_MA8DDR_A_MA9DDR_A_MA10DDR_A_MA11DDR_A_MA12

V_DDR_MCH_REF

DDR_A_MA13

M_CLK_DDR#1M_CLK_DDR1M_ODT0

DDR_A_BS0

DDR_CS0#


DDR_A_BS1DDR_A_BS1

DDR_A_BS1DDR_A_BS1

M_ODT0

DDR_CKE0 DDR_CKE0

DDR_CKE0

DDR_SDQ8

DDR_SDQ9

DDR_SDQ10

DDR_SDQ11DDR_SDQ12DDR_SDQ13

DDR_SDQ14

DDR_SDQ15

DDR_SDQ25

DDR_SDQ24

DDR_SDQ26

DDR_SDQ27

DDR_SDQ28DDR_SDQ29

DDR_SDQ30

DDR_SDQ31

DDR_A_BS2DDR_A_BS2

DDR_A_BS2DDR_A_BS2

DDR_A_BS2 DDR_A_MA13

+0.9V_DDR_VTT

+0.9V_DDR_VTT

+3.3V_RUN

+3.3V_RUN

+1.8V_SUS+1.8V_SUS

+1.8V_SUS +1.8V_SUS

+1.8V_SUS DDR_SDQS#[0..7]

DDR_SDQ[0..63]

DDR_SDQS[0..7]

DDR_A_MA[0..13]

DDR_A_WE#

DDR_A_BS0

DDR_CS0#

DDR_A_CAS#

DDR_A_BS1

DDR_A_RAS#

DDR_CS0#

M_CLK_DDR0 M_CLK_DDR#0

DDR_CKE0

M_ODT0

DDR_A_BS0

DDR_A_WE#

DDR_A_RAS# DDR_A_CAS#

V_DDR_MCH_REF

M_CLK_DDR#1 M_CLK_DDR1

DDR_A_BS1

M_ODT0

DDR_CKE0

DDR_SDM[0..7]

CLK_SDATACLK_SCLK

DDR_A_BS2

DDR_A_BS2

Title


Date: Sheet o fLA-3741P 0.1DDRII-ON BOARD II



MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Layout Note:Place near U8,U9,U10,U11

Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V_DDR_VTT

Layout Note:Place these resistorclosely DIMM0,alltrace lengthMax=1.3"

Layout Note:Place these resistorclosely DIMM0,alltrace length

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

+FAN1_VOUT

THERMATRIP1#

THERMATRIP2#

REM_DIODE1_PREM_DIODE1_N

FAN1_TACH

THERMATRIP3#

THERMATRIP2#

+3VSUS_THRM

THERMATRIP1#

LDO_SET

+3V_LD

OIN

REM_DIODE3_NREM_DIODE3_P

+FAN1_VOUT

SNIFFER_GREEN#SNIFFER_YELLOW#

LDO_SET

+3.3V_ALW

+RTC_CELL

+5V_RUN

+RTC_CELL

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN

+2.5V_RUN

+3.3V_SUS

+3.3V_SUS+3.3V_SUS

+3.3V_SUS

+3.3V_SUS+3.3V_SUS

+1.05V_VCCP

+1.05V_VCCP

+2.5V_RUN

FAN1_TACH

ATF_INT#

THERMTRIP_SIO

THERMTRIP_MCH#

H_THERMTRIP#

DAT_SMB

H_THERMDA

H_THERMDC

SUSPWROK

POWER_SW#

ICH_PWRGD#

ACAV_IN

THERM_STP#

SNIFFER_GREEN#SNIFFER_YELLOW#

2.5V_RUN_PWRGD

CLK_SMB

Title



FAN & Thermal Sensor



FAN1 Control and Tachometer

Place under CPU



SMBUS ADDRESS : 2FPlace cap close to theGuardian pins as possible.

REM_DIODE3_N, REM_DIODE3_P routing together.Trace width / Spacing = 10 / 10 mil

Place near the bottom SODIMM

Place C341 close to the Guardianpins as possible

Place C197 close to the Guardianpins as possible

Use Rev:CNeed create P/N

For Vmargin pop R578 andR158=30K,R158=1K for production.

SET local temperature on M/BVSET=(Tp-70)/21 =3.3V*R157/(R152+R157) =1.044Tp=92 degree

C2030.1U_0402_16V4Z~D@

1

2

R152147K_0402_1%~D

1

2

R150 1K_0402_5%~D

1 2

R15768K_0402_1%~D

1

2

C

2

0

6

1

U

_

0

6

0

3

_

1

0

V

4

Z

~

D

1

2

R15310K_0402_5%~D

1

2

EB

C

Q

6

M

M

S

T

3

9

0

4

-

7

-

F

_

S

O

T

3

2

3

~

D

2

3

1

D3RB751S40T1_SOD523-2~D

@

2

1

C1960.1U_0402_16V4Z~D

1

2

C

2

0

0

2

2

0

0

P

_

0

4

0

2

_

5

0

V

7

K

~

D

1

2

C2070.1U_0402_16V4Z~D@

1

2

C1950.1U_0402_16V4Z~D

1

2

C1932200P_0402_50V7K~D

1

2R143

10K_0402_5%~D

12

C2052200P_0402_50V7K~D

@

1

2

C

1

9

2

2

2

U

_

0

8

0

5

_

6

.

3

V

6

M

~

D

@

1

2

R148 1K_0402_5%~D

1 2

EB

C

Q8 MMST3904-7-F_SOT323~D

2

3

1

R14449.9_0603_1%~D 1 2

R57831.6K_0402_1%~D

@

1

2

R

1

5

5

1

K

_

0

4

0

2

_

5

%

~

D

1

2

C190100P_0402_50V8J~D@

1

2

C

2

0

2

1

0

U

_

0

8

0

5

_

6

.

3

V

6

M

~

D

1

2

R1581K_0603_5%~D

1

2

R1548.2K_0402_5%~D

1

2

C

2

0

8

1

0

U

_

0

8

0

5

_

1

0

V

4

Z

~

D

1

2

R151 8.2K_0402_5%~D

1 2

C2010.1U_0402_16V4Z~D

1

2

U13

EMC4000_QFN40~D

SMDATA7SMBCLK8

LDO_SHDN#_ADDR23

DP235DN234

+3V_SUS12VSUS_PWRGD21

+RTC_PWR3V18

+3V_PWROK#13

POWER_SW#38

THERMTRIP1#14

THERMTRIP2#15

THERMTRIP3#16

VSET39HW_LOCK#29VSS9

ATF_INT# 17

VCP 3

LDO_POK 31

DN1 36DP1 37

THERMTRIP_SIO 30ACAV_CLR 4

SYS_SHDN# 22

DP31DN32

VDD_5V 5

FAN_OUT6

GPIO110GPIO211GPIO319GPIO420

LDO_SET 24

LDO_OUT 25

LDO_IN 26

LDO_OUT 27

LDO_IN 28

GPIO532

FAN_DAC33

VCP 40

THERMAL PAD 41

EB

C

Q

7

M

M

S

T

3

9

0

4

-

7

-

F

_

S

O

T

3

2

3

~

D

2

3

1

R14210K_0402_5%~D

1

2

R14710K_0402_5%~D

1

2

R160 0.27_1210_5%~D

12

C1990.1U_0402_16V4Z~D

1

2

JFAN1

MOLEX_53780-0370~D

112233

GND 4GND 5

R1457.5K_0402_5%~D

1 2

R15610K_0402_5%~D@

12

C1982200P_0402_50V7K~D@

1

2

EB

C

Q

5

M

M

S

T

3

9

0

4

-

7

-

F

_

S

O

T

3

2

3

~

D

2

3

1

C

1

9

1

2

2

U

_

0

8

0

5

_

6

.

3

V

6

M

~

D

1

2

R149

2.2K_0402_5%~D

1 2

C2090.1U_0402_16V4Z~D

1

2

C1940.1U_0402_16V4Z~D

1

2

C1972200P_0402_50V7K~D

1

2

C2042200P_0402_50V7K~D

1

2

R1468.2K_0402_5%~D

1

2

R159

2.2K_0402_5%~D

1 2

55

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LCD_TST

LCD_DDCCLKLCD_DDCDATA

LCD_A1-

LCD_A0+

LCD_A2-

LCD_A0-

LCD_A2+

LCD_A1+

LCD_ACLK+LCD_ACLK-

FPBACK_ENBIA_PWM

PANEL_BKEN

LAMP_STAT#

LAMP_D_STAT#

BIA_PWM

+LCDVDD

+PWR_SRC

+5V_ALW

+LCDVDD

+LCDVDD

+15V_SUS

+GFX_PWR_SRC+GFX_PWR_SRC

+3.3V_RUN

+3.3V_RUN

+3.3V_RUN+15V_SUS

SBAT_SMBDAT

RUN_ON

LCD_TST

LCD_A0- LCD_A0+

LCD_A1- LCD_A1+

LCD_A2- LCD_A2+

LCD_ACLK- LCD_ACLK+

ENVDD

FPBACK_EN

PANEL_BKEN

BIA_PWM

LCD_DDCDATA LCD_DDCCLK

SBAT_SM

dell d430 la-3741p service manual

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