demo course file

7/29/2019 Demo Course File

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LORDS INSTITUTE OF ENGINEERING AND TECHNOLGY PAGE NO1

ame of faulty:sayyada mubeen & chaitanya page no1

LORDS INSTITUTE OF ENGINEERING AND TECHNOLOGYHimayathsagar, Hyderabad-8

COURSE FILE

NAME OF THE FACULTY:K.P.CHAITANYA & SAYYADA MUBEEN

DEPARTMENT: CSE

SUBJECT:COMPUTER ORGANIZATION

YEAR(SEMESTER)/BRANCH: II YR AND III YR CSE


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CERTIFICATE

This is to certify that Mr./Ms.__K.P.CHAITANYA ,SAYYADA MUBEEN

Asst.Prof./Assoc.Prof./Prof. of CSE department has completed all the

requirement of the Course file of COMPUTER ORGANIZATION_

B.Tech/M.Tech,______Semester as per the University requirement.

Head of the Department PRINCIPAL


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CONTENTS OF COURSE FILE

S.No CONTENT Page No.

1. Syllabus2. Academic Calender

3. Plan of Syllabus Coverage

4. Teaching Diary

5. Class work Time Table

6. Hard Copy of Course Material Subjective (Unit Wise)

7. Soft Copy of Course Material Subjective (Unit Wise)

8. Hard Copy of Objective Type Questions(Multiple choice/Fillin the blanks/True or False/Match the following etc.)

9. Soft Copy of Objective Type Questions(Multiple choice/Fill inthe blanks/True or False/Match the following etc.)

10. OHP Sheets (Slides if any)

11. Power Point Presentations Soft and Hard Copy (if any)

12. Mid Term Exam Question Papers (Objective and Subjective)

13. Solution to Mid Term Exam Question papers

14. University End Exam Question Papers

15. Solution to University End Exam Question Papers

16. Assignments (Unit Wise) Question Papers and AnswerScripts of Students

17. Unit Test(Unit Wise) Question Papers and Answer Scripts ofStudents

18. Additional Solved Problems19. Add-on Course Material


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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

HYDERABAD

II Year B.Tech. CSE -II Sem T P C

4+1* 0 4

COMPUTER ORGANIZATION

UNIT I :

BASIC STRUCTURE OF COMPUTERS : Computer Types, Functional unit, Basic OPERATIONAL concepts, Bus

structures, Software, Performance, multiprocessors and multi computers. Data Representation. Fixed Point

Representation. Floating Point Representation. Error Detection codes.

UNIT II :

REGISTER TRANSFER LANGUAGE AND MICROOPERATIONS : Register Transfer language.Register Transfer

Bus and memory transfers, Arithmetic Mircrooperatiaons, logic micro operations, shift micro operations, Arithmetic

logic shift unit. Instruction codes. Computer Registers Computer instructions

Instruction cycle.

Memory Reference Instructions. Input Output and Interrupt. STACK organization. Instruction formats. Addressing

modes. DATA Transfer and manipulation. Program control. Reduced Instruction set computer.

UNIT III :

MICRO PROGRAMMED CONTROL : Control memory, Address sequencing, microprogram example, design of

control unit Hard wired control. Microprogrammed control

UNIT IV :

COMPUTER ARITHMETIC :Addition and subtraction, multiplication Algorithms, Division Algorithms, Floating point

Arithmetic operations. Decimal Arithmetic unit Decimal Arithmetic operations.

UNIT V :

THE MEMORY SYSTEM : Basic concepts semiconductor RAM memories. Read-only memories Cache memories

performance considerations, Virtual memories secondary storage. Introduction to RAID.


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UNIT-VI

INPUT-OUTPUT ORGANIZATION : Peripheral Devices, Input-Output Interface, Asynchronous data transfer Modes

of Transfer, Priority Interrupt Direct memory Access, Input Output Processor (IOP) Serial communication;

Introduction to peripheral component, Interconnect (PCI) bus. Introduction to

standard serial communication protocols like RS232, USB, IEEE1394.

UNIT VII :

PIPELINE AND VECTOR PROCESSING : Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction Pipeline,

RISC Pipeline Vector Processing, Array Processors.

UNIT VIII :

MULTI PROCESSORS : Characteristics or Multiprocessors, Interconnection Structures, Interprocessor Arbitration.

InterProcessor Communication and Synchronization Cache Coherance. Shared Memory Multiprocessors.

TEXT BOOKS :

1. Computer Organization Carl Hamacher, Zvonks Vranesic, SafeaZaky, Vth Edition, McGraw Hill.

2. Computer Systems Architecture M.Moris Mano, IIIrd Edition, Pearson/PHI

REFERENCES :

1. Computer Organization and Architecture William Stallings Sixth Edition, Pearson/PHI

2. Structured Computer Organization Andrew S. Tanenbaum, 4th Edition PHI/Pearson

3. Fundamentals or Computer Organization and Design, - Sivaraama Dandamudi Springer Int. Edition.

4. Computer Architecture a quantitative approach, John L. Hennessy and David A. Patterson, Fourth Edition Elsevier

5.Computer Architecture: Fundamentals and principles of Computer Design, Joseph D. Dumas II, BS Publication.


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PLAN OF SYLLABUS COVERAGE

SUBJECT:

YEAR/SEMESTER/BRANCH:

TOTAL NO. OF WEEKS AS PER ACADEMIC CALENDER:

S.No. Unit Syllabus to be Covered Period Week1 1 Basic structure of computer

Computer types and introduction

Functional units and basic concepts

Bus structure

s/w performance

Multiprocers and Multicomputer

Data types complements

Data representation and fixed point

Error Detection codes

2 2 RTL and Microoperatins

Register transfer languageBus and Memory transfer

Arthemetic Micro operations

Logic micro operations

ALU shift Instruction codes

Computer Instruction

Input Output Interupt

Stack Organisation

Micro program ,Micro program control

3 3 Micro pragramed control

Control Memory

Address sequenceAdressing modes

Data transfer and manipulation

Reduced instruction set of computer

4 4 Computer Arthemmetic


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Sign of the Concerned Faculty Head of the Department


PLAN OF SYLLABUS COVERAGE

SUBJECT:

YEAR/SEMESTER/BRANCH:

TOTAL NO. OF WEEKS AS PER ACADEMIC CALENDER:

S.No. Unit Syllabus to be Covered Period Week4 Multipling alogarithim,Addition

Subtraction alogarithim

Division algorithim

Floating point algorithim

Division problems

5 5 Memory hierarchy system

Auxilary Associative

Cache memory

Virtual Memory management

6 6 Peripheral Devices input output

Data transmission modePriority DMA

Serial Communication

Data Modes

7 7 Parallel processing

Pipeline Arithmetic

Instructing pipeline

RISC pipeline

Vector processing features

Array processing

8 8 Multiprocessors

StructuresIPC

Synchronization

Cache coherence

Sign of the Concerned Faculty Head of the Department


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TEACHING DIARY

S.No Date No.ofPeriods

CumulativePeriods

Syllabus Covered Sign

1 21/7 2 2 Basic structure of computer

2 23/7 2 4 Computer types and introduction3 26/7 1 5 Functional units and basic concepts

4 27/7 1 6 Bus structure

5 28/7 1 7 s/w performance

6 29/7 1 8 Multiprocers and Multicomputer

7 31/7 1 9 Data types complements

8 3/8 1 10 Data representation and fixed point

9 4/8 1 11 Error Detection codes

10 5/8 2 13 RTL and Microoperatins

11 6/8 1 14 Register transfer language

12 9/8 1 15 Bus and Memory transfer

13 10/8 1 16 Arthemetic Micro operations

14 16/8 1 17 Logic micro operations

15 17/8 1 18 ALU shift Instruction codes

16 18/8 1 19 Computer Instruction

17 19/8 1 20 Input Output Interupt

18 21/8 2 22 Stack Organisation

19 23/8 2 24 Micro program ,Micro program control

20 24/8 1 25 Micro pragramed control

21 24/8 1 26 Control Memory

22 25/8 1 27 Address sequence

23 25/8 1 28 Adressing modes24 26/8 1 29 Computer Arthemmetic



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TEACHING DIARY


CumulativePeriods


25 28/8 1 30 Multipling alogarithim,Addition26 28/8 1 31 Subtraction alogarithim

27 2/9 2 33 Division algorithim

28 3/9 2 35 Floating point algorithim

29 6/9 2 37 Memory hierarchy system

30 7/9 1 38 Auxilary Associative

31 8/9 1 39 Cache memory

32 8/9 1 40 Virtual Memory management

33 16/9 1 41 Peripheral Devices input output

34 17/9 1 42 Data transmission mode

35 18/9 1 43 Priority DMA

36 20/9 1 44 Serial Communication

37 21/9 2 45 Data Modes

38 28/9 1 46 Parallel processing

39 29/9 2 48 Pipeline Arithmetic

40 30/9 1 49 Instructing pipeline

41 4/10 1 50 RISC pipeline and vector processing

42 5/10 1 51 Array processing

43 8/10 1 52 Multiprocessors

44 9/10 2 54 Structures

45 11/10 2 56 IPC

46 12/10 2 58 Synchronization

47 14/10 1 59 Cache coherence

48 18/10 1 60 cache



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TEACHING DIARY


CumulativePeriods


49 20/10 1 61 Revision on 1, 250 21/10 2 63 Revision of 3,4

51 25/10 2 65 Revision of 5

52 27/10 3 68 Revision of 6,7

53 27/10 2 70 Revision of 8

55 28/10 3 73 Revision Test



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TIME TABLE

Day/Period I II III IV V VI VII VIII

Monday L co

Tuesday U co

Wednesday N co

Thursday co CCo(tut)

Friday H

Saturday co

COURSE FILE LORDS INSTITUTE OFENGINEERING & TECHNOLOGY PAGE NO:


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SUBJECT:

YEAR/SEMESTER:

BRANCH:

NAME OF THE FACULTY:

UNIT-1

BASIC STRUCTURE OF COMPUTERS

Computer Types

Digital Computer is a fast electronic calculating machine that accepts digitized input information, processes it according to a list of internally stored instructions, and produces the resulting output information.

Many types of computers exist that differ widely in Size, Cost,Computational Power and

intended Use Personal Computer/ Desktop computers Portable Notebook Computers Work Stations Enterprise System Servers Super Computers

Figure 1.1 Block diagram of a digital computer.

Functional Units


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FunctionalUnits

A digital computer consists of five functionally independent parts. Input

Output Memory Unit Arithmetic and Logic Unit Control Unit

INPUT UNIT: computers accept coded information through input units, which reads thedata.

Ex: Keyboard, Mouse, joy sticks. Output Units:

Table (1.1) Basic identities of Boolean Algebra.

BUS STRUCTURES

There are different types of buses

They are

a)controll bus

b)data bus

A bus structure comprises a plurality of driver circuits, each driver circuit comprising an inputfor a first signal and a terminal for an output signal wherein each driver circuit is capable of

providing the output signal at the terminal upon receipt of the first signal, a parallel buscomprising a plurality of output signal lines at a receiving end, being connectable to a target

component, each of the signal lines extending at least from the receiving end to the terminal of a

different one of the plurality of driver circuits, such that a length of the output signal linebetween the receiving end and the respective driver circuits decreases in a connection order

among the plurality of driver circuits, and a signal line coupled to each of the inputs of the driver

circuits in the connection order.

MULTIPROCESSORS AND MULTICOMPUTERS

multicomputer-- A computer made up of several computers. The term generally refers to an

architecture in which each processor has its own memory rather than multiple processors with a

shared memory.


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Something similiar to parallel computing.

Distributed computing deals with hardware and software systems containing more than one

processing

element or storage element, concurrent processes, or multiple programs, running under a loosely

or tightly controlled regime. A multicomputer may be considered to be either a loosely coupledNUMA computer or a tightly coupled cluster. Multicomputers are commonly used when strong

computer power is required in an environment with restricted physical space or electrical power.

Common suppliers include Mercury Computer Systems, CSPI, and SKY Computers.

Common uses include 3D medical imaging devices and mobile radar.

In distributed computing a program is split up into parts that run simultaneously on multiple

computers communicating over a network. Distributed computing is a form of parallel

computing, but parallel computing is most commonly used to describe program parts running

simultaneously on multiple processors in the same computer. Both types of processing requiredividing a program into parts thatcan run simultaneously, but distributed programs often must

deal with heterogeneous environments, network links of varying latencies, and unpredictablefailures in the network or the computers.

multiprocessor-- A multiprocessor system is simply a computer that has more than one CPU on

its motherboard. If the operating system is built to take advantage of this, it can run differentprocesses(or different threads belonging to the same process) on different CPUs.

Multiprocessing is the use of two or more central processing units (CPUs) within a single

computer system. The term also refers to the ability of a system to support more than one

processor and/or the ability to allocate tasks between them.[1] There are many variations on thisbasic theme, and the definition of multiprocessing can vary with context, mostly as a function of

how CPUs are defined (multiple cores on one die, multiple chips in one package, multiple

packages in one system unit, etc.).

BASIC OPERATONAL CONCEPTS

DATA REPRESENTATION

Information that a Computer is dealing with

* Data

- Numeric Data

Numbers( Integer, real)

- Non-numeric Data


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Letters, Symbols

* Relationship between data elements

- Data Structures

Linear Lists, Trees, Rings, etc

NUMERIC DATA REPRESENTATION

R = 10 Decimal number system, R = 2 Binary

R = 8 Octal, R = 16 Hexadecimal

Radix point(.) separates the integer

portion and the fractional portion

Data

Numeric data - numbers(integer, real)

Non-numeric data - symbols, letters

Number System

Nonpositional number system

- Roman number system

Positional number system

- Each digit position has a value called a weight associated with it

- Decimal, Octal, Hexadecimal, Binary

Base (or radix) R number

- Uses R distinct symbols for each digit

- Example AR

= an-1

an-2

...a1

a0

.a-1

a-m

Table for addition is infinite

--> Impossible to build, very expensive even

if it can be built


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* Positional Number System

- Table for Addition is finite

--> Physically realizable, but cost wise

the smaller the table size, the less

expensive --> Binary is favorable to Decimal

0 1 2 3 4 5 6 7 8 9

0 0 1 2 3 4 5 6 7 8 9

1 1 2 3 4 5 6 7 8 9 10

2 2 3 4 5 6 7 8 9 1011

3 3 4 5 6 7 8 9 101112

4 4 5 6 7 8 9 10111213

5 5 6 7 8 9 1011121314

6 6 7 8 9 101112131415

7 7 8 9 10111213141516

8 8 9 1011121314151617

9 9 101112131415161718

REPRESENTATION OF NUMBERS - POSITIONAL NUMBERS

Decimal Binary Octal Hexadecimal

00 0000 00 0

01 0001 01 1

02 0010 02 2

03 0011 03 3

04 0100 04 4

05 0101 05 5

06 0110 06 6

07 0111 07 7


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08 1000 10 8

09 1001 11 9

10 1010 12 A

11 1011 13 B

12 1100 14 C

13 1101 15 D

14 1110 16 E

15 1111 17 F

CONVERSION OF BASES

Decimal to Base R number

Base R to Decimal Conversion

V(A) = ak k

A = an-1 an-2 an-3 a0 . a-1 a-m

(736.4)

8

= 7 x 82 + 3 x 81 + 6 x 80 + 4 x 8-1

= 7 x 64 + 3 x 8 + 6 x 1 + 4/8 = (478.5)10

(110110)2 = ... = (54)10

(110.111)2 = ... = (6.785)10

(F3)16 = ... = (243)10

(0.325)6 = ... = (0.578703703 .................)10

- Separate the number into its integer and fraction parts and convert each partseparately.

- Convert integer part into the base R number

successive divisions by R and accumulation of the remainders.

- Convert fraction part into the base R number


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successive multiplications by R and accumulation of integer digits

EXAMPLE

Convert 41.687510 to base 2.

Integer = 41

41

20 1

10 0

5 0

2 1

1 0

0 1

Fraction = 0.6875

0.6875

x 2

1.3750

x 2

0.7500

x 2

1.5000

x 2

1.0000

(41)10 = (101001)2 (0.6875)10 =(0.1011)2

(41.6875)10 = (101001.1011)2

Convert (63)10 to base 5: (223)5

Convert (1863)10 to base 8: (3507)8


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Convert (0.63671875)10 to hexadecimal: (0.A3)16

COMPLEMENT OF NUMBERS

Two types of complements for base R number system:

- R's complement and (R-1)'s complement

The (R-1)'s Complement

Subtract each digit of a number from (R-1)

Example

- 9's complement of 83510 is 16410

- 1's complement of 10102 is 01012(bit by bit complement operation)

The R's Complement

Add 1 to the low-order digit of its (R-1)'s complement

Example

- 10's complement of 83510 is 16410 + 1 = 16510

- 2's complement of 10102 is 01012 + 1 = 01102

FIXED POINT REPRESENTATION

Binary Fixed-Point Representation

X = xnxn-1xn-2 ... x1x0. x-1x-2 ... x-m

Sign Bit(xn): 0 for positive - 1 for negative

Remaining Bits(xn-1xn-2 ... x1x0. x-1x-2 ... x-m)

Numbers: Fixed Point Numbers and Floating Point Numbers

SIGNED NUMBERS

Signed magnitude representation

Signed 1's complement representation

Signed 2's complement representation


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Example: Represent +9 and -9 in 7 bit-binary number

Only one way to represent +9 ==> 0 001001

Three different ways to represent -9:

In signed-magnitude: 1 001001

In signed-1's complement: 1 110110

In signed-2's complement: 1 110111

In general, in computers, fixed point numbers are represented

either integer part only or fractional part only.

Need to be able to represent both positive and negative numbers

CHARACTERISTICS OF 3 DIFFERENT REPRESENTATIONS

Complement

Signed magnitude: Complement only the sign bit

Signed 1's complement: Complement all the bits including sign bit

Signed 2's complement: Take the 2's complement of the number,

Maximum and Minimum Representable Numbers and Representation of Zero

X = xn xn-1 ... x0 . x-1 ... x-m

Signed Magnitude

Max: 2n - 2-m 011 ... 11.11 ... 1

Min: -(2n - 2-m) 111 ... 11.11 ... 1

Zero: +0 000 ... 00.00 ... 0

-0 100 ... 00.00 ... 0

Signed 1s Complement


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Max: 2n - 2-m 011 ... 11.11 ... 1

Min: -(2n - 2-m) 100 ... 00.00 ... 0

Zero: +0 000 ... 00.00 ... 0

-0 111 ... 11.11 ... 1

signed 2s Complement

Max: 2n - 2-m 011 ... 11.11 ... 1

Min: -2n 100 ... 00.00 ... 0

Zero: 0 000 ... 00.00 ... 0

2s COMPLEMENT REPRESENTATION WEIGHTS

Signed 2s complement representation follows a weight scheme similar to that ofunsigned numbers

Sign bit has negative weight Other bits have regular weights

X = xn xn-1 ... x0

V(X) = - xn 2n + xi 2ii = 0n-1 V(X) = - xn 2n + xi 2ii = 0n-1


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ERROR DETECTING CODES

Simplest is the Parity System

Simplest method for error detection

- One parity bit attached to the information

- Even Parity and Odd Parity

Even Parity

- One bit is attached to the information so that

the total number of 1 bits is an even number

1011001 0

1010010 1

Odd Parity

One bit is attached to the information so that the total number of 1 bits is an odd number

OTHER DECIMAL CODESDecimal BCD(8421) 2421 84-2-1 Excess-3

0 0000 0000 0000 0011

1 0001 0001 0111 0100

2 0010 0010 0110 01013 0011 0011 0101 0110

4 0100 0100 0100 0111

5 0101 1011 1011 1000

6 0110 1100 1010 1001

7 0111 1101 1001 1010

8 1000 1110 1000 1011

9 1001 1111 1111 1100 d3 d2 d1 d0: symbol in the codes

BCD: d3 x 8 + d2 x 4 + d1 x 2 + d0 x 1

8421 code.2421: d3 x 2 + d2 x 4 + d1 x 2 + d0 x 1

84-2-1: d3 x 8 + d2 x 4 + d1 x (-2) + d0 x (-1)

Excess-3: BCD + 3

Note: 8,4,2,-2,1,-1 in this table is the weightassociated with each bit position.

BCD: It is difficult to obtain the 9's complement.However, it is easily obtained with the other codes listed above.

Self-complementing codes

External Representations


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SUBJECT:

YEAR/SEMESTER:

BRANCH:


UNIT2

REGISTER TRANSFER LANGUAGE

Combinational and sequential circuits can be used to create simple digital systems.

These are the low-level building blocks of a digital computer. Simple digital systems are frequently characterized in terms of

the registers they contain, and the operations that they perform.

Typically, What operations are performed on the data in the registers What information is passed between registers

MICROOPERATIONS (1)

The operations executed on data stored in registers are called microoperations. Examples of microoperations

Shift Load Clear Increment Count

MICROOPERATION (2)

An elementary operation performed (during one clock pulse), on the information stored in one

or more registers.

R f(R, R)

f: shift, load, clear, increment, add, subtract, complement,


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and, or, xor,

INTERNAL HARDWAREORGANIZATION OF A DIGITAL SYSTEM

- Set of registers it contains and their function

- The sequence of microoperations performed on the binary information stored in the registers

- Control signals that initiate the sequence of

microoperations (to perform the functions)

Definition of the internal hardware organization of a computer

REGISTER TRANSFER LANGUAGE

The symbolic notation used to describe the microoperation transfers among registers iscalled a

Register transfer language.

Register transfer language A symbolic language A convenient tool for describing the internal organization of digital computers Can also be used to facilitate the design process of digital systems.

ALU(f)

Registers(R)

ALU(f)

Registers(R)


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Often we want the transfer to occur only under a predetermined control condition.

if (p=1) then (R2 R1)

where p is a control signal generated in the control section.

In digital systems, this is often done via a control signal, called a control function

If the signal is 1, the action takes place

This is represented as:

P: R2 R1

Which means if P = 1, then load the contents of register R1 into register R2, i.e., if (P = 1)

then

(R2 R1)

Register Transfer

Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13,IR).

Often the names indicate function: MAR - memory address register PC - program counter IR - instruction register

Often we want the transfer to occur only under a predetermined control condition.

if (p=1) then (R2 R1)

where p is a control signal generated in the control section.

R1

Register R

Numbering of bits

Showing individual bits

Subfields (Divided into two parts)

PC(H) PC(L)

15 8 7 0

Block diagram of a register

7 6 5 4 3 2 1 0

R2

15 0


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In digital systems, this is often done via a control signal, called a control function If the signal is 1, the action takes place

This is represented as:

P: R2 R1

Which means if P = 1, then load the contents of register R1 into register R2, i.e., if (P = 1)then

(R2 R1)

SIMULTANEOUS OPERATIONS

If two or more operations are to occur simultaneously, they are separated with commas

P: R3 R5, MAR IR

Here, if the control function P = 1, load the contents of R5 into R3, and at the same time(clock),

load the contents of register IR into register MAR

BUS AND MEMORY TRANSFERS

HARDWARE IMPLEMENTATION OF CONTROLLED

TRANSFERSImplementation of controlled transfer

P: R2 R1

Block diagram

Timing diagram

Clock

Transfer occurs here

R2

R1

ControlCircuit

LoadP

n

Clock

Load

t t+1

The same clock controls the circuits that generate the control function

and the destination register Registers are assumed to use positive-edge-triggered flip-flops


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Bus is a path(of a group of wires) over which information is transferred, from any of several

sources to any of several destinations.

From a register to bus BUS R

Bus and Memory Transfers

BUS TRANSFER IN RTL

Depending on whether the bus is to be mentioned explicitly or not, register transfer canbe indicated.

In the former case the bus is implicit, but in the latter, it is explicitly indicated

R2 R1

BUS R1, R2 BUS

MEMORY (RAM)

Memory (RAM) can be thought as a sequential circuits containing some number of registers

These registers hold the words of memory Each of the r registers is indicated by an address These addresses range from 0 to r-1

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

Register A Register B Register C Register D

B C D1 1 1

4 x1MUX

B C D2 2 2

4 x1MUX

B C D3 3 3

4 x1MUX

B C D4 4 4

4 x1MUX

4-line bus

x

yselect

0 0 0 0

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4


B C D1 1 1

4 x1MUX

B C D2 2 2

4 x1MUX

B C D3 3 3

4 x1MUX

B C D4 4 4

4 x1MUX

4-line bus

x

yselect

0 0 0 0


Bus lines


Bus lines


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Each register (word) can hold n bits of data Assume the RAM contains r = 2k words. It needs the following

n data input lines n data output lines k address lines

A Read control line A Write control line

MEMORY TRANSFER

Collectively, the memory is viewed at the register level as a device, M. Since it contains multiple locations, we must specify which address in memory we will

be using This is done by indexing memory references Memory is usually accessed in computer systems by putting the desired address in a

special register, the Memory Address Register (MAR, or AR)

When memory is accessed, the contents of the MAR get sent to the memory unitsaddress lines

M

MEMORY READ

data input lines

data output lines

n

n

k

address lines

Read

Write

RAMunit

data input lines

data output lines

n

n

k

address lines

Read

Write

RAMunit

ARMemory

unit

Read

Write

Data inData out

ARMemory

unit

Read

Write

Data inData out


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To read a value from a location in memory and load it into a register, the register transferlanguage

notation looks like this:

This causes the following to occur The contents of the MAR get sent to the memory address lines A Read (= 1) gets sent to the memory unit The contents of the specified address are put on the memorys output data lines These get sent over the bus to be loaded into register R1

R1 M[MAR]

MEMORY WRITE

To write a value from a register to a location in memory looks like this in register transferlanguage:

This causes the following to occur The contents of the MAR get sent to the memory address lines A Write (= 1) gets sent to the memory unit The values in register R1 get sent over the bus to the data input lines of the

memory The values get loaded into the specified address in the memory

ARITHMETIC MICROOPERATIONS

Computer system microoperations are of four types:

1. Register transfer microoperations transfer binary information from one register to another

2. Arithmetic microoperationsperform arithmetic operations on numeric data stored in registers.

3. Logic microoperationsperform bit manipulation operations on non numeric data stored in

registers.

4. Shift microoperationsperform shift operations on data stored in registers.

Table: Arithmetic Micro-Operations

R3 R1 + R2 Contents of R1 plus R2 transferred to R3

R3 R1 - R2 Contents of R1 minus R2 transferred to R3

R2 R2 Complement the contents of R2


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R2 R2+ 1 2's complement the contents of R2 (negate)

R3 R1 + R2+ 1 subtraction

R1 R1 + 1 Increment

R1 R1 - 1 Decrement

The basic arithmetic microoperations are

Addition Subtraction Increment Decrement

The additional arithmetic microoperations are Add with carry Subtract with borrow

Transfer/Load etc.

BINARY ADDER / SUBTRACTOR / INCREMENTER

Binary Adder-Subtractor

Binary

Incrementer

FA

B0 A0

S0

C0FA

B1 A1

S1

C1FA

B2 A2

S2

C2FA

B3 A3

S3

C3

C4

FA

B0 A0

S0

C0C1FA

B1 A1

S1

C2FA

B2 A2

S2

C3FA

B3 A3

S3C4

M


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Binary Adder

LOGIC MICROOPERATIONS

It specifies binary operations on the strings of bits stored in registers Logic microoperations are bit-wise operations, i.e., they work on the individual

bits of data useful for bit manipulations on binary data useful for making logical decisions based on the bit value

There are, in principle, 16 different logic functions that can be defined over two binaryinput variables

However, most systems only implement four of these

AND (), OR (), XOR (), Complement/NOT

The others can be created from combination of these

LIST OF LOGIC MICROOPERATIONS

0 0 0 0 F0 = 0 F 0 Clear

HA

x y

C S

A0 1

S0

HA

x y

C S

A1

S1

HA

x y

C S

A2

S2

HA

x y

C S

A3

S3C4

0 0 0 0 0 1 1 10 1 0 0 0 1 1 11 0 0 0 1 0 1 11 1 0 1 0 1 0 1

A B F0 F1 F2 F13 F14 F15

0 0 0 0 0 1 1 10 1 0 0 0 1 1 11 0 0 0 1 0 1 11 1 0 1 0 1 0 1

A B F0 F1 F2 F13 F14 F15


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0 0 0 1 F1 = xy F A B AND

0 0 1 0 F2 = xy' F A B

0 0 1 1 F3 = x F A Transfer A

0 1 0 0 F4 = x'y F A B

0 1 0 1 F5 = y F B Transfer B

0 1 1 0 F6 = x y F A B Exclusive-OR

0 1 1 1 F7 = x + y F A B OR

1 0 0 0 F8 = (x + y)' F A B) NOR

1 0 0 1 F9 = (x y)' F (A B) Exclusive-NOR

1 0 1 0 F10 = y' F B Complement B

HARDWARE IMPLEMENTATION OF LOGIC MICROOPERATIONS

0 0 F = A B AND

0 1 F = AB OR

1 0 F = A B XOR

1 1 F = A Complement

APPLICATIONS OF LOGIC MICROOPERATIONS

Logic microoperations can be used to manipulate individual bits or a portions of a word in aregisterConsider the data in a register A. In another register, B, is bit data that will be used to

modify the contents of A

Selective-set A A + B Selective-complement A A B Selective-clear A A B Mask (Delete) A A B Clear A A B Insert A (A B) + C Compare A A B


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SELECTIVE SET

In a selective set operation, the bit pattern in B is used to set certain bits in A1 1 0 0 At

1 0 1 0 B

1 1 1 0 At+1 (A A + B)

If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keepsits previous

value

SELECTIVE COMPLEMENT

In a selective complement operation, the bit pattern in B is used to complement certainbits in A1 1 0 0 At

1 0 1 0 B

0 1 1 0 At+1 (A A B)

If a bit in B is set to 1, that same position in A gets complemented from its original value,otherwise

it is unchanged

SELECTIVE CLEAR

In a selective clear operation, the bit pattern in B is used to clear certain bits in A1 1 0 0 At

1 0 1 0 B

0 1 0 0 At+1 (A A B)

If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged

MASK OPERATION

In a mask operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 At


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1 0 1 0 B

1 0 0 0 At+1 (A A B)

If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged

CLEAR OPERATION

In a clear operation, if the bits in the same position in A and B are the same, they arecleared in A,

otherwise they are set in A

1 1 0 0 At

1 0 1 0 B

0 1 1 0 At+1 (A A B)

INSERT OPERATION

An insert operation is used to introduce a specific bit pattern into A register, leaving theother bit

positions unchanged

This is done as A mask operation to clear the desired bit positions, followed by An OR operation to introduce the new bits into the desired positions

Example Suppose you wanted to introduce 1010 into the low order four bits of A: 1101 1000 1011 0001 A (Original) 1101 1000 1011 1010 A (Desired)

1101 1000 1011 0001 A (Original)1111 1111 1111 0000 Mask

1101 1000 1011 0000 A (Intermediate)

0000 0000 0000 1010 Added bits

1101 1000 1011 1010 A (Desired)


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SHIFT MICROOPERATIONS

Shift microoperations are used for serial transfer of data. The information transferred through the serial input determines the type of shift. There

are threetypes of shifts

Logical shift Circular shift Arithmetic shift

LOGICAL SHIFT

In a logical shift the serial input to the shift is a 0. A right logical shift operation: A left logical shift operation: In a Register Transfer Language, the following notation is used

shl for a logical shift left shr for a logical shift right Examples:

R2 shr R2 R3 shl R3

CIRCULAR SHIFT

In a circular shift the serial input is the bit that is shifted out of the other end of theregister.

A right circular shift operation: A left circular shift operation: In a RTL, the following notation is used

cil for a circular shift left cir for a circular shift right Examples:

R2 cir R2

00

00


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R3 cil R3

ARITHMETIC SHIFT

An arithmetic shift is meant for signed binary numbers (integer) An arithmetic left shift multiplies a signed numberby two An arithmetic right shift divides a signed numberby two The main distinction of an arithmetic shift is that it must keep the sign of the number the

same as it

performs the multiplication or division

A left arithmetic shift operation:

00

ARITHMETIC SHIFT

An left arithmetic shift operation must

checked for the overflow

VBefore the shift, ifbits differ, the shi

overflow

In a RTL, the following notation is use ashl for an arithmetic shift left ashr for an arithmetic shift right

Examples: R2 ashr R2

R3 ashl R3

signbit


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AR

ITHMETIC LOGIC SHIFT UNIT

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F = A Transfer A

0 0 0 0 1 F = A + 1 Increment A

0 0 0 1 0 F = A + B Addition

0 0 0 1 1 F = A + B + 1 Add with carry

INSTRUCTION CODES

Every different processor type has its own design (different registers, buses,

microoperations,

machine instructions, etc)

Modern processor is a very complex device

It containMany registers

Multiple arithmetic units, for both integer and floating point calculations

The ability to pipeline several consecutive instructions to speed execution

ARITHMETIC LOGIC SHIFT UNIT

S3 S2 S1 S0 Cin Operation Function0 0 0 0 0 F = A Transfer A0 0 0 0 1 F = A + 1 Increment A0 0 0 1 0 F = A + B Addition0 0 0 1 1 F = A + B + 1 Add with carry0 0 1 0 0 F = A + B Subtract with borrow0 0 1 0 1 F = A + B+ 1 Subtraction0 0 1 1 0 F = A - 1 Decrement A0 0 1 1 1 F = A TransferA0 1 0 0 X F = A B AND0 1 0 1 X F = A B OR0 1 1 0 X F = A B XOR0 1 1 1 X F = A Complement A1 0 X X X F = shr A Shift right A into F1 1 X X X F = shl A Shift left A into F

ArithmeticCircuit

LogicCircuit

C

C 4 x 1MUX

Select

0123

F

S3S2S1S0

BA

i

A

D

A

E

shrshl

i+1 i

ii

i+1i-1

i

i


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However, to understand how processors work, we will start with a simplified processor

model This is similar to what real processors were like ~25 years ago

M. Morris Mano introduces a simple processor model he calls theBasic Computer

We will use this to introduce processor organization and the relationship of the RTL model tothe higher level computer processor

INSTRUCTION CYCLE

In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory

2. Decode the instruction

3. Read the effective address from memory if the instruction has an indirect address

4. Execute the instruction

After an instruction is executed, the cycle starts again at step 1, for the next instruction

Note: Every different processor has its own (different) instruction cycle

COMPUTER INSTRUCTIONS

Instructions

Basic Computer Instruction Format

15 14 12 11 0

I Opcode Address

Memory-Reference Instructions (OP-code = 000 ~ 110)

Register-Reference Instructions (OP-code = 111, I = 0)

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0

Register operation0 1 1 1

15 12 11 0

I/O operation1 1 1 1


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FETCH and DECODE

Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)T1: IR M [AR], PC PC + 1 (S0S1S2=111, T1=1)T2: D0, . . . , D7 Decode IR(12-14), AR IR(0-11), I IR(15)

S2

S1

S0

Bus

7Memory

unitAddress

Read

AR

LD

PC

INR

IR

LD Clock

1

2

5

Common bus

T1

T0

Instruction Cycle

INPUT-OUTPUT AND INTERRUPT

Input-Output Configuration

INPR Input register - 8 bitsOUTR Output register - 8 bitsFGI Input flag - 1 bitFGO Output flag - 1 bitIEN Interrupt enable - 1 bit

- The terminal sends and receives serial information- The serial info. from the keyboard is shifted into INPR- The serial info. for the printer is stored in the OUTR- INPR and OUTR communicate with the terminal

serially and with the AC in parallel.- The flags are needed to synchronize the timing

difference between I/O device and the computer

A Terminal with a keyboard and a Printer

I/O and Interrupt

Input-outputterminal

Serialcommunication

interface

Computerregisters andflip-flops

Printer

Keyboard

Receiverinterface

Transmitterinterface

FGOOUTR

AC

INPR FGI

Serial Communications Path

Parallel Communications Path


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ARITHMETIC LOGIC SHIFT UNIT

S3 S2 S1 S0 Cin Operation Function

0 0 0 0 0 F = A Transfer A

0 0 0 0 1 F = A + 1 Increment A

0 0 0 1 0 F = A + B Addition

0 0 0 1 1 F = A + B + 1 Add with carry

0 0 1 0 0 F = A + B Subtract with borrow

0 0 1 0 1 F = A + B+ 1 Subtraction

0 0 1 1 0 F = A - 1 Decrement A

1 0 X X X F = shr A Shift right A into F

1 1 X X X F = shl A Shift left A into F

MEMORY REFERENCE INSTRUCTIONS

AND to AC

D0T4: DR M[AR] Read operandD0T5: AC AC DR, SC 0 AND with AC

ADD to AC

D1T4: DR M[AR] Read operandD1T5: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E

- The effective address of the instruction is in AR and was placed there duringtiming signal T2 when I = 0, or during timing signal T3 when I = 1

- Memory cycle is assumed to be short enough to complete in a CPU cycle- The execution of MR instruction starts with T4

MR Instructions

SymbolOperationDecoder

Symbolic Description

AND D0 AC AC M[AR]ADD D1 AC AC + M[AR], E CoutLDA D2 AC M[AR]STA D3 M[AR] ACBUN D4 PC ARBSA D5 M[AR] PC, PC AR + 1ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1


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AND to AC

D0T4: DR M[AR] Read operandD0T5: AC AC DR, SC 0 AND with AC

ADD to AC

D1T4: DR M[AR] Read operandD1T5: AC AC + DR, E Cout, SC 0 Add to AC and store carry in E

- The effective address of the instruction is in AR and was placed there duringtiming signal T2 when I = 0, or during timing signal T3 when I = 1

- Memory cycle is assumed to be short enough to complete in a CPU cycle- The execution of MR instruction starts with T4

MR Instructions

SymbolOperationDecoder

Symbolic Description

AND D0 AC AC M[AR]ADD D1 AC AC + M[AR], E CoutLDA D2 AC M[AR]STA D3 M[AR] ACBUN D4 PC ARBSA D5 M[AR] PC, PC AR + 1ISZ D6 M[AR] M[AR] + 1, if M[AR] + 1 = 0 then PC PC+1


Memory, PC after execution

21

0 BSA 135

Next instruction

Subroutine

20

PC = 21

AR = 135

136

1 BUN 135

Memory, PC, AR at time T4

0 BSA 135

Next instruction

Subroutine

20

21

135

PC = 136

1 BUN 135

Memory Memory

LDA: Load to ACD2T4: DR M[AR]D2T5: AC DR, SC 0

STA: Store ACD3T4: M[AR] AC, SC 0

BUN: Branch Unconditionally

D4T4: PC AR, SC 0BSA: Branch and Save Return Address

M[AR] PC, PC AR + 1


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MEMORY REFERENCE

INSTRUCTIONS

MR Instructions

BSA:D5T4: M[AR] PC, AR AR + 1D5T5: PC AR, SC 0

ISZ: Increment and Skip-if-ZeroD6T4: DR M[AR]D6T5: DR DR + 1D6T4: M[AR] DR, if (DR = 0) then (PC PC + 1), SC 0

OWCHART FOR MEMORY REFERENCE INSTRUCTIO

MR Instructions

Memory-reference instruction

DR M[AR] DR M[AR] DR M[AR] M[AR] ACSC 0

AND ADD LDA STA

AC AC DRSC 0

AC AC + DRE CoutSC 0

AC DRSC 0

D T0 4

D T1 4 D T2 4 D T3 4

D T0 5 D T1 5 D T2 5

PC ARSC 0

M[AR] PCAR AR + 1

DR M[AR]

BUN BSA ISZ

D T4 4 D T5 4 D T6 4

DR DR + 1D T5 5 D T6 5

PC ARSC 0

M[AR] DRIf (DR = 0)then (PC PC + 1)SC 0

D T6 6


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STACK ORGANIZATON

INPUT-OUTPUT AND INTERRUPT

Input-Output Configuration

INPR Input register - 8 bits

OUTR Output register - 8 bitsFGI Input flag - 1 bitFGO Output flag - 1 bitIEN Interrupt enable - 1 bit

- The terminal sends and receives serial information- The serial info. from the keyboard is shifted into INPR- The serial info. for the printer is stored in the OUTR- INPR and OUTR communicate with the terminal

serially and with the AC in parallel.- The flags are needed to synchronize the timing

difference between I/O device and the computer

A Terminal with a keyboard and a Printer

I/O and Interrupt

Input-output

terminal

Serial

communicationinterface

Computer

registers andflip-flops

Printer

Keyboard

Receiverinterface

Transmitterinterface

FGOOUTR

AC

INPR FGI

Serial Communications Path

Parallel Communications Path

PROGRAM CONTROLLED DATA TRANSFER

loop: If FGI = 1 goto loop

INPR new data, FGI 1loop: If FGO = 1 goto loop

consume OUTR, FGO 1

-- CPU -- -- I/O Device --

/* Input */ /* Initially FGI = 0 */loop: If FGI = 0 goto loop

AC INPR, FGI 0/* Output */ /* Initially FGO = 1 */

loop: If FGO = 0 goto loop

OUTR AC, FGO 0

I/O and Interrupt

Start Input

FGI 0

FGI=0

AC INPR

MoreCharacter

END

Start Output

FGO 0

FGO=0

MoreCharacter

END

OUTR AC

AC Datayes

no

yes

no

FGI=0 FGO=1

yes

yesno

no


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INSTRUCTION FORMATS

A computer instruction is often divided into two parts An opcode (Operation Code) that specifies

the operation for that instruction An address that specifies the registers and/or locations in

memory to use for that operationIn the Basic Computer, since the memory contains 4096 (= 212)

words, we needs 12 bit to specify which memory address this instruction will use In the BasicComputer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1:

indirect addressing)Since the memory words, and hence the instructions, are 16 bits long, that

leaves 3 bits for the instructions opcode

The address field of an instruction can represent either Direct address: the address in memory of

the data to use (the address of the operand), or Indirect address: the address in memory of the

address in memory of the data to use

ADDRESSING MODES

The address field of an instruction can represent either Direct address: the address in memory of

the data to use (the address of the operand), orIndirect address: the address in memory of the

address in memory of the data to use

Effective Address (EA):The address, that can be directly used without modification to access an

operand for a computation-type instruction, or as the target address for a branch-type instruction


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Effective Address (EA)

The address, that can be directly used without modification to access an operand for a

computation-type instruction, or as the target address for a branch-type instruction

DATA TRANSFER AND MANIPULATION

When collecting data locally, institutions can customize their collection and delivery systems to

produce the precise formats and data structure necessary for their needs. This section therefore

focuses on vendor-provided statistics only. Of the vendors that do provide usage data, some offer

the option to receive/review the data in HTML, TXT, XLS, CSV, or even XML (currently rare).

This diversity is not bad in itself. The problem is lodged in the fact that not every vendor

provides all of the same options. In order to deposit all e-resource usage data into a single

location (be it a spreadsheet or database), vendor-provided data must be manipulated to varying

degrees. Different delivery formats (HTML, CSV, etc.) must be normalized through uniqueprocessing protocols for each format. The data must be cleaned to liminate extraneous

presentation elements (like report titles, footnotes or blank lines). T

The raw data itself may need to be further aggregated, disaggregated, or transposed to normalize

content increments that may be inconsistent with those of the repository (e.g. data provided in

daily or weekly increments may need to be aggregated to monthly totals prior to deposit). In

0 AD

45

2

Operand45

1 AD

30

3

135

30

Operand135

+

A

+

A

Direct Indirect


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many cases the raw data is not sufficiently meaningful and local categories must be assigned to

columns/groups of data to ensure that the data gets into the right place in the repository. It is

clear that some sort of XML-based data transfer protocol standard would facilitate faster and

more meaningful data transfer and integration, which would in turn enable easier local repository

design.

RISC(REDUCED INSTRUCTION SET COMPUTERS)

Reduced instruction set computing, orRISC (pronounced/rsk/), is a CPU design strategybased on the insight that simplified (as opposed to complex) instructions can provide higher

performance if this simplicity enables much faster execution of each instruction. A computer

based on this strategy is a reduced instruction set computer (also RISC). There are many

proposals for precise definitions, but the term is slowly being replaced by the more descriptive

load-store architecture. Well known RISC families include, and SPARC.Some aspects

attributed to the first RISC-labeleddesigns around 1975 include the observations that the

memory-restricted compilers of the time were often unable to take advantageof features intendedto facilitate manualassembly coding, and that complex addressing modes take many cycles to

perform due to the required additional memory accesses.

It was argued that such functions would be better performed by sequences of simpler instructions

if this could yield implementations small enough to leave room for many registers, reducing the

number of slow memory accesses. In these simple designs, most instructions are of uniform

length and similar structure, arithmetic operations are restricted to CPU registers and onlyseparate loadandstore instructions access memory. These properties enable a better balancing of

pipeline stages than before, making RISC pipelines significantly more efficient and allowing

Typical characteristics of RISC

For any given level of general performance, a RISC chip will typically have far fewertransistors

dedicated

to the core logic which originally allowed designers to increase the size of the register set and

increase internal parallelism.

Other features, which are typically found in RISC architectures are:

Uniform instruction format, using a single word with the opcode in the same bit positions in

every instruction, demanding less decoding; Identical general purpose registers, allowing any register to be used in any context,

simplifying compiler design (although normally there are separate floating point registers); Simple addressing modes. Complex addressing performed via sequences of arithmetic and/or

load-store operations;
http://en.wikipedia.org/wiki/Wikipedia:IPA_for_Englishhttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_Englishhttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_Englishhttp://en.wikipedia.org/wiki/CPU_designhttp://en.wikipedia.org/wiki/SPARChttp://en.wikipedia.org/wiki/Compilerhttp://en.wikipedia.org/wiki/Addressing_modehttp://en.wikipedia.org/wiki/Instruction_pipelinehttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/General_purpose_registershttp://en.wikipedia.org/wiki/Floating_pointhttp://en.wikipedia.org/wiki/Addressing_modehttp://en.wikipedia.org/wiki/Addressing_modehttp://en.wikipedia.org/wiki/Floating_pointhttp://en.wikipedia.org/wiki/General_purpose_registershttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Instruction_pipelinehttp://en.wikipedia.org/wiki/Addressing_modehttp://en.wikipedia.org/wiki/Compilerhttp://en.wikipedia.org/wiki/SPARChttp://en.wikipedia.org/wiki/CPU_designhttp://en.wikipedia.org/wiki/Wikipedia:IPA_for_English


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Fe data types in hardware, some CISCs have byte string instructions, or support complexnumbers; this is so far unlikely to be found on a RISC.Exceptions abound, of course, within

both CISC and RISC.RISC designs are also more likely to feature a Harvard memory model,where the instruction stream and the data stream are conceptually separated; this means that

modifying the memory where code is held might not have any effect on the instructions

executed by the processor (because the CPU has a separate instruction and data cache), atleast until a special synchronization instruction is issued. On the upside, this allows both

caches to be accessed simultaneously, which can often improve performanceMany early

RISC designs also shared the characteristic of having a branch delay slot. A branch delay slot is an instruction space immediately following a jump or branch. The

instruction in this space is executed,whether or not the branch is taken (in other words the

effect of the branch is delayed).

This instruction keeps the ALU of the CPU busy for the extra time normally needed to perform a

branch. Nowadays the branch delay slot is considered an unfortunate side effect of a particular

strategy for implementing some RISC designs, and modern RISC designs generally do away

with it .
http://en.wikipedia.org/wiki/Bytehttp://en.wikipedia.org/wiki/String_(computer_science)http://en.wikipedia.org/wiki/Complex_numberhttp://en.wikipedia.org/wiki/Complex_numberhttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/Branch_delay_slothttp://en.wikipedia.org/wiki/Arithmetic_and_logical_unithttp://en.wikipedia.org/wiki/Arithmetic_and_logical_unithttp://en.wikipedia.org/wiki/Branch_delay_slothttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/Complex_numberhttp://en.wikipedia.org/wiki/Complex_numberhttp://en.wikipedia.org/wiki/String_(computer_science)http://en.wikipedia.org/wiki/Byte


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SUBJECT:

YEAR/SEMESTER:

BRANCH:

NAME OF THE FACULTY:UNIT3

MICROPROGRAMMED CONTROL

Control Memory

Microprogram

Program stored in memory that generates all the control signals required to execute the

instruction set Correctly. Consists of microinstructions.it Contains a control word and a

sequencing word Control Word - All the control information required for one clock cycle

Sequencing Word - Information needed to decide the next microinstruction address

- Vocabulary to write a microprogram

Control Memory(Control Storage: CS) Storage in the microprogrammed control unit to store the

microprogramWriteable Control Memory(Writeable Control Storage:WCS) CS whose contents

can be modified, Allows the microprogram can be changed, Instruction set can be changed or

modified

ADDRESS SEQUENSING

Sequencer (Microprogram Sequencer)

A Microprogram Control Unit that determines the Microinstruction Address to be executed n

the next clock cycle


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CONDITIONAL BRANCHING

Unconditional BranchFixing the value of one status bit at the input of the multiplexer to 1

Conditional Branch

IfCondition is true, then Branch (address fromthe next address field of the current microinstruction)else Fall Through

Conditions to Test: O(overflow), N(negative),Z(zero), C(carry), etc.

Control address register

Control memoryMUX

Load address

Increment

Status(condition)

bits

Micro-operationsCondition select

Next address

...

CONDITIONAL BRANCHING

Unconditional Branch

Fixing the value of one status bit at the input of the multiplexer to 1

Conditional Branch

IfCondition is true, thenBranch (address from

the next address field of the current microinstruction)

elseFall Through

Conditions to Test: O(overflow), N(negative),

Z(zero), C(carry), etc.

MICROPROGRAM EXAMPLE

Computer Configuration

MUX

AR

10 0

PC

10 0

Address Memory

2048 x 16

MUX

DR15 0

Arithmeticlogic andshift unit

AC

15 0

SBR

6 0

CAR

6 0

Control memory128 x 20

Control unit


50/87



COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Implementation of Control Unit

Control Unit Implementation

Combinational Logic Circuits (Hard-wired)

Microprogram

I R Status F/Fs

Control Data

CombinationalLogic Circuits

ControlPoints

CPU

Memory

Timing State

Ins. Cycle State

Control Unit's State

Status F/Fs

Control Data

Next AddressGenerationLogic

CSAR

ControlStorage

(-programmemory)

Memory

I R

CSDR

CPs

CPUD

}

MICROPROGRAMMED CONTROL

DESIGN OF CONTROL UNIT- DECODING ALU CONTROL INFORMATION -

microoperation fields

3 x 8 decoder

7 6 5 4 3 2 1 0

F1

3 x 8 decoder

7 6 5 4 3 2 1 0

F2

3 x 8 decoder

7 6 5 4 3 2 1 0

F3

Arithmeticlogic andshift unit

ANDADD

DRTAC

ACLoad

FromPC

FromDR(0-10)

Select 0 1

Multiplexers

ARLoad Clock

AC

DR

DRTAR

PCTAR


51/87



MICROINSTRUCTION FORMAT

- Control Information, Sequencing Information, Constant Information which is useful

when feeding into the system.

These information needs to be organized in some way for Efficient use of the microinstructionbits Fast decoding

Field Encoding

- Encoding the microinstruction bits

- Encoding slows down the execution speed

due to the decoding delay

- Encoding also reduces the flexibility due to

the decoding hardware

MACHINE INSTRUCTION FORMAT

Microinstruction Format

EA is the effective addressSymbol OP-code Description

ADD 0000 AC AC + M[EA]BRANCH 0001 if (AC < 0) then (PC EA)STORE 0010 M[EA] ACEXCHANGE 0011 AC M[EA], M[EA] AC

Machine instruction format

I Opcode

15 14 11 10

Address

0

Sample machine instructions

F1 F2 F3 CD BR AD

3 3 3 2 2 7

F1, F2, F3: Microoperation fields

CD: Condition for branching

BR: Branch field

AD: Address field

SYMBOLIC MICROINSTRUCTIONS


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Symbols are used in microinstructions as in assembly language A symbolic microprogram can be translated into its binary equivalent by a microprogramassembler.

Sample Format

five fields: label; micro-ops; CD; BR; AD

CD: one of {U, I, S, Z}, where U: Unconditional Branch

I: Indirect address bit

S: Sign of AC

Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

SYMBOLIC MICROPROGRAM - FETCH ROUTINE

During FETCH, Read an instruction from memory and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:ARPC

DR M[AR], PC PC + 1,AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0

SYMBOLIC MICROPROGRAM

Control Storage: 128 20-bit words The first 64 words: Routines for the 16 machine instructions The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines


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SYMBOLIC MICROPROGRAM

ORG 0NOPREADADD

ORG 4NOPNOPNOPARTPC

ORG 8NOPACTDRWRITE

ORG 12NOPREADACTDR, DRTACWRITE

ORG 64PCTARREAD, INCPCDRTARREADDRTAR

IUU

SUI

U

IUU

IUUU

UUUUU

CALLJMPJMP

JMPJMPCALLJMP

CALLJMPJMP

CALLJMPJMPJMP

JMPJMPMAPJMPRET

INDRCTNEXTFETCH

OVERFETCHINDRCTFETCH

INDRCTNEXTFETCH

INDRCTNEXTNEXTFETCH

NEXTNEXT

NEXT

ADD:

BRANCH:

OVER:

STORE:

EXCHANGE:

FETCH:

INDRCT:

Label Microops CD BR AD

Partial Symbolic Microprogram

This microprogram can be implemented using ROM

Address Binary Microinstruction

Micro Routine Decimal Binary F1 F2 F3 CD BR AD

ADD 0 0000000 000 000 000 01 01 1000011

1 0000001 000 100 000 00 00 0000010

2 0000010 001 000 000 00 00 1000000

3 0000011 000 000 000 00 00 1000000

BRANCH 4 0000100 000 000 000 10 00 0000110

5 0000101 000 000 000 00 00 1000000

6 0000110 000 000 000 01 01 1000011

7 0000111 000 000 110 00 00 1000000

STORE 8 0001000 000 000 000 01 01 1000011

9 0001001 000 101 000 00 00 0001010

10 0001010 111 000 000 00 00 1000000

11 0001011 000 000 000 00 00 1000000

EXCHANGE 12 0001100 000 000 000 01 01 1000011

13 0001101 001 000 000 00 00 000111014 0001110 1 00 1 01 0 00 0 0 00 0001111

15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 0 00 1 00 1 01 0 0 00 1000010

66 1000010 101 000 000 00 11 0000000

INDRCT 67 1000011 000 100 000 00 00 1000100

68 1000100 101 000 000 00 10 0000000

BINARY MICROPROGRAM


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COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Implementation of Control Unit

Control Unit Implementation

Combinational Logic Circuits (Hard-wired)

Microprogram

I R Status F/Fs

Control Data

CombinationalLogic Circuits

ControlPoints

CPU

Memory

Timing State

Ins. Cycle State

Control Unit's State

Status F/Fs

Control Data

Next AddressGenerationLogic

CSAR

ControlStorage

(-programmemory)

Memory

I R

CSDR

CPs

CPUD

}

NANOSTORAGE AND NANOINSTRUCTION

The decoder circuits in a vertical microprogram storage organization can be replaced by a ROM

=> Two levels of control storage First level - Control Storage

Second level -Nano Storage

Two-level microprogram First level Vertical format Microprogram Second level

-Horizontal format Nanoprogram , Interprets the microinstruction fields, thus converts

a vertical microinstruction format into a horizontal nanoinstruction format.


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TWO-LEVEL MICROPROGRAMMING - EXAMPLE

Microprogram: 2048 microinstructions of 200 bits each With 1-Level Control Storage: 2048 x

200 = 409,600 bits Assumption:256 distinct microinstructions among 2048

* With 2-Level Control Storage:

Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions

Control storage: 2048 x 8 bits

To address 256 nano storage locations 8 bits are needed

* Total 1-Level control storage: 409,600 bits

Total 2-Level control storage: 67,584 bits (256 x 200 + 2048 x 8)


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SUBJECT:

YEAR/SEMESTER:

BRANCH:


UNIT -V

THE MEMORY SYSTEM

Basic concepts semiconductor RAM memories

A semiconductor random access memory system for use in a processor system is adapted to

operate with a magnetic disc storage device, such as the so-called floppy-disc store. A

semiconductor RAM has data input/output terminals and address terminals for writing data into

or reading data out of a storage location that is addressed by an address signal supplied to theaddress terminals. Track and sector address registers are coupled to the processor system for

receiving and storing the typical track and sector address signals normally generated in thesystem. A counter counts timing pulses to produce a count signal, which timing pulses are

generated by a timing control circuit. An address synthesizer is coupled to the track and sector

address registers and also to the counter for synthesizing a RAM address signal from the storedtrack and sector address signals as well as the count signal and for supplying this RAM address

signal to the RAM address terminals to access the RAM storage location which is addressed

thereby.

Thus, when the processor system generates the typical track and sector address signals normally

used with a floppy disc store, such track and sector address signals are used to address a typical

semiconductor RAM.

Random-access memory (RAM) is a form ofcomputer data storage. Today, it takes the form ofintegrated circuits that allow stored data to be accessed in any order (that is, at random).

"Random" refers to the idea that any piece of data can be returned in a constant time, regardless

of its physical location and whether it is related to the previous piece of data.

The word "RAM" is often associated with volatile types of memory (such as DRAM memory

modules), where the information is lost after the power is switched off. Many other types of

memory are RAM as well, including most types ofROM and a type offlash memory called

NOR-Flash.

Types of RAM
http://en.wikipedia.org/wiki/Computer_data_storagehttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Datahttp://en.wikipedia.org/wiki/Random_accesshttp://en.wikipedia.org/wiki/Constant_timehttp://en.wikipedia.org/wiki/Volatile_memoryhttp://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/DIMMhttp://en.wikipedia.org/wiki/DIMMhttp://en.wikipedia.org/wiki/Read_only_memoryhttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Flash_memory#NOR_flashhttp://en.wikipedia.org/wiki/Flash_memory#NOR_flashhttp://en.wikipedia.org/wiki/Flash_memory#NOR_flashhttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Read_only_memoryhttp://en.wikipedia.org/wiki/DIMMhttp://en.wikipedia.org/wiki/DIMMhttp://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/Volatile_memoryhttp://en.wikipedia.org/wiki/Constant_timehttp://en.wikipedia.org/wiki/Random_accesshttp://en.wikipedia.org/wiki/Datahttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Computer_data_storage


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Top L-R, DDR2 with heat-spreader, DDR2 without heat-spreader, Laptop DDR2, DDR, Laptop

DDR

1 Megabit chip - one of the last models developed by VEB Carl Zeiss Jena in 1989

Modern types ofwritable RAM generally store a bit of data in either the state of a flip-flop, as inSRAM (static RAM), or as a charge in a capacitor(ortransistorgate), as in DRAM (dynamicRAM), EPROM, EEPROM and Flash. Some types have circuitry to detect and/or correct random

faults called memory errors in the stored data, using parity bits orerror correction codes. RAM

of the read-only type, ROM, instead uses a metal mask to permanently enable/disable selectedtransistors, instead of storing a charge in them. Of special consideration is SIMM and DIMM

memory modules.

Memory hierarchy

Many computer systems have a memory hierarchy consisting ofCPU registers, on-die SRAM

caches, external caches, DRAM, paging systems, and virtual memory orswap space on a hard

drive. This entire pool of memory may be referred to as "RAM" by many developers, even

though the various subsystems can have very different access times, violating the originalconcept behind the random access term in RAM. Even within a hierarchy level such as DRAM,

the specific row, column, bank, rank, channel, orinterleave organization of the components

make the access time variable, although not to the extent that rotating storage media or a tape is

variable.
http://en.wikipedia.org/wiki/DDR2_SDRAMhttp://en.wikipedia.org/wiki/Carl_Zeiss_AGhttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Static_random_access_memoryhttp://en.wikipedia.org/wiki/Electric_chargehttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Dynamic_random_access_memoryhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/EEPROMhttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/Parity_bithttp://en.wikipedia.org/wiki/Error_detection_and_correctionhttp://en.wikipedia.org/wiki/Read_only_memoryhttp://en.wikipedia.org/wiki/CPU_registerhttp://en.wikipedia.org/wiki/Static_random_access_memoryhttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/Paginghttp://en.wikipedia.org/wiki/Virtual_memoryhttp://en.wikipedia.org/wiki/Swap_spacehttp://en.wikipedia.org/wiki/Access_timehttp://en.wikipedia.org/wiki/Memory_rankhttp://en.wikipedia.org/wiki/Interleavehttp://en.wikipedia.org/wiki/Storage_mediahttp://en.wikipedia.org/wiki/File:Bundesarchiv_Bild_183-1989-0406-022,_VEB_Carl_Zeiss_Jena,_1-Megabit-Chip.jpghttp://en.wikipedia.org/wiki/File:RamTypes.JPGhttp://en.wikipedia.org/wiki/File:RamTypes.JPGhttp://en.wikipedia.org/wiki/File:Bundesarchiv_Bild_183-1989-0406-022,_VEB_Carl_Zeiss_Jena,_1-Megabit-Chip.jpghttp://en.wikipedia.org/wiki/File:RamTypes.JPGhttp://en.wikipedia.org/wiki/File:RamTypes.JPGhttp://en.wikipedia.org/wiki/File:Bundesarchiv_Bild_183-1989-0406-022,_VEB_Carl_Zeiss_Jena,_1-Megabit-Chip.jpghttp://en.wikipedia.org/wiki/File:RamTypes.JPGhttp://en.wikipedia.org/wiki/File:RamTypes.JPGhttp://en.wikipedia.org/wiki/Storage_mediahttp://en.wikipedia.org/wiki/Interleavehttp://en.wikipedia.org/wiki/Memory_rankhttp://en.wikipedia.org/wiki/Access_timehttp://en.wikipedia.org/wiki/Swap_spacehttp://en.wikipedia.org/wiki/Virtual_memoryhttp://en.wikipedia.org/wiki/Paginghttp://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/Cachehttp://en.wikipedia.org/wiki/Static_random_access_memoryhttp://en.wikipedia.org/wiki/CPU_registerhttp://en.wikipedia.org/wiki/Read_only_memoryhttp://en.wikipedia.org/wiki/Error_detection_and_correctionhttp://en.wikipedia.org/wiki/Parity_bithttp://en.wikipedia.org/wiki/Flash_memoryhttp://en.wikipedia.org/wiki/EEPROMhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/Dynamic_random_access_memoryhttp://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Capacitorhttp://en.wikipedia.org/wiki/Electric_chargehttp://en.wikipedia.org/wiki/Static_random_access_memoryhttp://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Carl_Zeiss_AGhttp://en.wikipedia.org/wiki/DDR2_SDRAM


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Swapping

If a computer becomes low on RAM during intensive application cycles, many CPUarchitectures and operating systems are able to perform an operation known as "swapping".

Swapping uses apaging file, an area on a hard drive temporarily used as additional working

memory. Excessive use of this mechanism is called thrashing and is generally undesirablebecause it lowers overall system performance, mainly because hard drives are far slower than

RAM. However, if a program attempts to allocate memory and fails, it may crash.

Other uses of the "RAM" term

Other physical devices with readwrite capability can have "RAM" in their names: for example,

DVD-RAM. "Random access" is also the name of an indexing method: hence, disk storage is

often called "random access" (Wiki:PowerOfPlainText, Fortran language features, MBASIC,

RAM disks:Software can "partition" a portion of a computer's RAM, allowing it to act as amuch faster hard drive that is called a RAM disk. A RAM disk loses the stored data when thecomputer is shut down, unless memory is arranged to have a standby battery source.

Shadow RAM

Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allowfor shorter access times. The ROM chip is then disabled while the initialized memory locations

are switched in on the same block of addresses (often write-protected). This process, sometimes

calledshadowing, is fairly common in both computers and embedded systems.

As a common example, the BIOS in typical personal computers often has an option called useshadow

BIOS or similar. When enabled, functions relying on data from the BIOSs ROM will instead

use DRAM locations (most can also toggle shadowing of video card ROM or other ROM

sections). Depending on the system, this may not result in increased performance, and may causeincompatibilities. For example, some hardware may be inaccessible to the operating system if

shadow RAM is used. On

some systems the benefit may be hypothetical because the BIOS is not used after booting infavor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs

READ ONLY MEMORIES

Read-only memory (ROM) is a class ofstorage media used in computers and other electronicdevices. Data stored in ROM cannot be modified, or can be modified only slowly or withdifficulty, so it is mainly used to distribute firmware (software that is very closely tied to specific

hardware, and unlikely to need frequent updates).
http://en.wikipedia.org/wiki/Paginghttp://en.wikipedia.org/wiki/Hard_drivehttp://en.wikipedia.org/wiki/Thrashing_(computer_science)http://en.wikipedia.org/wiki/DVD-RAMhttp://c2.com/cgi/wiki?PowerOfPlainTexthttp://en.wikipedia.org/wiki/Fortran_language_features#Direct-access_fileshttp://en.wikipedia.org/wiki/MBASIC#Files_and_input.2Foutputhttp://en.wikipedia.org/wiki/RAM_diskhttp://en.wikipedia.org/wiki/Embedded_systemshttp://en.wikipedia.org/wiki/BIOShttp://en.wikipedia.org/wiki/Operating_systemhttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Firmwarehttp://en.wikipedia.org/wiki/Softwarehttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Computer_hardwarehttp://en.wikipedia.org/wiki/Softwarehttp://en.wikipedia.org/wiki/Firmwarehttp://en.wikipedia.org/wiki/Computerhttp://en.wikipedia.org/wiki/Computer_storagehttp://en.wikipedia.org/wiki/Operating_systemhttp://en.wikipedia.org/wiki/BIOShttp://en.wikipedia.org/wiki/Embedded_systemshttp://en.wikipedia.org/wiki/RAM_diskhttp://en.wikipedia.org/wiki/MBASIC#Files_and_input.2Foutputhttp://en.wikipedia.org/wiki/Fortran_language_features#Direct-access_fileshttp://c2.com/cgi/wiki?PowerOfPlainTexthttp://en.wikipedia.org/wiki/DVD-RAMhttp://en.wikipedia.org/wiki/Thrashing_(computer_science)http://en.wikipedia.org/wiki/Hard_drivehttp://en.wikipedia.org/wiki/Paging


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In its strictest sense, ROM refers only to mask ROM (the oldest type ofsolid state ROM), which

is fabricated with the desired data permanently stored in it, and thus can never be modified.

However, more modern types such as EPROM and flash EEPROM can be erased and re-programmed multiple times.

Types

The firstEPROM, anIntel1702, with thedieandwire bondsclearly visible through the erase

window.

Semiconductor based:Classic mask-programmed ROM chips are integrated circuits that

physically encode the data to be stored, and thus it is impossible to change their contents after

fabrication. Other types ofnon-volatile solid-state memory permit some degree of modification:

Programmable read-only memory(PROM), orone-time programmable ROM

(OTP), can be written to orprogrammed via a special device called a PROM

programmer.

Erasable programmable read-only memory(EPROM) can be erased by exposure to

strongultravioletlight (typically for 10 minutes or longer), then rewritten with a process

that again needs higher than usual voltage applied. Repeated exposure to UV light willeventually wear out an EPROM).

Electrically alterable read-only memory(EAROM) is a type of EEPROM that can be

modified onebitat a time. Writing is a very slow process and again needs higher voltage
http://en.wikipedia.org/wiki/Mask_ROMhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/Flash_EEPROMhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/Wire_bondhttp://en.wikipedia.org/wiki/Wire_bondhttp://en.wikipedia.org/wiki/Wire_bondhttp://en.wikipedia.org/wiki/Non-volatilehttp://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Erasable_programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Erasable_programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Ultraviolethttp://en.wikipedia.org/wiki/Ultraviolethttp://en.wikipedia.org/wiki/Ultraviolethttp://en.wikipedia.org/wiki/Electrically_alterable_read-only_memoryhttp://en.wikipedia.org/wiki/Electrically_alterable_read-only_memoryhttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/File:Eprom.jpghttp://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Electrically_alterable_read-only_memoryhttp://en.wikipedia.org/wiki/Ultraviolethttp://en.wikipedia.org/wiki/Erasable_programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Non-volatilehttp://en.wikipedia.org/wiki/Wire_bondhttp://en.wikipedia.org/wiki/Die_(integrated_circuit)http://en.wikipedia.org/wiki/Intelhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/Flash_EEPROMhttp://en.wikipedia.org/wiki/EPROMhttp://en.wikipedia.org/wiki/Semiconductor_fabricationhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Mask_ROM


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(usually around 12V) than is used for read access. EAROMs are intended for applications that

require infrequent and only partial rewriting.

Flash memory(or simply flash) is a modern type of EEPROM invented in 1984. Flash

memory can be erased and rewritten faster than ordinary EEPROM,Optical storage

media, suchCD-ROMwhich is read-only (analogous to masked ROM).CD-RisWrite

Once Read Many(analogous to PROM), whileCD-RWsupports erase-rewrite cycles

(analogous to EEPROM); both are designed forbackwards-compatibility with CD-ROM.

CACHE MEMORIES

In computer engineering, a cache is a component that transparently stores data so that future

requests for that data can be served faster. The data that is stored within a cache might be values

that ha

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