demonstrations of designes for -...

21.12.2015

1

Computer System Structures

cz:Struktury počítačových systémů

Lecturer: Richard Šusta [email protected], [email protected],

+420 2 2435 7359

ČVUT-FEL in Prague, CR – subject A0B35SPS

Version: 1.0

Demonstrations of designes for

4bit register

mailto:[email protected]

mailto:[email protected]

21.12.2015

2

SPS 3

a) without detection of an edge of the clock

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity reg4a is

port (clock : in std_logic;

data : in std_logic_vector(3 downto 0);

q4 : out std_logic_vector(3 downto 0));

end;

architecture rtl of reg4a is

begin process(data)

begin

q4 <= data;

end process;

end rtl;

q4[3..0] data[3..0]

clock (GND)

If we do not detect any edge of the clock,

the result is a wire.

SPS 4

a) without detection edge of the clock - synchronous part

…

process(data)

begin

q4 <= data;

end process;

…

q4[3..0] data[3..0]

clock (GND)

Without detections of edges of the clock,

we obtain just a wire.

Process-Header with sensitivity list

Process-DataFlow part

On the following slides, there will only synchronous parts of

processes - full codes are on hidden slides

q4 depends on data, thus, data are in "sensitivity list"

21.12.2015

3

SPS 5

b) Detection of the edge of the clock -

synchronous část

process(clock)

begin

if rising_edge(clock) then

q4 <= data;

end if;

end process; D Q

clock

data[3..0]

q4[3..0]

q4[3..0]~reg0

In synchronous part of process

"if rising_edge(clock) then …"

final values of assignments are

implemented by registers.

Process-Synchronous part

Process-Clock test


q4 is changed only on the rising edge of the clocks, thus, clock only is in sensitivity list

SPS 6

b) Full code: detection edge of the clock

library IEEE;


entity reg4b is




end;

architecture rtl of reg4b is

begin process(clock)

begin


q4 <= data;

end if; end process;

end rtl;

D Q

clock

data[3..0]

q4[3..0]

q4[3..0]~reg0

4bit synchronous register

samples data inputs on

rising edges of the clock and

store them into q4 outputs.

21.12.2015

4

SPS 7

c) detection of the edge of the clock - synchronous part

process(clock)

begin


q4 <= "0000";

q4 <= data;

end if;

end process;

D Q

clock

data[3..0]

q4[3..0]

q4[3..0]~reg0

In synchronous part of processes

("if rising_edge(clock) then …")

final values of assignments are



Process-Clock test


q4 is changed only on rising edges of the clock, thus, clock only is in "sensitivity list"

SPS 8

c) Full code: Detection of the edge of the clock

library IEEE;


entity reg4c is




end;

architecture rtl of reg4c is


begin


q4 <= "0000"; q4 <= data;


end rtl;

D Q

clock

data[3..0]

q4[3..0]

q4[3..0]~reg0

4bit synchronous register

samples data inputs on

rising edges of the clock and

store them into q4 outputs.

The first <= assignment is

ignored, it is without any

effect to q4.

21.12.2015

5

SPS 9

d) Wrong dependency of 2 clocks

process(clock)

begin


q4 <= data;

elsif falling_edge(clock) then

q4 <= not data;

end if;

end if;

end process;

Our FPGA does not contain flip-

flops sensitive to to clocks

- its synthesis is impossible here.

Error: Netlist error at reg4.vhd(13):

can't infer register for q4[0]

because it changes value on both

rising and falling edges of the clock

Error: HDL error at reg4.vhd(13):

couldn't implement registers for

assignments on this clock edge

SPS 10

d) Full code: Wrong dependency of 2 clocks

library IEEE;


entity reg4d is

port (clock: in std_logic;



end;

architecture rtl of reg4d is


begin


q4 <= data;

elsif falling_edge(clock) then

q4 <= not data;

end if;

end if;

end process;

end rtl;

Our FPGA does not contain flip-

flops sensitive to to clocks

- its synthesis is impossible here.

Error: Netlist error at reg4.vhd(13):

can't infer register for q4[0]

because it changes value on both

rising and falling edges of the clock

Error: HDL error at reg4.vhd(13):

couldn't implement registers for

assignments on this clock edge

21.12.2015

6

SPS 11

e) We asynchronous clear (aclrn)

process(clock, aclrn) begin if aclrn = ‘0' then q4 <=“0000”; elsif rising_edge(clock) then

q4 <= data;

end if; end if; end process;

Signal q4 is changes either with aclrn or on rising edges of the clock.

The both signals must be in "sensitivity list".

D Q

CLR

aclrn

data[3..0] q4[3..0]

q4[3..0]~reg0

clock


Process-Asynchronous

inputs

Process-Clock test


SPS 12

e) Full code: We add asynchronous clear (aclrn)

library IEEE; use IEEE.STD_LOGIC_1164.all; entity reg4 is port (clock, aclrn : in std_logic; data : in std_logic_vector(3 downto 0); q4 : out std_logic_vector(3 downto 0)); end reg4; architecture rtl of reg4 is begin process(clock, aclrn) begin if aclrn = ‘0' then q4 <=“0000”; elsif rising_edge(clock) then q4 <= data; end if; end if; end process; end rtl;

D Q

PRE

ENA

CLR

aclrn

data[3..0]

q4[3..0]

q4[3..0]~reg0

clock

Signal q4 is changes either

with aclrn or on rising edges

of the clock. The both signals

must be in "sensitivity list". sí

v "sensitivity list".

21.12.2015

7

SPS 13

D Q

PRE

ENA

CLR

q4[3]

q4[3..0]~reg0aclrn

q4[3..0]

apren

clockdata[3..0]

f) Unrecommended 2 asynchronous inputs (1/2)

port (clock,

aclrn, apren : in std_logic; …

*******

begin process(clock, aclrn, apren)

begin if apren = '0' then q4 <= "1111";

elsif aclrn = '0' then q4 <= "0000";

elsif rising_edge(clock) then

q4 <= data;

end if;

end process;

Never use two

asynchronous inputs on

Cyclone FPGA.

Ocyclone FPGA has only

flip-flops with one

asynchronous input.

SPS 14

f) Warnings

Warning (13004): Presettable and clearable registers converted to equivalent

circuits with latches. Registers power-up to an undefined state, and

DEVCLRn places the registers in an undefined state.

Warning (13310): Register "q4[0]~reg0" is converted into an equivalent

circuit using register "q4[0]~reg0_emulated" and latch "q4[0]~1"







Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational

loops as latches.

Warning (335093): TimeQuest Timing Analyzer is analyzing 1 combinational

loops as latches.

21.12.2015

8

SPS 15

f) 2 asynchronous input implementation

CLK

D

CLK

Q

CLRN

1

1 bit register 0

Q

1

0 MUX21

Data

APREN

ACLRN

RS latch

RS latch

is not recommended

on FPGA Cyclone

SPS 16

g) Wrong asynchronous input

library IEEE;


entity reg4g is

port (clock, aclrn : in std_logic;



end;

architecture rtl of reg4g is

begin process(clock, aclrn)

begin


q4 <= data;

elsif aclrn = ‘0' then q4 <=“0000”;

end if;

end if;

end process;

end rtl;

Asynchronous input (here aclrn)

must have the highest priority

i.e. it must appear before the

detection of an edge of the clock

- otherwise it is always

non-synthesizable sable

Error (10818): Can't infer register

for "q4[3..0]" at reg4g.vhd(14)

because it does not hold its value

outside the clock edge

Error (10822): HDL error at

reg4g.vhd(14): couldn't implement

registers for assignments on this

clock edge

21.12.2015

9

SPS 17

h) Wrong second output


begin


q4 <= data;

q4n <= not data; end if;

end process;

D Q

PRE

ENA

CLR

D Q

PRE

ENA

CLR

q4[3..0]~reg0

q4n[3..0]~reg0

clock

data[3..0]

q4[3..0]

q4n[3..0]

SPS 18

h) Wrong second output

library IEEE;


entity reg4h is



q4 : out std_logic_vector(3 downto 0);

q4n : out std_logic_vector(3 downto 0));

end;

architecture rtl of reg4h is


begin


q4 <= data;

q4n <= not data; end if;

end process;

end rtl; D Q

PRE

ENA

CLR

D Q

PRE

ENA

CLR

q4[3..0]~reg0

q4n[3..0]~reg0

clock

data[3..0]

q4[3..0]

q4n[3..0]

In synchronous part, final

values of assignments are


21.12.2015

10

SPS 19

i) Assignment <= versus :=

process(clock)

variable qv :

std_logic_vector(q4'range);

begin


qv := data;

q4<= qv;

q4n <= not qv; end if;

end process;

end rtl;

Only final values of assignments have effect.

Process-Clock test


Process-

Declarations


D Q

PRE

ENA

CLR

D Q

PRE

ENA

CLR

q4[3..0]~reg0

q4n[3..0]~reg0

clock

data[3..0]

q4[3..0]

q4n[3..0]

SPS 20

D Q

PRE

ENA

CLR

D Q

PRE

ENA

CLR

D Q

PRE

ENA

CLR

q4[3..0]~reg0

q4n[3..0]~reg0qv[3..0]

clockdata[3..0]

q4[3..0]

q4n[3..0]

j) Assignment <= versus :=

architecture rtl of reg4j is

signal qv : std_logic_vector(q4'range);

begin

process(clock)

begin


qv <= data;

q4 <= qv;


end process;

Assignment <= are performed with delta delay,

thus, the result is a shift register.

Process-Clock test



Architecture-Declarations

21.12.2015

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SPS 21

j) Full code: Assignment <= versus :=

library IEEE;


entity reg4j is



q4, q4n : out std_logic_vector(3 downto 0));

end;

architecture rtl of reg4j is

signal qv : std_logic_vector(q4'range);


begin if rising_edge(clock) then

qv <= data;

q4<= qv;


end process;

end rtl;

D Q

PRE

ENA

CLR

D Q

PRE

ENA

CLR

D Q

PRE

ENA

CLR

q4[3..0]~reg0

q4n[3..0]~reg0qv[3..0]

clockdata[3..0]

q4[3..0]

q4n[3..0]

SPS 22

k) Correct second output

process(clock)

variable qv : std_logic_vector(q4'range);

begin


qv := data; end if;

q4<= qv; q4n <= not qv;

end process;

Concurrent assignments <=

are compiled by registers in

synchronous part, outside by

logic.

D Q

q4[3..0]~reg0

clock

data[3..0]

q4[3..0]

q4n[3..0]


Process-DataFlow part

Process-Clock test


21.12.2015

12

SPS 23

k) Full code: Correct second output

library IEEE;


entity reg4k is



q4, q4n : out std_logic_vector(3 downto 0));

end;

architecture rtl of reg4k is


begin


qv := data; end if;

q4<= qv; q4n <= not qv; end process;

end rtl;

D Q

q4[3..0]~reg0

clock

data[3..0] q4[3..0]

q4n[3..0]

Concurrent assignments <=

are compiled by registers in

synchronous part, outside by

logic.

SPS 24

l) Inside outside of if rising_edge

process(clock) begin if rising_edge(clock) then q4(1 downto 0) <= data(1 downto 0); end if; q4(3 downto 2) <= data(3 downto 2); end process;

D Q

PRE

ENA

CLR

clock

data[3..0] q4[1..0]

q4[1..0]~reg0

q4[3..2]

2

2

4

q4[3..2]

21.12.2015

13

SPS 25

Full code: Inside outside of if rising_edge

library IEEE; use IEEE.STD_LOGIC_1164.all; entity reg4l is port (clock : in std_logic; data : in std_logic_vector(3 downto 0); q4 : out std_logic_vector(3 downto 0)); end; architecture rtl of reg4l is begin process(clock) begin if rising_edge(clock) then q4(1 downto 0) <= data(1 downto 0); end if; q4(3 downto 2) <= data(3 downto 2); end process; end rtl;

D Q

PRE

ENA

CLR

clock

data[3..0] q4[1..0]

q4[1..0]~reg0

q4[3..2]

2

2

4

q4[3..2]

Concurrent assignments <= are compiled by registers

in synchronous part, outside by logic.

SPS 26

2 synchronous inputs – clear + enable

port (clock, enable, sclrn : in std_logic;

*******


begin if rising_edge(clock) then

if enable = '1' then q4 <= data;

elsif sclrn = '0' then q4 <= "0000"; end if;


synchronous clear (sclrn) is in the next 'elsif' condition, the enable has higher priority

than sclrn.

enable

D Q PRE

ENA

CLR

SEL

DATAA

DATAB OUT0

MUX21

SEL

DATAA

DATAB OUT0

MUX21

4' h0 --

q4[3..0]~reg0

q4~[3..0] q4~[7..4]

clock

sclrn

data[3..0]

q4[3..0]

1st 2nd

21.12.2015

14

SPS 27

Synchronous clear priority

port (clock, enable, sclrn : in std_logic; ******* begin process(clock)

begin if rising_edge(clock) then if sclrn = '0' then q4 <= "0000"; elsif enable = '1' then q4 <= data;

end if; end if; end process;

synchronous clear

(sclrn) is before enable

in 'if-elsif' statement,

thus, it has higher

priority than enable

1st 2nd

D Q

PRE

ENA

CLR

SEL

DATAA

DATAB OUT0

MUX21

SEL

DATAA

DATAB OUT0

MUX21

4' h0 --

q4[3..0]~reg0

q4~[3..0] q4~[7..4]

clock

enable

sclrn

data[3..0] q4[3..0]

SPS 28

Asynchronous and synchronous inputs

port (clock, enable, sclrn, aclrn : in std_logic;

*******

begin process(clock, aclrn )

begin if aclrn= '0' then q4 <= "0000";

elsif rising_edge(clock) then

if sclrn = '0' then q4 <= "0000";

elsif enable = '1' then q4 <= data; end if;


D Q

PRE

CLR

SEL

DATAA

DATAB OUT0

MUX21

SEL

DATAA

DATAB OUT0

MUX21

q4~[3..0]

clock

enable

sclrn

aclrn

data[3..0] q4[3..0]

q4[3..0]~reg0

q4~[7..4]

4' h0 --

21.12.2015

15

Shift / delay

Shift register

SPS 30

Concurrent process

x1 x2 x4 x3

A. It can be emulated by parallel

computers

B. It is feature of circuits

21.12.2015

16

SPS 31

Task: Shift cells of array concurrent = performed

in the same time Computer system

Concurrent Sequential

VHDL "sequential assignments" for variable x : std_logic_vector(3 downto 0);

x(3):=x(2); x(2):=x(1); x(1):=x(0); -- sequantial statements - order is important

All by one statement: x:=x(2 downto 0) & '0';

x0 x1 x3 x2

start

x0 x1 x3 x2

VHDL

signal xs : std_logic_vector(3 downto 0);

xs <= xs(2 downto 0) & '0';

krok2-3

krok4-5

krok2

krok1

SPS 32

Shift Register

shift its content by each rising/falling edge of the clock

its effectivity does not depend on its length

SO SI

21.12.2015

17

SPS 33

library ieee; use ieee.std_logic_1164.all;

entity reg_width is

port( CLK : in std_logic;

SI : in std_logic;

SO : out std_logic );

end;

architecture rtl of shift is

begin

process (CLK)

variable qv:std_logic_vector( 3 downto 0 );

begin

if rising_edge(CLK) then

qv:=qv(2 downto 0) & SI;

end if;

SO<=qv(2);

end process;

end rtl;

Assign results to signals

Shift Register

Entity-Ports

Evaluate next values

Process-Clock test

Process-Declarations

Process-Header with sensitivity list Architecture.P

rocess

concurrent statement

Libraries

Modifications

of shift register

21.12.2015

18

SPS 35

Barrel shifter (1/3) with asynchronous Clear and synchronous Load

SLOAD

CLK

ACLRN

clear after power-up D[3]

Q[3]

D

CLK

Q

CLRN

1

1-bit register 0

MUX2

1

D

CLK

Q

CLRN

1

1-bit register 0

MUX2

1

D

CLK

Q

CLRN

1

1-bit register 0

MUX2

1

D

CLK

Q

CLRN

1

1-bit register 0

MUX2

1

D[2] D[1] D[0]

Q[2]

Q[1]

Q[0] 4bit version

Barrel shifter aka ring counter

SPS 36

Barrel shifter (2/3)

library ieee; use ieee.std_logic_1164.all;

entity reg_width is

generic( WIDTH:natural:=4 );

port( CLK, SLOAD, ACLRN : in std_logic;

D : in std_logic_vector(WIDTH-1 downto 0);

Q : out std_logic_vector(WIDTH-1 downto 0) );

end;

architecture rtl of reg_width is

constant ZERO : std_logic_vector(Q'range):=( others=>'0' );

begin

process (CLK, ACLRN)

-- see next page

end process;

end rtl;

Libraries

Entity-Ports

Architecture.

-Declarations

Entity-Generic

Process

concurrent

statement

21.12.2015

19

SPS 37

Barrel shifter (3/3)

with asynchronous Clear and synchronous Load


variable qv:std_logic_vector( WIDTH-1 downto 0 );

begin

if ACLRN='0' then qv:=ZERO;

elsif rising_edge(CLK) then

if SLOAD='0' then

qv:=qv(WIDTH-2 downto 0) & qv(WIDTH-1);

else qv:=D;

end if;

end if;

Q<=qv;

end process;

Evaluate

next

value

P-Asynchronous input

Process-Clock test

P-Declarations


Architecture.Process

concurrent statement

Assign results to signals

SPS 38

Shift registers have not left and right directions related to positions of each flip-flop on the

scheme, but left-right shift is related to weight of output bits:

•right directions is dividing a binary number by 2

•left direction is multiplication by 2.

Bidirectional shift register (1/3)

with asynchronous Clear

SLI

Clk

1

0

ACLRN

D

CLK

Q

CLRN

1

0

D

CLK

Q

CLRN

1

0

D

CLK

Q

CLRN

Right

SLO

SRI

qv[2] qv[1] qv[0]

SRO

21.12.2015

20

SPS 39

library ieee;

use ieee.std_logic_1164.all;

entity shift3BiDir is

port( CLK, ACLRN, SLI, SRI : in std_logic;

SLO, SRO: out std_logic );

end;


with asynchronous Clear

SPS 40


with asynchronous Clear architecture rtl of shift3BiDir is

begin



begin

if ACLRN='0' then qv:=(others=>'0');


if IsRight='0' then qv:=qv(1 downto 0) & SLI;

else qv:=SRI & qv(2 downto 1);

end if;

end if;

SLO<=qv(2); SRO<=qv(0);

end process; end rtl;

21.12.2015

21

SPS 41

Bidirectional shift register with synchronous preset

4 input multiplexer with connected inputs 10 and 11

acts as cascade of two 2-input multiplexers; higher

bit addresses SLOAD has a higher priority than

RIGHT.

SLI D

CLK

Q

CLRN

D

CLK

Q

CLRN

D

CLK

Q

CLRN

RIGHT

SLO

SRI

SLOAD

01

00

11

10

01

00

11

10

01

00

11

10

CLRN

D1 D2

DFF DFF DFF

SLO

CLK

D0

01

00

11

10

1

0

1

0

RIGHT SLOAD

SLOAD

RIGHT

SPS 42


with asynchronous Clear and synchronous Load library ieee; use ieee.std_logic_1164.all;

entity shift3BiDir is

port( CLK, Right, ACLRN : in std_logic;

SLOAD : in std_logic;

D : in std_logic_vector(2 donwto 0);

SLI, SRI : in std_logic;

SLO, SRO: out std_logic );

end;

architecture rtl of shift3BiDir is

begin


-- next page

end process; end rtl;

21.12.2015

22

SPS 43


with asynchronous Clear and synchronous Load process (CLK, ACLRN)


begin

if ACLRN='0' then qv:=(others=>'0');


if SLOAD='1' then qv:=D;

elsif Right='0' then qv:=qv(1 downto 0) & SLI;

else qv:=SRI & qv(2 downto 1);

end if;

end if;

SLO<=qv(2); SRO<=qv(0);

end process;

Some usage of

shift registers

21.12.2015

23

Usage of shift registers

time delay

fast Johnson counter

serialization of data

filtering of signal

pseudorandom generators

calculation error-detecting code by cyclic redundancy check (CRC)

SPS 46

Johnson counter - very fast

CLK

ACLRN

clear after power-up

Q[3]

D

CLK

Q

CLRN

1-bit register

D

CLK

Q

CLRN

1-bit register

D

CLK

Q

CLRN

1-bit register

D

CLK

Q

CLRN

1-bit register

Q[2] Q[1] Q[0]

4bit version 0000

0001

0011

0111

1111

1110

1100

1000

0000

Johnson counter aka Twisted ring counter

21.12.2015

24

Linear Feedback Shift Registers

psoudorandom generators

error detection CRC code

SPS 48

Linear Feedback Shift Register

7

6

5

4

3

2

1

0

Q[0]Q[1]Q[2] Step

Q(0 to 2) <= (Q(0) xor Q(2)) & Q(0 to 1);

Q[0] xor Q[2]

111

repeats

110

100

001

010

101

011

111

0

1

1

1

0

0

1

0

Many possible connections

F l o

p

F l o

p

F l o

p

Q[0] Q[1] Q[2]

CLK

D D D

21.12.2015

25

SPS 49

Linear Feedback Shift Register

7

6

5

4

3

2

1

0

Q[0]Q[1]Q[2] Step

Q(0 to 2) <= Q(2) & (Q(0) xor Q(2)) & Q(1);

Q[0] xor Q[2]

111

repeats

011

110

001

010

100

101

111

0

1

1

1

0

1

0

0

111

110

100

001

010

101

011

111

F l o

p

F l o

p

F l o

p

Q[0] Q[1] Q[2]

CLK

D D D

Serialization

parallel <-> series

21.12.2015

26

Serialization by shift registers

D Q

C CLR

0

D Q

C CLR

1

D Q

C CLR

2

D Q

C CLR

3

CLK

ACLR

DIN QD

D Q

C CLR

3

D Q

C CLR

2

D Q

C CLR

1

D Q

C CLR

0

CLK

ACLR

DIN

QA QB QC QD

D Q

C CLR

3

D Q

C CLR

2

D Q

C CLR

1

D Q

C CLR

0

CLK

ACLR

L/S

A B C D

I0 I1 I0 I1 I0 I1 I0 I1

QD

DIN

Serial-In, Serial-Out

Parallel-In, Serial-Out

Serial-In, Parallel-Out

SPS 52

Shift registers - CCD reading 1/3

[Image source: Digital Photography Review]

21.12.2015

27

SPS 53



SPS 54



21.12.2015

28

SPS 55

Analog video / Digital monitor

[Image: DVI specifications reference]

SPS 56

Analog video / Digital monitor

[Images: DVI specifications reference]

Screen Mode Pixel Rate (MHz) Serial Data

Rate (Mb/s)

VGA 640x480 @ 60 Hz 25 250

SVGA 800x600 @ 60 Hz 40 400

XGA 1024x768 @ 60 Hz 65 650

SXGA 1280x1024 @ 60 Hz 108 1080

pixel rate/clock [MHz]

Serial data rate [Mb/s]

21.12.2015

29

SPS 57

Single link DVI


SPS 58

DVI Encoding

DVI encoding switch order of bits in bytes,

in cases, when it reduced bit transitions, i.e. frequency

of transmitted signal

9 bit pattern, 4 transitions

Source: DVI specifications

21.12.2015

30

SPS 59

Dual Link DVI


SPS 60

DVI

ANALOG

DIGITAL

DVI-I / DVI-A DVI-D

DIGITAL

VGA

Compatibility Část DVI-I signálu je stejná jako VGA

GROUND SIGNAL

21.12.2015

31

SPS 61

DVI versus VGA

DVI-D

DVI-A <=> VGA

VGA/DVI-A CONVERTER

DVI-A

DVI-I p

ixels

are

se

nt a

s a

na

log

va

lue

s

SPS 62

DVI Versus HDMI

HDMI

Connector

HDMI

Connector

DVI

Connector

DVI

Connector

DVI is HDMI without sound

21.12.2015

32

SPS 63

DisplayPort VESA standard

Video

Audio

Řízení

Data

Video

Audio

Řízení

Data

Datový kanál 1

Datový kanál 2

Datový kanál 3

Datový kanál 4

Pomocný kanál

Hot Plug Detect

Přijímač Vysílač

DisplayPort zdroj DisplayPort přijímač

DisplayPort source can generate and DVI or HDMI signals, but the source

HDMI / DVI cannot be connected to DisplayPort receiver

- the receiver cannot convert.

navržen VESA (Video Electronics Standards Association)

Shift register as a filter

of glitches

21.12.2015

33

SPS

Debouncing

What is bouncing? When the contacts of any mechanical switch bang

together they rebound a bit before settling, causing bounce. .

VCC

0V

SPS

Swutch bouncing Oscillographic records of pulses generated

when pressing or releasing buttons and toggle switches.

[Source: L. Traylor: Computer Techniques, Oregon 2009]

21.12.2015

34

SPS

DE2 denounced KEY inputs

67

Debounce KEY[n]

VCC

0V

SW[n]

In contrast, the input SW [n] lack RC circuits, they are not

debounced and they may generate sequences of pulses when

closing / opening.

SPS

DE2 detailed schematic of KEY

68

Uc(t)

KEY[n]

0V

100KΩ

Budič

1 µF

VCC

uc(t)=VCC (1-e-t /τ),

τ=R.C=105.10-6=0,1s 0 τ 2τ 3τ

86,3% Vcc

95% Vcc

63,2% Vcc

press

button

ko

nd

en

zá

tor C

se

vyb

íjí pře

s

sko

ro n

ulo

vý

od

po

r tlačítk

a

release button

or power-up state

output of driver

at FPGA input KEY[n] true, ´1´

false, ´0´

uc(t)

t - čas

CMOS driver (74HC245) used in DE2 gives ´1´ on its

output when input has voltage from 40% to 60% og Vcc.

Denounced inputs KEY can drive clock inputs or asynchronous inputs of

flip-flops, but SW switches do not.

21.12.2015

35

SPS 69

Mapping of Physical World

When a button is pressed, it is usually asserted (true). However, its

physical construction may output this as a LOW VOLTAGE.

Button

Pressed

Released

Logic

value

1

0

Button

Pressed

Released

Logic

value

0

1

(a) Positive Logic (b) Negative Logic

There are two logic levels (T - True and F- False or '1' and '0') and two

voltage levels (H - High and L - Low) or button states (pressed, released).

The digital designer may choose either voltage level or state (but not both!)

to represent logic truth for each input or output;

For example, an H may represent '1' on input X1, but H can be '0' on

output Y, if it is required.

SPS 70

Simple Debouncing DE2 - KEY[3..0]

V CC

0V

Input

0V

100KΩ

1µF

+5 VDC

RC integrator as a debouncer and initiator...

74HC245

hysteresis

After DE2 board is switched on, KEY[3..0] will go to 1

with a delay of several milliseconds.

Q: How to replace KEY by SW?

A: Use them with debouncer from shift register.

P: We have only 4 KEY inputs and some of them are no longer reliable.

21.12.2015

36

Debounce SW inputs

suitable as clocks

Output changes on 2 matches of values

time

72

21.12.2015

37


time

73


time

74

21.12.2015

38


time

75


time

76

21.12.2015

39


time

77


time

78

21.12.2015

40


time

79


time

80

21.12.2015

41


time

81


time

82

21.12.2015

42


time

83


time

84

21.12.2015

43


time

85


time

86

21.12.2015

44

SPS 87

Filter of 2 same inputs

clk

Q0

QFilter

CLRN

D PRN

Q

DFF

inst CLRN

D PRN

Q

DFF

inst1

PRN

CLRN

D

ENA

Q

DFFE

inst2

VCC

VCC

NOT

inst7

XOR

inst4

VCC D INPUT

VCC CLK INPUT

Qfilter OUTPUT

not (a xor b)

equals to (a≡b)

SPS 88

Debounce.vhd

library ieee;use ieee.std_logic_1164.all;

entity debounce is

port (d, clk: in std_logic; qfilter: out std_logic );

end entity;

architecture rtl of debounce is

begin

process (clk)

variable memory : std_logic_vector(1 downto 0);

variable result : std_logic;

begin

if rising_edge(clk) then

memory := memory(0) & d;

if memory(1)=memory(0)

then result:=memory(1);

end if;

end if;

qfilter<=result;

end process;

end rtl;

Libraries

Entity-Ports

Process-Clock test



21.12.2015

45

89

Binary counters /

ffrequency dividers by 2N

N-bit binary counters from 0 až 2N-1-1

and frequency dividers by modulo 2N

SPS

4bit counter/divider - Carry/Borrow

0000 0001 1111

0010 1110

0011 1101

0100 1100

1000

0101 1011

0110 1010

0111 1001

0 1

2

3

4

5

6

7

15

11

14

13

12

8 9

10

Inside: Natural number Outside: 4-bit encoding

0

1 2

3

15

4

5 6

7 8 9

Turn x notches counterclockwise

to add x

Turn y notches clockwise

to subtract y

11

14

13

12

10

← borrow

carry →

90

Uvnitř dekadická čísla

Vně binární kódy

arithmetic carry or borrow is generated out

of the most significant number bit position

21.12.2015

46

SPS

Counter and dividers

Denote the frequency of the clock signal applied at the input CLK as

fclk

Use the main scale bit of the counter as an output signal. The bit has

logically just one change from '0' to '1' and only one of '1' to '0'. The

frequency of this signal is denoted as fout.

If the binary counter counts from 0 to M-1, where M is any integer

greater than one, then the counter also divides the input frequency by

M

91

fclk

M fout =

In the literature, therefore, the word divider (of frequency) is often

used as a synonym for the binary counter by 1, since the design is

practically identical and both circuits differ only by their usage.

SPS

With every rising edge of the clock, the counter loads into the

output of register value by 1 greater than the current output value.

Depending on our needs, we can use a simple register composed

of DFF circuits; if we also need to enable it, we use DFFE circuits,

we can possibly also add multiplexers add synchronous reset,

preset...

General schematic of synchronous counter up

92

D[n-1..0]

CLK

Q[n-1..0]

CLRN

Registr n-bitů

+1

+

n - bus with width of n-bits

n n-bitová

adder

´1´ nebo KEY[n]

21.12.2015

47

Adder

in hardware

93

SPS

Karnaugh maps for bits of adder

94

0 1

1 0

B

A 0 1

0

1

S0

0 0

0 1

1 1

0 1

1 0

1 1

1 0

0 0

B

00 01 11 10

00

01

11

10

A

They have too small groups of

bits, therefore, coverage of KM

has exponential complexity in

gates and interconnections.

S1

0 0

0 0

0 0

1 0

0 1

0 0

1 1

1 0

0 1

1 1

1 0

1 0

0 0

0 0

1 0

1 0

1 1

1 0

1 1

1 1

0 0

0 0

0 1

1 1

1 1

1 0

0 0

1 0

0 1

0 0

0 0

0 0

A 0 1 3 2 6 7 5 4 000 001 011 010 110 111 101 100

0 000

1 001

3 011

2 010

6 110

7 111

5 101

4 100

B

S2

A

B

S +

S=A+B

S bity [Sn-1…S2 S1 S0]

21.12.2015

48

Design of adder directly from KM by Sum-Of-Products

Bit n of sum Total operations

bit n of sum OR operations AND operations bit 0 až n

0 1 2 3 1 5 14 22 2 15 52 89 3 35 148 272 4 75 380 727 5 152 688 1567 6 320 1400 3287 7 768 3072 7127 9 2304 8192 17623

10 8194 27648 53465 11 16388 46080 115933

95 The calculation was performed by logic minimizer BOOM

developed by Dept. of Computers of CTU-FEE

Simplifying designes

by "Ripple" 96

21.12.2015

49

SPS

Ripple (1st meaning)

ripple from Middle English. repylle akin to Old High German riffila= saw

ripple a large instrument like a comb for removing seeds and other matter from flax or hemp

97

ripple

SPS 98

Ripple (2nd meaning)

ripple: become fretted or lightly ruffled on surface (as water), become covered with or form in small waves or undulations

Ripple Effect = Domino Effect / Chain Reaction

21.12.2015

50

Usage of ripple efect

Design of adder with ripple efect

99

SPS

Decomposition of adder

Simplest N-bit adder

we chain 1-bit full adders

"Carry" ripple through their chain

Minimal number of logical elements

Delay is given by the last Cout - 2*(N-1)+ 3 gates of the last

adder

= (2 N+1) times propagation delay of 1 gate

100

A31 B31

Cout31

S31

+

A30 B30

S30

+

A29 B29

S29

+

A1 B1

S1

+

A0 B0

S0

+ Cout1

Cin29=Cout28

Cin0

21.12.2015

51

SPS 101

Half adder without Carry-In

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

0 0 1 1

+ 0 + 1 + 0 + 1

0 1 1 10

Sum Carry Sum

Sum <= A xor B;

Carry <= A and B

Sum

Carry

SPS

Full 1bit adder

10

2

C B

+

S A

Cout

S S

C

A

B

S

C

A

B B

A

Cin

+ +

+ A

B S

C

+

Fuul adder is composed from

2 half adders, i.e. two adders without Cin

A 0 0 1 1 0 0 1 1

+B 0 1 0 1 0 1 0 1

Sum 00 01 01 10 00 01 01 10

+ Carry-In 0 0 0 0 1 1 1 1

CarryOut Sum 00 01 01 10 01 10 10 11

A B

Cin Cout

S

+

21.12.2015

52

SPS

Ripple example 2/3: Full adder

10

3

A

B

Cin

Half Adder

Half Adder

S=Cin xor A xor B

Cout

S S

C

A

B

S

C

A

B B

A

Cin

+ +

+

Cout=A.B+Cin.(A xor B)

SPS 104

A B

Cin Cout

S

S1

A1 B1

Adder

A B

Cin Cout

S

S0

A0 B0

A B

Cin Cout

S

S2

A2 B2

A B

Cin Cout

S

S3

A3 B3

Carry

+ + + +

1nit full adder

21.12.2015

53

SPS

32bit CLA "carry look-ahead" adder

The carry-lookahead adder calculates one or more carry bits

before the sum, which reduces the wait time to calculate the

result of the larger value bits

105

S3

+

S2

+

S1

+

A3 B3 A2 B2 A1 B1 A0 B0

S0

+ Cin0

A4 B4

S4

+ Cin4=Cout3

A5 B5

S5

+

Static "carry look ahead (CLA)" unit for 4 bits C

ou

t 2

Co

ut 1

Co

ut 0

Co

ut 3

Co

ut 1

Co

ut 0

SPS

4bit with CLA (carry look-ahead)

106

A3 B3 A2 B2 A1 B1 A0 B0 Cin0

S3 S2 S1 S0 Cout3

CLA adder - 36 gates / delay 6 hradel

Ripple adder - 20 gates / delay= 2*(4-1)+3 = 9 gates

obvod

SN74283

21.12.2015

54

Special case

adder+1

SPS

Karnaugh map of adder +1

108

1 0 A0 0 1 S0

The number of gates is given

by sum of arithmetic

progression, i.e. it has

complexity O(n2), where n is

the width of S in bits.

1

A

S +

0 1

1 0

A1

A0 0 1

0

1

S1

1 0 A0 0 1 S0

0 1

1 0

A1

A0 0 1

0

1

S1

1 0 A0 0 1 S0

0 0

1 1

1 0

0 1

00 01 11 10

0

1

A1 A0 S2

A2

1bit adder +1

2bit adder +1

3bi adder +1

S0=not A0 S1=A1 xor A0 S2=A2 xor (A1 and A0)

Equation: Si = Ai xor (Ai-1 and Ai-2 and … A1 and A0); i=0..n-1

21.12.2015

55

Divider by 2

Clock signal

D

CLK

Q

CLRN

'1'

1bit adder Output

Combinatorial

Logic

Output 109

SPS

Simple synchronous circuit

110

21.12.2015

56

Counter 0..1 / Divider by 2 with enable

Hodiny

D

CLK

Q

CLRN

'1'

1bit adder +0/+1 not necessary,

but better

Output

111

enable

Enable

Q xor 0 = Q

Q xor 1 = not Q

On enable=´0´, counter increments by 0, on enable=´1´, counter

inc]rements by +1.

Alternatively: We can use DFFE flip-flop

Counter 0..3 / divider 4

Clock

2bit adder+1

Output

112

Q0

Q1

00

10

01 11

D

CLK

Q

CLRN

D

CLK

Q

CLRN

VC

C

21.12.2015

57

SPS

Counter 0..15 / Divider by 16

Qi = Qi xor (Qi-1 and Qi-2 and … and Q0 and EN);

Q2:= Q2 xor (Q1 and Q0

and EN)

Q1:= Q1 xor (Q0 and EN)

Q0:= Q0 xor EN (EN-enable)

Q3:= Q3 xor (Q2 and Q1 and Q0

and EN)

113

SPS

Counter 0..15 / Divider 16 with iteration

Q0 = Q0 xor C0; C0=EN;

Qi = Qi xor Ci; Ci=Ci-1 and Qi-1;

114

ripple

effect

21.12.2015

58

Divider with 50% duty cycle

SPS 116

Counter modulo different from 2N

Counter modulo CONST_MODULO

if qv<(CONST_MODULO-1) -- eg. if qv<9 pro MOD 10

then qv:=qv+1;

else qv:=(others=>'0');

end if;

Never use

qv:=(qv+1) mod CONST_MODULO;

eg. qv:=(qv+1) mod 10;

Note: Operator MOD (reminder after division) consumes a lot of

logic elements when it is synthesized in circuits -> non-effective

designs

21.12.2015

59

SPS 117

50% duty cycle in divider by 1000 [C:1/3]

Entity Ports CLK : in std_logic; q : out std_logic;

Process Declarations

variable cnt : integer range 0 to 499:=0;

variable q2 : std_logic := '0';

Process Synchronous part

if cnt<499 then cnt:=cnt+1;

else cnt:=0; q2:=not q2;

end if;

Process Dataflow part

q<=q2;

13 LE (10 reg)

q

SPS 118


library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;

entity FreqDivBy1000 is

port(CLK : in std_logic; q : out std_logic);

end entity;

architecture behav of FreqDivBy1000 is

begin

process (CLK)

variable cnt : integer range 0 to 499:=0;


begin

if (CLK'event and CLK='1') then

if cnt<499 then cnt:=cnt+1;

else cnt:=0; q2:=not q2; end if;

end if;

q<=q2;

end process;

end behav;

Libraries

Entity-Ports

Next value

Assign result to signals

Process-Clock test



21.12.2015

60

SPS 119

+A[8..0]

B[8..0]

ADDER

D Q

PRE

ENA

CLR

<A[8..0]

B[8..0]

LESS_THAN

D

ENA

Q

PRE

CLR

SEL

DATAA

DATABOUT0

MUX21

9' h001 -- 9' h1F3 --

9' h000 --

Add0 cnt[8..0] LessThan0

q2cnt~[8..0]

CLK

q


binary

counter

comparator

< 499

synchro. clear

9bits clock

ENA

q

clock

Q D

SPS 120

A' B' C' D' + A' B C' D + A B C D + A B' C D' A' B' D + A' C B C' D' + A C' + A B D'

AB 00 01 11 10

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

00

01

11

10 C

CD

A

D

B

K-map for F 1

AB 00 01 11 10

0 0 0 0

1 0 0 0

1 1 0 1

1 1 0 0

00

01

11

10 C

CD

A

D

B

K-map for F 2

AB 00 01 11 10

0 1 1 1

0 0 1 1

0 0 0 0

0 0 1 0

00

01

11

10 C

CD

A

D

B

K-map for F 3

Remeber Two-Level Simplification

F1 =

F2 =

F3 =

F1 = F2' . F3'

Equality is expensive operation

21.12.2015

61

SPS 121

Style of code [D:1/5]

Process Synchronous part

origin: if cnt<499 then

cnt:=cnt+1;

else cnt:=0; q2:=not q2;

end if;

new: if cnt=499 then

cnt:=0; q2:=not q2;

else cnt:=cnt+1;

end if;

13 LE (10 reg)

18 LE (10 reg)

SPS 122

Process Declarations

origin: variable cnt : integer range 0 to 499:=0;

new: variable cnt : integer:=0;

new2: variable cnt : integer;

13 LE (10 reg)

44 LE (33 reg)

76 LE (33 reg)

Style of code [D:3/5]

21.12.2015

62

SPS 123

General even divider 1/2

library ieee;use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity FreqDivByEven is

generic( EVEN_DIV: integer := 1000 );

port(CLK : in std_logic;

q : out std_logic);

begin assert EVEN_DIV mod 2=0

report "FreqDivByEven requires EVEN divisor"

severity severity_level(error);

end entity;

to be continued (on the next slide)

Libraries

Entity-Ports

Entity-Generic

Entity-Passive process

SPS 124

General even divider 2/2

architecture behav of FreqDivByEven is

constant DIVISOR:integer := EVEN_DIV/2;

begin

process (CLK)

variable cnt : integer range 0 to DIVISOR-1:=0;


begin

if (CLK'event and CLK='1') then

if DIVISOR>1 and cnt<DIVISOR-1 then cnt:=cnt+1;

else cnt:=0; q2:=not q2; end if;

end if;

q<=q2;

end process;

end behav;

Architecture Declarations

Next values

Write results into signals

Process-Clock test



demonstrations of designes for -...

Documents