department of electronics and communication …aim: to study the pin configurations, specifications...

DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

LABORATORY MANUAL

FOR

IC APPLICATIONS

II B.Tech. II SEM

Department of Electronics and Communication Engineering

ANURAG COLLEGE OF ENGINEERING

(Approved by AICTE, New Delhi & Affiliated to JNTU-HYD)

AUSHAPUR (V), GHATKESAR (M), MEDCHAL-

MALKAJGIRI.DIST, T.S.501301

Department of ECE LINEAR IC APPLICATIONS LAB

Anurag college of engineering 2

ANURAG COLLEGE OF ENGINEERING

(Approved by AICTE, New Delhi & Affiliated to JNTU-HYD)

AUSHAPUR (V), GHATKESAR (M), Medchal-Malkajigiri.DIST, T.S.501301

EC407PC: IC APPLICATIONS LAB L T P C

0 0 3 1.5

B TECH II Year II Semester ECE

Note: Verify the functionality of the IC in the given application

Design and Implementation of:

1.Inverting and Non-Inverting Amplifiers using Op Amps

2.Adder and Subtractor using Op Amp.

3.Comparators using Op Amp.

4.Integrator Circuit using IC 741.

5.Differentiator Circuit using Op Amp.

6.Active filter Applications-LPF, HPF (First Order)

7.IC 741 waveform Generators-Sine, Square wave and Triangular Waves.

8.Mono-Stable Multivibrator using IC 555.

9.Astable multivibrator using IC 555.

10.Schmitt Trigger Circuits using IC 741.

11.IC 565-PLL Applications.

12.Voltage Regulator using IC 723

13.Three terminal voltage regulators-7805, 7809, 7912

Major Equipments required for Laboratories:

1)5 V Fixed Regulated Power Supply/ 0-5V or more Regulated Power Supply.

2.20 MHz Oscilloscope with Dual Channel.

3)Bread board and components/ Trainer Kit.

4)Multimeter.



STUDY OF OP-AMPS

AIM: To study the pin configurations, specifications & functioning of different integrated

circuits used in the practical applications.

APPARATUS REQUIRED:

a) IC µA 741 OP-Am

b) LM 311N Voltage Comparator

c) NE ISE 555/SE 555C

d) VCO IC 566

e) Phase Locked Loop NE/SE 565

f) IC 723 Voltage Regulator

g) Three Terminal Voltage Regulators

a) µA 741 OP-AMP

Pin configuration

Specifications

1. Supply voltage:

µA 741A, µA 741, µA 741E ---------------- ±22V

µA 741C ---------------- ±18 V

2. Internal power dissipation

DIP package ----------------- 310 mw.

3. Differential input voltage ---------------- ±30 V.

4. Operating temperature range

Military (µA 741A, µA 741) ---------------- -550 to +1250 C.

Commercial (µA 741E, µA 741C) --------------- 00 C to +700 C.

5. Input offset voltage ---------------- 1.0 mV.



6. Input Bias current ---------------- 80 nA.

7. PSSR ---------------- 30µV/V.

8. Input resistance ----------------- 2MΩ.

9. CMMR ------------------ 90dB.

10. Output resistance ------------------ 75Ω.

11. Bandwidth ------------------ 1.0 MHz.

12. Slew rate ------------------ 0.5 V/µ sec.

b) LM 311N VOLTAGE COMPARATOR

Pin configuration

Specifications

1. Total supply voltage ------------ 36 V

2. Input Voltage ------------ ±15V

3. Power dissipation ------------ 500mW

4. Operating temperature ------------ 00 C to 700C

5. Input offset voltage ------------- 2.0 mV

6. Input Bias current ------------ 100nA

7. Voltage gain ------------- 200V/mV

c) NE / SE 555 TIMER

Pin configuration



Specifications

1. Supply voltage ------------ 4.5 V to 18 V

2. Supply current ------------ 3mA

3. Output voltage (low) --------------- 0.1 V

4. Output voltage (high) --------------- 12.5 V (15 V Vcc) & 3.3 V (5V Vcc)

5. Maximum operating frequency --------------- 500 KHz

6. Timing --------------- µsec to hours

d) IC 566 VCO

Pin configuration

Specifications

1. Operating supply voltage (Vcc) --------- 12V (on less otherwise specified 24V).

2. Operating Supply current --------- 12.5mA

3. Input Voltage (Vc) --------- 3Vp-p.

4. Operating Temperature --------- 0 to 700C.

5. Power dissipation --------- 300mw.

e) NE / SE 565 PHASE LOCKED LOOP

Pin configuration



Specifications

1. Maximum supply voltage -----26 V

2. Input Voltage ----3 V(P-P)

3. Power dissipation ----300mw

4. Operating temperature ----NE 565- 00 C to 700C (SE 565—55 to +1250 C)

5. Supply voltage ----12 V

6. Supply current ----8mA

7. Output current- sink ----1mA

Output current- Source ----10 mA

f) IC 723 VOLTAGE REGULATOR

Pin configuration

Specifications

1. Input voltage ----------- 40V max.

2. Output voltage ----------- 2V to 37V.

3. Output current ----------- 150mA.

(With out external pass txt)

4. Output current ------------- 10A.

(With external pass txt)

5. Input regulation -------------- 0.02%.



6. Load regulation ------------- 0.03%.

7. Operating temperature ------------ - 550 C to 1250 C.

g) THREE TERMINAL VOLTAGE REGULATORS

i) IC 78XX (Positive Voltage Regulators)

Pin configuration

Specifications

1.Input voltage

For 5V to 18V regulated output ---------- 35V.

Upto 24V regulated output ---------- 40V.

2.Internal power dissipation ---------- Internally limited.

3.Storage temperature range -------- -650 C to 1500 C.

4.Operating junction Temperature range

µA7800 --------- -550 C to 1500 C.

µA7800C -------- 00 C to 1250 C.

ii) IC 79XX ( Negative Voltage Regulators )

Pin configuration



Specifications

1. Input voltage

For -5V to -18V regulated output ---------- -35V.

For -24V regulated output ---------- -40V.

2. Internal power dissipation ------- Internally limited.

3. Storage temperature range -------- -650 C to 1500 C.

4. Operating junction Temperature range

µA7800 --------- -550 C to 1500 C.

µA7800C -------- 00 C to 1250 C.

RESULT:

The pin configurations. specifications & functioning of different integrated circuits used in

the practical applications have been studied.

Experiment 1(a)

Design and implementation of Inverting Op-amp

Aim:

To design and study the open loop gain from Inverting Amplifier circuit.

Components required:

Function generator, CRO, Regulated Power supply, resistor, capacitor, 741 IC, connecting

wires.

Vlab Specifications Taken:

Inverting Amplifier circuit design has been implemented on the virtual breadboard using

following specifications:

· Power Supply: +10v and -10v

· Function generator: Selected wave with following specifications:

Frequency = 50Hz Amplitude: 750mV, 850mV, 900mV, 950mV, 1V, 2V. Duty cycle = 50%



· Resistor R2: 10.38K


Theory:

An inverting-amplifier circuit is built by grounding the positive input of the operational

amplifier and connecting resistors R1 and R2, called the feedback networks, between the

inverting input and the signal source and amplifier output node, respectively. With

assumption that reverse-transfer parameter is negligibly small, open-circuit voltage gain Av,

input resistance Zin and output resistance Zo can be calculated.

Inverting Amplifier configuration of an op-amp

Procedure:

1. Connect the circuit as shown in the circuit diagram.

2. Give the input signal as specified.

3. Switch on the power supply.

4. Note down the outputs from the CRO

5. Draw the necessary waveforms on the graph sheet.

Observations:

1. Observe the output waveform from CRO. An inverted and amplified waveform will be

observed.

2. Measure the input and output voltage from the input and output waveform in the CRO.

3. Calculate

4. Compare the theoretical voltage gain from the above equation with the experimental

value obtained by dividing output voltage by input voltages observed.

5. Observe outputs of the inverting amplifier circuit using different input waveforms.

VLab Observations Obtained:



For example, a case has been taken and the required parameters values is being noted down

below:

1. Input Voltage: 1.73VV

2. Frequency: 50Hz

3. Output Voltage: 11.9V

Calculations:

1.Calculate experimentally observed voltage gain Av using observed Vo& Vin from CRO.

2.Theoretically voltage gain is given by:

Result:

Hence the opamp can configure as inverting amplifier circuit as observed from the output

waveforms.

Precautions:

1. Connections should be verified before clicking run button.

2. The resistance to be chosen should be in Kohm range.

3. Best performance is being obtained within 50Hz to 1Mhz.

Experiment 1(b)

Design and implementation of Non Inverting Op-amp

Aim:

To design and study the open loop gain from Non-Inverting Amplifier circuit.

Components required:

Function generator, CRO, Regulated Power supply, resistor, capacitor, 741 IC, connecting

wires.

Vlab Specifications Taken:

Non-inverting amplifier circuit design has been implemented on the virtual breadboard using

following specifications:

· Power Supply: +10v and -10v



· Function generator: Selected wave with following specifications:

Frequency = 50Hz

Amplitude: 750mV, 850mV, 900mV, 950mV, 1V, 2V.

Duty cycle = 50%

· Resistor R2:10.38


Theory:

The operational amplifier can also be used to construct a non-inverting amplifier with the

circuit indicated below. The input signal is applied to the positive or non-inverting input

terminal of the operational amplifier, and a portion of the output signal is fed back to the

negative input terminal. Analysis of the circuit is performed by relating the voltage at V2 to

both the input voltage Vin and the output voltage Vo.

The output is applied back to the inverting (-) input through the feedback circuit (closed loop)

formed by the input resistor R1 and the feedback resistor R2. This creates ve feedback as

follows. Resistors R1 and R2 form a voltage-divider circuit, which reduces Vo and connects

the reduced voltage V2 to the inverting input.

Figure 1: Non-Inverting Amplifier configuration of an op-amp

Procedure:

1. Connect the circuit as shown in the circuit diagram.


3. Switch on the power supply.

4. Note down the outputs from the CRO

5. Draw the necessary waveforms on the graph sheet.

Observations:

1. Observe the output waveform from CRO. A non-inverted and amplified waveform will

be observed.


3. Calculate



4. Compare the theoretical voltage gain from the above equation with the experimental

value obtained by dividing output voltage by input voltages observed.

5. Observe outputs of the inverting amplifier circuit using different input waveforms.

VLab Observations Obtained:

For example, a case has been taken and the required parameters values is being noted down

below:

1. Input Voltage: 1.94VV

2. Frequency: 50Hz

3. Output Voltage: 17.3V

Calculations:

1. Calculate experimentally observed voltage gain Av using observed Vo & Vin from CRO.

2. Theoretically voltage gain is given by:

Result:

Hence the opamp can configure as non-inverting amplifier circuit as observed from the

output waveforms.

Precautions:

1. Connections should be verified before clicking run button.

2. The resistance to be choosen should be in Kohm range.

3. Best performance is being obtained within 50Hz to 1Mhz.

EXPERIMENT NO: 2

Adder and Subtractor using Op Amp (IC 741)

AIM: To design and study the operation of IC 741 Operational amplifier as

a) Adder

b) Subtractor

APPARATUS REQUIRED:

1. CDS Board with in-built power supply / Bread Board.

2. Function Generator



3. Cathode Ray Oscilloscope.

4. Digital Multimeter.

5. Regulated Power Supply (Dual Channel).

6. Connecting Wires.

COMPONENTS REQUIRED:

1. IC741 :1No

2. Decade Resistance Box (DRB) :1No

3. Resistor ------1KΩ :4No

10KΩ :3No

100KΩ :1No

CIRCUIT DIAGRAMS:

a) ADDER

Fig.1

b) SUBTRACTOR



Fig.2

THEORY:

Adder:

A typical summing amplifier (Inverting Adder) with three inputs Va ,Vb & Vc applied at the

inverting terminal of IC741 is shown in fig(1). The following analysis is carried out assuming

that the Op-Amp is an ideal one, that is AOL = ∞, Ri = ∞ & R0=0; since the input bias current

is assumed to be zero, there is no voltage drop across the resistor Rcomp and hence the non

inverting input terminal is at ground potential.

The voltage at node ‘A’ is zero as the non- inverting input terminal is grounded. The

nodal equation by KCL at node ‘a’ is given as

0a b c o

a b c f

f f f

o a b c

a b c

V V V V

R R R R

R R RV V V V

R R R

+ + + =

= − + +

Case (1):- Ra=Rb=Rc=Rf

V0 = - (Va + Vb+ Vc)

Case (2):- Ra=Rb=Rc=3Rf

V0 = - (Va + Vb+ Vc)/3

Subtractor



A typical subtractor with two inputs Va & Vb applied at the non-inverting terminal &

Inverting terminal of IC741 respectively is shown in fig(2). The following analysis is carried

out assuming that the Op-Amp is an ideal one, that is AOL = ∞, Ri = ∞ & R0=0;

Let Ra = Rb= Rf = R,

Vo= Va - Vb

PROCEDURE:

Adder

1. Connect the Adder circuit as shown in fig.1 with Ra = Rb = Rc = Rf = 1KΩ, RL =100KΩ

and R = 250Ω on the CDS board.

2. Switch ‘ON’ the power supply and apply + 15V to pin no.7 and -15V to pin no.4 of the

IC741.

3. Apply the input voltages from the regulated supplies to the corresponding inputs at the

inverting input terminal of IC741 (pin no.2).

3. Connect the Digital Multimeter at the Out put terminals (pin no.6), and note down the

output voltage and verify with theoretical values.

4. Repeat the above steps for different input voltages.

Subtractor

1. Connect the Subtractor circuit as shown in fig.2 with Ra = Rb = Rf = R = 1KΩ and RL

=100KΩ on the CDS board.


IC741.

3. Apply the input voltages from the regulated supplies to the corresponding inputs at the

inverting & non-inverting input terminals of IC741 (pin no.2 & 3 respectively).

3. Connect the Digital Multimeter at the Out put terminals (pin no.6), and note down the

output voltage and verify with theoretical values.

4. Repeat the above steps for different input voltages.

RESULT:

Adder and Subtractor are designed using 741 Op – Amp and the experimental results were

compared with the theoretical values



EXPERIMENT NO: 3

Comparators using Op Amp.

COMPARATOR

i. Non-Inverting Comparator

Fig.3

ii. Inverting Comparator

Fig.4



Theory

A Comparator is a circuit that makes a comparison between two signals applied on to

inverting and non-inverting input terminals. One signal is the input signal and the other is a

reference signal with which the input is compared. Based on the application of input signal to

inverting or non-inverting the comparators are of two types

1) Non-Inverting Comparator and

2) Inverting Comparator

As shown in the figure 3 and 4 respectively and their outputs are defined as + Vsat or – Vsat

depending on the relation between Vin and Vref.

Procedure

1. Connect the comparator circuit as shown in fig.3.

2. Connect the 1MHz function generator to the input terminals. Apply 1V signal at non-

inverting terminals of the op-amp IC741.

3. Connect the 20MHz C.R.O at the output terminals.

4. Keep 1V reference voltage at the Inverting terminal of the Op-amp. When Vin is less than

the Vref, then output voltage is at –Vsat because of the higher input voltage at negative

terminal. Therefore the output voltage is at logic low level

5. Now, Keep –1V reference voltage. When Vref is less than the Vin, then the output voltage is

at +Vsat because of the higher input voltage at positive terminal. Hence, the output voltage is

at logic high level.

6. Observe and record the output voltage and waveforms.

EXPECTED WAVEFORMS:

i) If Vref is Positive in the Inverting comparator



ii) If Vref is Negative in the Inverting comparator

If Vref is Positive in the Non-inverting comparator

If Vref is Negative in the Non-inverting comparator



RESULT:

Applied input signal is compared with reference voltages in a comparator using 741 Op –

Amp and the corresponding waveforms were noted.

REVIEW QUESTIONS:

1. Draw an Op- amp circuit whose output VO = V1+ V2 – V3 –V4.

2. Show that the o/p of an n-input inverting adder is V0 = - (Va +Vb + … + Vn)

3. Design a mixed adder for V0=V1+2V2-V3-5V4.

4. Design a Subtractor for V0 = Va - 5Vb -2Vc

5. If a triangular waveform is applied to an op-amp in open loop configuration, with non-

inverting terminal grounded, sketch the output wave form.

6. For the circuit shown determine the expression for V0.



8. For the circuit shown, find the current through R4.

Given: R1 = 10 kΩ; R2 = 20 kΩ; R3 = 1 kΩ, R4 = 4.8 kΩ; V1 = 1 V

9. Determine the value of V0 for the circuit shown, if V1 = 2V and V2 = 1V.

14. Calculate VO in the circuit shown below for V1 = 5V, V2 = 2V.



WORKSPACE



EXPERIMENT NO: 4

INTEGRATOR USING IC741

AIM: To design, construct and verify the response of Integrator using Op-amp IC741 for sine

and square wave inputs at 1 KHz frequency.

APPARATUS REQUIRED:

1. Bread Board / CDS Board.

2. Function Generator (1MHz).

3. Cathode Ray Oscilloscope (20MHz/30 MHz)




1. IC741 :1No

2. Resistor ----- 10KΩ :2No

3. 100KΩ POT/ Decade Resistance Box (DRB) :1No

4. 10KΩ POT/ Decade Resistance Box (DRB) :1No

5. Capacitor ---- 0.1µF :2No

CIRCUIT DIAGRAMS:

(a)Integrator:

Fig.1

THEORY:

(a) Integrator



A circuit in which the output voltage waveform is the integration of the input is called

integrator.

1. The equation (1) indicates that the output voltage is directly proportional to the negative

integral of the input voltage and inversely proportional to the time constant R1CF. For

Example if the input is a sine wave, the output will be a cosine wave or if the input is a square

wave, the output will be a triangular wave.

2. When the input signal frequency is ZERO, the integrator works as an open – loop

amplifier. This is because of the capacitor CF acts as an open circuit (XCF =1/ωCF = infinite

for f=0).

3. Therefore the ideal integrator becomes unstable & suffers with low frequency noise. To

overcome this problem RF is connected across the feed back capacitor CF. Thus RF limits the

low-frequency gain and hence minimizes the variations in the output voltage.

3. Frequency fb at which the gain of the integrator is 0 dB, is given by

fb =1/2∏R1CF -----------→ (2)

4. Both the stability and the low – frequency roll-off problems can be corrected by the

addition of a resistors RF in the feed back path. The frequency response of practical integrator

is as shown in fig (3). In this ‘f’ is relative operating frequency and for f < fa gain of the

integrator is constant and is equal to RF / R1. However after fa the gain decreases at a rate of

20dB/decade. In other words, between fa and fb the circuit acts as an integrator. The gain-

Limiting frequency fa is given by

fa =1/2∏RFCF ----------→ (3)

NOTE: The input signal will be integrated properly if the time period T of the input signal is

greater than or equal to RFCF.

PROCEDURE:

(a) Integrator

1. Connect the circuit as shown in fig.1 on the breadboard.


IC741.

3. Apply a sine wave input signal of 2V peak-to-peak amplitude at 1 KHz frequency from the

function generator (at pin no.2 of the IC741).

4. Connect the C.R.O at (pin no.6) the output terminals.

5. Observe and plot the input & output voltage waveforms.

6. Measure the output voltage (Vo) from the experimental results.

7. Calculate the output voltage of the inverting Amplifier theoretically using the formula



8. Apply a square wave input signal of 2V P-P amplitude at 1 KHz frequency from the

function generator and repeat the above steps.

9. Compare the experimental results with the theoretical values.

Fig.3. Frequency Response of Integrator

Fig.5a: Output waveform of Integrator for Sine wave input

Fig.5b: Output waveform of Integrator for Square wave input

RESULT: The Integrator circuits were constructed using IC 741 and verified their response

for sine & square wave inputs.

REVIEW QUESTIONS:



1. For an op-amp. integrator circuit, sine wave input of 4 Sin 1000t is given. In the

circuit, R = 200 MΩ and C = 0.1 μF. Determine the value of output voltage.

2. What type of output waveform is obtained when a triangular wave is applied to

integrator circuit?



Experiment 5

Differentiator circuit using Op Amp.

Aim:

Differentiator using Op-amp IC741 for sine and square wave inputs at 1 KHz frequency.

Fig.2

(b) Differentiator

The differentiator circuit performs the mathematical operation of differentiation. That is the

output waveform is the derivative of the input waveform. Therefore

VO = RFC1 dVin / dt --------------→ (4)

1. The above equation (4) indicates that the output voltage is directly proportional to the

derivative of the input voltage and also proportional to the time constant RFC1.

For Example if the input is a sine wave, the output will be a cosine wave or if the input is a

square wave, the output will be spikes.

2. The reactance of the circuit increases with increase in frequency at a rate of 20dB/ decade.

This makes the circuit unstable. In other words the gain of an ideal differentiator circuit is

direct dependent on input signal frequency. Therefore at high frequencies (f=∞), the gain of

the circuit becomes infinite making the system unstable.

3. The input impedance XC1 decreases with increase in frequency, which makes the circuit

very susceptible to high frequency noise.



4. The frequency response of the basic differentiator is shown in fig.4 In this fig fa is the

frequency at which the gain is 0 dB.

fa =1/2∏RFC1 -----------→ (5)

5. Both the stability and the high – frequency noise problem can be corrected by the addition

of two components R1 and CF as shown in fig.2.The frequency response of which is shown

in fig.4. From f to fa the gain decreases at 40dB/decade.This 40 dB/decade change in gain is

caused by the R1C1 and RFCF combinations. The gain limiting frequency fb is given by

fb =1/2∏R1C1 ----------→ (6) Where R1 C1 = RF CF.

R1C1 and RFCF help to reduce significantly the effect of high frequency input, amplifier

noise, and offsets. Above all, it makes the circuit more stable by preventing the increase in

gain with frequency. In general, the value of f1, and in turn R1C1 and RFCF should be selected

such that fa <fb < fc, Where fc is the unity gain- bandwidth of an open-loop Op-Amp.

NOTE: The input signal will be differentiated properly if the time period T of the input

signal is greater than or equal to RF C1.

(b) Differentiator



IC741.

3. Apply a sine wave input signal of 2V peak-to-peak amplitude at 1 KHz frequency from the

function generator (at pin no.2 of the IC741).


5. Observe and plot the input & output voltage waveforms.

6. Measure the output voltage (Vo) from the experimental results.

7. Calculate the output voltage of the inverting Amplifier theoretically using the formula VO

= RFC1 dVin / dt

8. Apply a square wave input signal of 2V P-P amplitude at 1 KHz frequency from the

function generator and repeat the above steps.

9. Compare the experimental results with the theoretical values.

EXPECTED WAVEFORMS:



Fig.4. Frequency Response of Differentiator

Fig.6a: Output waveform of Differentiator for Sine wave input

Fig.6b: Output waveform of Differentiator for Square wave input

RESULT: The Differentiator circuits were constructed using IC 741 and verified their

response for sine & square wave inputs.

REVIEW QUESTIONS:

1.Sketch the output wave forms, if a square wave input is applied to op-amp differentiator

circuit. Given R = 0.1 kΩ, C = 0.01 μF. frequency of the square wave input is 100 Hzs.



3. Sketch the Input and Output waveforms when we apply a 1Khz triangle wave with peak to

peak value of 5V to the Differentiator circuit.

4. A low frequency differentiator is desired for a particular application to Perform the

operation Vo (t) =-0.001 dvi(t)/dt . Determine the suitable design of differentiator circuit for

the periodic signal with a frequency of 1 KHz.

5.Determine the component values of a differentiator circuit to perform true differentiation,

when the input is a square wave of 1 kHz frequency.

WORKSPACE



EXPERIMENT NO: 6

ACTIVE FILTER APPLICATIONS – LPF, HPF(FIRST ORDER)

AIM: To design, construct and plot the frequency response of

a) First order low pass filter with cut-off frequency of 5 KHz

b) First order high pass filter with a cut-off frequency of 1 KHz.

APPARATUS REQUIRED:

1. Bread Board / CDC Board.

2. Function Generator (1MHz).

3. Cathode Ray Oscilloscope (20MHz/30 MHz)



6. Decade Resistance Box.


1. IC741 :1No

2. 1KΩ Potentiometer / DRB :1No

3. Resistor ------- 10KΩ :2No

100KΩ :1No

4. Capacitor ----- 0.1µF :1No

0.01µF :1No

CIRCUIT DIAGRAMS:

a) LOW PASS FILTER

Fig .1. Circuit diagram of 1st Order LPF



b) HIGH PASS FILTER

Fig .2. Circuit diagram of 1st Order HPF

THEORY:

A first order filter consists of a single RC network connected to the non-inverting

input terminal of the op-Amp as shown in the figure. Resistors R1 & Rf determine the gain of

the filter in the pass band. Components R & C determine the cutoff frequency of the filter.

Low-Pass filter: The circuit of 1st order low-pas filter is shown in fig.1 & its frequency

response is as shown in the fig3. The dashed curve in the fig.3 indicates the ideal response &

solid curve indicates practical filter response. It is not possible to achieve ideal

characteristics. However with special design techniques (Higher order filters) it is possible to

closely approximate the ideal response. Active filters are typically specified by the voltage

transfer function,

H(s) = V0 (s)/ Vi(s) ___________(1) (under steady state conditions)

i.e s=jω => H (jω) = H(jω) eJ Φ(w) _________(2), Where H (jω) is the magnitude

function and eJ Φ(w) is the phase function. Magnitude function is 20 log H(jω) dB &

phase function is -Φ(ω) * 57.296 degrees.

High Pass Filter: The circuit of 1st order high pass filter is shown in fig.2 & its frequency

response is as shown in the fig4. The dashed curve in the fig.4 indicates the ideal response &

solid curve indicates practical filter response. When an input signal is applied to High pass

filter, the signals at high frequencies are passed through circuit and signals at low frequencies

are rejected. That is the signal which are having frequencies less than the lower cutoff



frequency fL are rejected and the signal with frequency greater the lower cut off frequency fL

are passed through the circuit. That is

1. For f > fL, Vo(s) /Vi(s) = Maximum and is called as pass band.

2. For f < fL, Vo(s) /vi(s) = 0 and is called as the stop band

DESIGN:

Pass band gain of the active filter VO/Vin = Af = 1 + Rf/R1 __________(3)

Higher cut-off frequency of the low pass filter, fH =1/2ПRC ____________(4)

Lower cut-off frequency of the High pass filter, fL =1/2ПRC ____________(5)

First order LPF

1. The higher cut-off frequency is given as, fH = 5 KHz.

2. Choose the value of C such that the value of C ≤1µF (Typically C= 0.1µF)

3. Calculate the value of R, using the formula

R =1/2ПCfH ___________ (6)

= 318.47Ω (320 Ω Approx.)

4. Get the value of damping factor, α from the Butterworth polynomials

Note: For a 1st order Butterworth active filter, the value of damping factor α=1 (from

Butterworth polynomials)

5. Calculate the value of pass-band gain, AF using the formula, α =3-Af _________ (7)

=> AF = 3- α = 3-1= 2 _________ (8)

6. Using the formula AF = 1 + RF/R1, get a relation between RF & R1.

=> RF/R1= AF -1 = 1

=> RF= R1 _______________(9)

7. Choose the value of R1=10 KΩ => RF=10 KΩ ___________ (10)

First order HPF

1. The lower cut-off frequency is given as, fL = 1 KHz.

2. Choose the value of C such that the value of C ≤1µF (Typically C= 0.01µF)

3. Calculate the value of R, using the formula

R =1/2ПCfL

= 15.9 KΩ __________ (11)

4. Get the value of damping factor, α from the Butterworth polynomials



Note: For a 1st order Butterworth active filter, the value of damping factor α=1 (from

Butterworth polynomials)

5. Calculate the value of pass-band gain, AF using the formula, α =3-Af _________ (12)

=> AF = 3- α = 3-1= 2 ___________ (13)

6. Using the formula AF = 1 + RF/R1, get a relation between RF & R1.

=> RF/R1= AF -1 = 1

=> RF= R1 __________ (14)

7. Choose the value of R1=10 KΩ => RF=10 KΩ ___________ (15)

PROCEDURE:

Low pass Filter



IC741.

3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator

(at pin no.3 of the IC741 via RC Low pass network).


5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the

corresponding output voltage of the filter and tabulate the results.

6. Calculate the gain of the filter from the experimental results.

7. Plot the frequency response curve of the low pass filter with the experimental results

obtained & compare it with the expected waveform shown in Fig.1.

OBSERVATION TABLE: VIN = 2V p-p

Input

Frequency(fin)

in Hz

Vin

Input volatage in

volts

Vout

Output Voltage

in volts

GAIN

Vout / Vin 20 Log (Vout / Vin)

Magnitude in dB



High pass Filter



IC741.

3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator

(at pin no.3 of the IC741 via RC High pass network).


5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the

corresponding output voltage of the filter and the results.

6. Calculate the gain of the filter from the experimental results.

7. Plot the frequency response curve of the high pass filter with the experimental results

obtained & compare it with the expected waveform shown in Fig.2.

OBSERVATION TABLE:

VIN = 2V P-P

Input

Frequency(Fin)

in Hz

Vin

Input volatage in

volts

Vout

Output Voltage

in volts

GAIN


Magnitude in dB



EXPECTED WAVEFORMS:

Fig. 3 Frequency response of 1st Order LPF



Fig. 4 Frequency response of 1st Order HPF

RESULT: The first order LPF & HPF are designed for a chosen cutoff frequency and the

frequency response curves were plotted between voltage gain (dB) and frequency (Hz).

REVIEW QUESTIONS:

1. Design a first order low pass filter for 2 KHz frequency.

2. Design a five pole low pass active Butter worth filter with 3dB cut off frequency of 2 KHz.

3. Show that the amplitude response of low pass Butter worth filter well above cutoff

decreases by 20dB per decade.

4. Draw the fourth order High pass filter for cut off frequency fL=10 KHz.

5. Design a two pole high pass active Butter worth filter with a 3dB cutoff frequency of 1

KHz.

6. Design 4th order butter worth high pass filter with 3dB cutoff frequency of 5 KHz.

WORKSPACE



EXPERIMENT NO: 7

IC 741 WAVEFORM GENERATORS

Aim: To generate sine, triangular and square waveforms and to determine the Frequency of

oscillations.

Apparatus & Components Required:

1. Op-Amp IC 741 - 2No.

2. Bread board

3. Capacitor 0.1µF - 3No.

4. RPS (0 - 30V) - 1No.

5. Resistors - 10K - 2No., 470K - 1No.,1K - 3No.

6. Connecting wires

7. CRO(20MHz)

Circuit diagrams:

Sine Wave Generator: (RC phase shift oscillator)

Fig - 1

Square and Triangular Wave Generator:



Fig - 2

Theory:

RC oscillator is build using an amplifier and a RC network in feedback. For any oscillator the

two prime requirements to generate sustained and constant oscillations are

1. The total phase shift around loop must be 00 or 3600 degrees.

2. The loop gain should be equal to unity.

This is known as “Barkhausen Criterion”

In RC phase shift oscillator op-amp is used as an amplifier in inverting configuration. It gives

180o phase shift in its output. So the RC feedback network following the amplifier has to

produce additional 180o phase shift to make total phase shift 360o / 0o.

The circuit oscillates at a frequency F = 1 / 2πRC√6

The time period of the output of the uA741 square wave generator can be expressed using the

following equation:

The common practice is to make the R3 equal to R2. Then the equation for the time period can

be simplified as: T = 2.1976R1C1

The frequency can be determined by the equation: F = 1/T

Procedure:

For Sine Wave Generation:

1. Connect the circuit as per the circuit diagram shown in Fig 1.

2. Give +12V, -12V and ground to circuit from power supply

3. Observe the output on the CRO.

4. Calculate theoretical and practical output signal frequency and compare them.



For Square and Triangular Wave Generation:

1. Connect the circuit as per the circuit diagram shown in Fig 2.

2. Observe square wave at Vo’ and Triangular wave at Vo” as shown in figure 3.

3. Plot the waveforms on the graph sheet.

4. Calculate the frequency theoretically and compare them with the practical one.

Expected Waveforms:

Fig - 3.

Result:

Designed and verified the waveforms of waveform Generator using IC741.



Workspace



EXPERIMENT NO: 8

IC 555 TIMER - MONOSTABLE MULTIVIBRATOR

AIM: To design a Monostable Multivibrator using 555 timer to get 10msec. pulse output.

APPARATUS REQUIRED:

1. C.R.O

2. Regulated DC power Supply

3. Function generator

4. CDS Board/ Bread Board.

5. Connecting patch chords.


1. IC 555 Timer :1 No.

2. Resistors ---- 100 KΩ :1 No.

3. Capacitor ---- 1µF :1 No.

0.01µF :1 No.

CIRCUIT DIAGRAM:

Fig.1 Monostable Multivibrator



Fig.2. Trigger Circuit

THEORY:

The 555 Timer is used in number of applications; it can be used as monostable,

astable multivibrators, DC to DC converters, digital logic probes, analog frequency meters,

voltage regulators and time delay circuits.

The IC 555 timer is 8-pin IC and it can operate in free- running (Astable) mode or in

one-shot (Monostable) mode. It can produce accurate and highly stable time delays or

oscillations. Monostable can also called as One-shot Multivibarator. Fig (1) shows the Pin

configuration of Monostable Multivibrator. When the output is low, the circuit is in stable

state, Transistor Q1 is ON and capacitor C is shorted out to ground. However, upon

application of a negative trigger pulse to pin-2, transistor Q1 is turned OFF, which releases

short circuit across the external capacitor and drives the output High. The capacitor C now

starts charging up toward Vcc through R. However, when the voltage across the external

capacitor equals 2/3 Vcc, the output of comparator1 switches from low to high, which in turn

drives the output to its low state. The output, Q of the flip flop turns transistor Q1 ON, and

hence, capacitor C rapidly discharges through the transistor. The output of the Monostable

remains low until a trigger pulse is again applied. Then the cycle repeats. Fig (2) shows the

trigger circuit & Fig.3 shows trigger input, output voltage and capacitor voltage waveforms.

Pulse width of the trigger input must be smaller than the expected pulse width of the output

waveforms. Trigger pulse must be a negative going input signal with amplitude larger than

1/3 Vcc. The time during which the output remains high is given by



tp =1.1RC -------------(1)

Once triggered, the circuit’s output will remain in the high state until the set time tp elapses.

The output will not change its state even if an input trigger is applied again during this time

interval tp.

DESIGN:

Step 1: Choose C=1µF.

Step 2: Since in monostable multivibrator, tp=1.1RC. Therefore R= tp / 1.1C ---- (2)

Step 3: Using equation (2), design the value of R.

PROCEDURE:

1. Connect the 555 timer in Monostable mode as shown in fig.1.

2. Connect the C.R.O at the output terminals & observe the output.

3. Apply external trigger at the trigger input terminal (PIN 2) and observe the output of

Monostable Multivibrator.

4. Record the trigger input, voltage across the capacitor & output waveforms and measure the

output pulse width.

5. Verify results with the sample output waveforms as shown in fig (3)

6. Calculate the time period of pulse (tp =1.1RC) theoretically & compare it with practical

values.

OBSERVATION TABLE:

S.No Theoretical value of o/p pulse width (in m.sec)

(tp =1.1RC)

Practical value of the o/p

pulse width (in m.sec)

EXPECTED WAVEFORMS:



Fig.3

RESULT: Hence designed & studied 555 timer as a Monostable multivibrator and also

theoretical & Practical of time period values of the output waveform are compared.

REVIEW QUESTIONS:

1. Consider 555 monostable multivibrator circuit. If RA = 10 kΩ, determine the value of C

for output pulse duration of 1 msec.

2. For the above circuit, if RA = 10 kΩ and C = 0.1 μF, determine the value of tH.

3. In the case of 555 monostable circuit, if RA = 10 kΩ and C = 0.2 μF, calculate the time

interval.

4. Considering the circuit of Problem 6, 7 and 8, what value of RA should be installed, to

divide a 5 kHz input signal by 3?

5. The Monostable multivibrator circuit is to be used as a divided by 2 network. The

frequency of the input trigger signal is 2 KHz. If the value of C=0.01 µF, what should be

the value of RA (Let tp =1.2T)

6. Consider the Monostable multivibrator with R=3KΩ and C=0.0068µF. Determine the

pulse width.

7. Design a Monostable multivibrator to produce an output pulse 2 msec wide.



WORKSPACE



EXPERIMENT NO: 9

ASTABLE MULTIVIBRATOR USING 555 TIMER

AIM: To design an Astable Multivibrator using IC 555 timer to generate a square wave of

6.9 KHz with 52.38 % Duty Cycle.

APPARATUS:

1. C.R.O





COMPONENTS:

1. IC 555 Timer : 1 No.

2. Resistors ------ 10 KΩ : 1 No.

1KΩ : 1 No.

3. Capacitor ---- 0.01 µF : 1 No.

0.1 µF : 1 No.

PIN CONFIGURATION OF 555 TIMER:

Fig. 1



CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

Fig. 2

THEORY:

The 555 Timer is used in number of applications; it can be used as monostable, astable

multivibrators, DC to DC converters, digital logic probes, analogy frequency meters, voltage

regulators and time delay circuits. The IC 555 timer is 8-pin IC and it can operate in free-

running (Astable) mode or in one-shot (Monostable) mode. The pin configuration of NE 555

Timer is as shown fig (1). It can produce accurate and highly stable time delays or

oscillations.

Astable Multivibrator often called a free-running Multivibrator. External Trigger

input is not required to operate the 555 as an Astable Configuration. However, the time

during which the output is either high or low is determined by two external components

Resistor & Capacitor. Fig (2) shows the 555 as Astable Multivibrator. Initially, when the

output is high, capacitor C starts charging towards Vcc through resistor Ra and Rb. As soon as

voltage across the capacitor equals to 2/3 Vcc, comparator-1 triggers the flip-flop, and the

output is low. Now capacitor discharges through Rb and transistor Q1. When the voltage

across capacitor C equals to 1/3Vcc, comparator-2’s output triggers the flip-flop, and the



output goes high. Then the cycle repeats. The output voltage waveforms are as shown in fig

(3).In this way capacitor periodically charges and discharges between 2/3Vcc and 1/3Vcc

respectively.

The time during which the capacitor charges from 1/3Vcc to 2/3 Vcc is equal to the

ON time of the timer (i.e. the output is HIGH) and is given by

tc =0.69(R1+R2)C ---- (1)

The time during which the capacitor discharges from 2/3 Vcc to 1/3Vcc is equal to the OFF

time of the timer, during which the output is LOW and is given by

td =0.69(R2)C --- (2)

The total time period of the output is the sum of charging time( tc )and discharging time(td)

and is given by

T = tc + td = 0.69(R1 + 2R2) C --- (3)

Therefore the frequency of oscillations of Astable multivibrator is given by

F = 1/T = 1.45/ (R1 + 2R2) C --- (4)

DUTY CYCLE:

This term is in conjunction with Astable Multivibrator. The duty cycle is the ratio of the ON

time, tc during which the output is high to the total time period T. It is generally expressed as

a percentage.

Duty cycle,D = (TON /TON+ TOFF) = tc /T = (R1 + R2) / (R1 + 2R2) --- (5)

DESIGN:

Step1: Choose C=0.01 µF

Step2: using the formula, F = 1.45/ (R1 + 2R2) C, Get a relation between R1 & R2.

Step3: Consider the expression for duty cycle, D= (TON /TON+ TOFF) = (R1 + R2) / (R1 +2R2)

& obtain a relation between R1 & R2.

Step4: Using the relations between R1 & R2., obtained in step2 & step3, solve for R1 & R2.

PROCEDURE:

1. Connect the IC 555 timer in Astable mode as shown in fig.2

2. Connect the C.R.O at the output terminal (pin 3) and observe the output.

3. Record the waveforms at pin3, across the capacitor & compare them with the

sample output waveforms as shown in fig (3)

4. Measure the charging time (tc), discharging time (td) and total time period/ Frequency from

the output waveform.

5. Calculate tc, td, time period (T), frequency (f) of the square wave output and percentage

duty cycle theoretically.



6. Compare the theoretical values charging time (tc), discharging time (td) ,total time period/

Frequency & % Duty cycle with the practical values.

OBSERVATION TABLE:

S.NO Theoretical Values Practical Values

tc

(m.sec)

td

(m.sec)

T

(m.sec)

f

(in Hz)

D tc

(m.sec)

td

(m.sec)

T

(m.sec)

F

(inHz)

D

EXPECTED WAVEFORMS:

Fig.3

RESULT: Hence designed & studied IC 555 timer as an Astable multivibrator and also

calculated the frequency of oscillations & time period of output waveform.

REVIEW QUESTIONS:

1. List the important features of the IC555 Timer. 2. Define Duty cycle.

2. Consider the Astable multivibrator with R1=10KΩ,R2=200KΩ and C=0.1µF. Determine

a) High state interval b) Low state interval c) Period d) Frequency e) Duty cycle.



3. Design an Astable 555 timer circuit to produce a 2kHz square wave with a duty cycle of

70%. 6. What is the function of control input (pin5) of 555 timer?

4. Compare the time period ‘T’ of the Astable multivibrator using IC555 timer& op-amp

IC741.

5. Why do we connect pin 4 of IC 555 timer to supply pin when it is not used.

Workspace



EXPERIMENT NO: 10

SCHMITT TRIGGER CIRCUIT USING IC 741

AIM: To construct and study the Schmitt Trigger using IC741 Operational Amplifier.

APPARATUS REQUIRED:

1. Function Generator.

2. Regulated DC power Supply.

3. Dual Channel Oscilloscope(CRO).


5. CDS Board / Bread Board.

6. Connecting wires.


1. IC 741 : 1 No.

2. Resistors -------- 1KΩ : 2 No.

3. Decade Resistance Box (DRB) : 1 No.

CIRCUIT DIAGRAM:

Fig.1

THEORY:

Circuit diagram of Schmitt trigger is shown in Fig 1. It’s also called regenerative

comparator. The input Voltage is applied to the inverting terminal & feed back voltage to the

non-inverting terminal. The input voltage vi triggers the output Vo every time it exceeds

certain voltage levels. These voltage levels are called upper threshold & lower threshold. The

hysteresis width is difference between these two values.



These voltages are calculated as follows

Suppose the output voltage Vo= +Vsat. The voltage at inverting terminal will be

2

1 2

ref sat ref ut

RV V V V

R R + − = +

----- (1)

For Vo= -Vsat then

2

1 2

ref sat ref lt

RV V V V

R R − + = +

---- (2)

The input voltage Vi must become lesser than VL in order to cause Vo to switch from -Vsat to

+ Vsat.

The hysterisis width VH can be written as

2

1 2

2H ut lt sat

RV V V V

V V= − =

+ ---- (3)

PROCEDURE:

1. Connect the circuit as shown Fig.1.

2. Set Function Generator output for sine wave signal of Amplitude at 1V(p-p) & frequency

1KHz.

3. Set R1 and R2 values at fixed positions and note down the values in tabular column.

Calculate theoretical values of Vut and Vlt and note down the values in tabular column.

(+Vsat = 14V,- Vsat = -14V).

4. Apply Function Generator output at input terminals Vi, connect C.R.O- CH2 at output

terminals Vo, C.R.O-CH1 at input terminals Vi.

5. Observe square wave output on C.R.O for the given input sine wave & compare them

with the sample waveform as shown in fig.2.

6. Note down the practical Vut , Vlt and VH values in tabular column.

7. Compare the theoretical and practical values of Vut,Vlt and VH.

OBSERVATION TABLE:

S.No

Theoretical Values Practical Values

R

1

R2 ( )= +

+

1

1 2

ut sat

RV V

R R

in Volts

( )= −+

1

1 2lt sat

RV V

R R

in Volts

VH

in

volts

Vlt

(Volts)

Vut

(Volts)

VH

in

volts



INPUT AND OUTPUT WAVE FORMS OF SCHMITTH TRIGGER:

Fig.2

RESULT: Hence constructed and studied Schmitt trigger using IC 741.



WORKSPACE



EXPERIMENT NO. 11

PHASE LOCKED LOOP (PLL) USING IC 565

AIM: To calculate free running frequency, capture range and lock range of PLL System.

APPARATUS REQUIRED:

1. C.R.O


3. DC power supply

4. CDS board / Bread Board

5. Connecting wires


1. LM 565 IC : 1No

2. Resistors 10K : 1No

680Ω : 2No

3. Capacitors 0.1F : 1No

1F : 1No

0.01F : 1No

CIRCUIT DIAGRAM:

Fig. 1 Phase-locked loop (PLL)



PIN DIAGRAM:

Fig.2.Pin configuration of IC 565

THEORY:

The fig.1 shows the phase-locked loop (PLL) in its basic form. The PLL consists of

i) a phase detector ii) a low pass filter and iii) a voltage controlled oscillator as shown.

The phase detector, or comparator compares the input frequency fIN with the

feedback frequency fOUT. The output of the phase detector is proportional to the phase

difference between fIN and fout. The output voltage of a phase detector is a dc voltage and

therefore is often referred to as the error voltage. The output of the phase detector is then

applied to the low-pass filter, which removes the high-frequency noise and produces a dc

level. This dc level, in turn, is the input to the voltage-controlled oscillator (VCO). The filter

also helps in establishing the dynamic characteristics of the PLL circuit. The output

frequency of the VCO is directly proportional to the input dc level. The VCO frequency is

compared with the input frequencies and adjusted until it is equal to the input frequencies. In

short, the phase-locked loop goes through three states: free running, capture, and phase lock.

Before the input is applied, the phase-locked loop is in the free-running state.

Once the input frequency is applied, the VCO frequency starts to change and the phase-

locked loop is said to be in the capture mode. The VCO frequency continues to change until it

equals the input frequency, and the phase-locked state. When phase locked, the loop tracks

any change in the input frequency through its repetitive action.

Lock Range: The range of frequencies over which the PLL can maintain lock with

incoming signal is called the “ Lock Range” or “Track Range”

fL= 8f0/V-------(1) where V= + V –(–V),

where f0 is free running frequency.



Capture range: The range of frequencies over which the PLL can acquire lock with an

input signal is called the capture range.

fC = [fL / 2(3.6 103)C2 ] ½ ---------(2)

PROCEDURE:

1. Apply +5v to pin 10 and –5v to pin 1 of LM565

2. Connect R1= 10K resistor from pin 8 to10 and C1 =0.01F capacitor from pin 9 to

1.

3. Connect 680 resistor from pin 2 & pin 3 to ground.

4. Connect pin 4(VCO o/p) to CRO and measure its frequency. This frequency is called

the free running frequency, fo.

5. Calculate f0 theoretically using the formula f0 = 1.2 /4R1C1 and compare it with

practical value.

6. Connect the circuit as shown in fig.

7. Apply square wave at the input with an amplitude of 2Vpp and also connect it to

channel 1 of CRO.

8. Connect pin 4(VCO o/p) to channel 2 of CRO.

9. Vary the input signal frequency in steps and measure its corresponding o/p frequency.

10. Find the lock range and capture range from the obtained data.

11. Calculate lock range, fL and capture range, fC theoretically using formula

fL = 8 f0/V Hz where V = +V- (-V)

and fC = [ fL/(2 3.6 103 C2 ) ]1/2

12. Compare theoretical and practical values.

TABULAR COLUMN:

S.No. Input

frequency, Hz

Output

frequency, Hz fC in Hz fL in Hz



RESULT: Free running frequency, lock range and capture range of PLL are measured

practically and compared with theoretical values.

REVIEW QUESTIONS:

1. 1. For a PLL select the filter components whose lowest frequency from phase detector

is 5 Hz. A 0.5% variation in frequency is allowable. How long will it take for output

from the filter to stabilize?

2. Design a PLL for the given specificatons, f0 = 2.5 kHz, fc = 50 Hz, VCC = − VEE = 12

V.

3. If the free running frequency, VC voltage shift from VCO, the new frequency shift

from VCO in a PLL is?

4.Determine the dc controlled voltage Vc at lock if signal frequency fs= 10 KHz,VCO

free running frequency is 10.66kHz and the voltage to frequency transfer coefficient of

VCO is 6600Hz/V.

5.Calculate the output frequency fo , lock range ΔfL and capture range Δfc of a 565 PLL if

RT=10KΩ ,CT= 0.01µF and C=10µF.



WORKSPACE



EXPERIMENT NO: 12

VOLTAGE REGULATOR USING IC 723

AIM: a) To construct and study low and high voltage regulators using IC 723.

b) To find the %regulation of low and high voltage regulators.

APPARATUS REQUIRED:

1. Oscilloscope.



4. CDS Board / Bread Board

5. Regulated Power Supply


1. IC 723 : 1No.

2. 10K POT : 1No.

3. Resistors ---- 2.2KΩ : 2No.

1 KΩ : 1No.

4. Capacitors ---- 100 pF : 1No.

0.1 µF : 1No.

CIRCUIT DIAGRAM:

Fig.1 Low voltage Regulator



Fig.2 High Voltage Regulator

THEORY:

The IC 723 is a monolithic integrated circuit voltage regulator featuring high ripple rejection,

excellent input and load regulation & excellent temperature stability etc. It consists of a

temperature compensating reference voltage amplifier, an error amplifier, 150mA output

transistor and an adjustable output current limiter.

The basic low voltage regulator type 723 circuit is shown in figure.1.The unregulated

input voltage is 24V and the regulated output voltage is varied from 0.2V to 7.5V by varying

the value of R2. A stabilizing capacitor (C1) of 100pF is connected between frequency

compensation terminal and inverting (INV) terminal. External NPN pass transistor is added

to the basic 723-regulator circuit to increase its load current capability. For intermediate

output voltages the following formula can be used

Vout = (R2/R1+R2) Vref ----------(1)

The basic high voltage regulator type 723 circuit is shown in figure.2.The output voltage can

be regulated from 7 to 37Volts for an input voltage range from 9.5 to 40Volts. For

intermediate output voltages the following formula can be used

1 2 *

2

R RV V

out refR

+= ----------(2)



PROCEDURE:

LOW VOLTAGE REGULATOR

1. Connect the circuit diagram as shown in figure.1.

2. Apply the unregulated voltage to the 723 IC and note down the regulator output voltage.

3.Calculate the line regulation of the regulator using the formula

Line Regulation = ΔVO / ΔVi ------------- (3)

4. By varying 10K potentiometer at the load section and note down the regulator output

voltage.

5. Calculate the Load regulation of the regulator using the formula

Load Regulation ==ΔVO / ΔIL ------------ (4)

6. Also calculate the Percentage of load regulation using the formula

1 2

1

*100E E

E

− ----------------- (5)

Where E1 = Out put voltage without load & E2 = Out put voltage with load.

HIGH VOLTAGE REGULATOR


2. Apply the unregulated voltage to the 723 IC and note down the regulator output voltage.

3. Calculate the line regulation of the regulator using the formula

Line Regulation = ΔVO / ΔVi ------------ (6)

4. By varying 10K potentiometer at the load section and note down the regulator output

voltage.


Load Regulation = ΔVO / ΔIL ------------ (7)

6. Also calculate the Percentage of load regulation using the formula

1 2

1

*100E E

E

−-----------------(8)

Where E1 = Out put voltage without load & E2 = Out put voltage with load.



OBSERVATION TABLE:

i) FOR LOW VOLTAGE REGULATOR

LINE REGULATION: (RL is constant)

S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is Constant)

S.No Load Resistance, RL in Ohms Regulated DC output, VO in Volts



ii) FOR HIGH VOLTAGE REGULATOR


S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is constant)

S.No Load Resistance, RL in Ohms Regulated DC output, VO in Volts



EXPECTED WAVE FORMS

Fig.3. Line Regulation



Fig.4. Load Regulation

RESULT: Low and high voltage regulators using IC 723 were constructed and studied. Also

the line and load regulations of the low & high voltage regulators are verified.

REVIEW QUESTIONS:

1. Design a high voltage and low voltage regulator using IC 723.

2. Design a series regulated power supply to provide a nominal output voltage of 20 V, at IL =

1.2 A. Given Vi = 40 ± 5 V, r0 = 15 Ω, Rz = 10 Ω, Iz = 15 mA, IC2 = 12 mA, hie2 = 600 Ω. hfe2

= 300. IL = 10 mA.

3. Design a regulated power supply using 3-terminal I.C. to give V0 = + 5 V. I0 = 0.6 A, Vin =

12 VDC, TA = 60°C.

4. Design a power supply using 3-terminal I.C. regulator to give + 5 V output at 400 μA at

30°C.

5. Using I.Cs, design a regulated power supply to give output voltage, which is adjustable

from 1.2 V to 12 V. IL is to be 0.5 A, TA = 35°C.

WORKSPACE



EXPERIMENT NO: 13

THREE TERMINAL VOLTAGE REGULATORS

AIM: a) To construct and study the 3-terminal fixed voltage regulator using IC 78XX and

79XX series.

b) To find line regulation and load regulation of the IC regulator.

APPARATUS REQUIRED:

1. Multimeter

2. Regulated DC Dual Power supply

3. CDS Board / Bread Board

4. Connecting patch Chords


1. Capacitors --- 1000 µF : 1 No.

--- 22 µF : 1 No.

2. IC’s

7805 :1No

7812 :1No

7905 :1No

7912 :1No

CIRCUIT DIAGRAM:

a) Fixed Positive Voltage regulator:

Fig.1

b) Fixed Negative Voltage Regulator:



Fig.2

PROCEDURE:

For fixed positive voltage regulator (78XX):


2. Apply the unregulated voltage to the IC 78XX and note down the regulator output voltage,

vary input voltage from 7V to 20V and record the output voltages



4. By varying the load resistance RL note down the regulator output voltage.



For fixed negative voltage regulator (79XX):


2. Apply the unregulated voltage to the IC 79XX and note down the regulator output voltage,

vary input voltage from 7V to 20V and record the output voltages



4. By varying the load resistance RL note down the regulator output voltage.



OBSERVATION TABLES:

FOR POSITIVE VOLTAGE REGULATOR


S.NO Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts



LOAD REGULATION: (Vi is Constant)

S.NO Load Resistance, RL in Ohms Regulated DC output, VO in Volts

FOR NEGATIVE VOLTAGE REGULATOR







EXPECTED WAVE FORMS



Fig.3. Line Regulation For 78XX

Fig.4. Load Regulation for 78XX

Fig.5. Line Regulation for 79XX



Fig.6. Load Regulation for 79XX

RESULT: Hence constructed and studied the 3-terminal fixed voltage regulator using IC

78XX and 79XX series & also the line regulation and load regulation of them are verified.

REVIEW QUESTIONS:

1. Design a regulated power supply using 3-terminal I.C. to give V0 = + 5 V. I0 = 0.6 A, Vin

= 12 VDC, TA = 60°C.

2. Design a power supply using 3-terminal I.C. regulator to give + 5 V output at 400 μA at

30°C.

3. Using I.Cs, design a regulated power supply to give output voltage, which is adjustable

from 1.2 V to 12 V. IL is to be 0.5 A, TA = 35°C.

4. Design a current source using 7805 to supply a load current of 0.6 A, to drive a load of 20

Ω.

5.Design a voltage regulator using 78XX regulator to get a voltage output of 15V.

WORKSPACE



EXPERIMENTS BEYOND OF SYLLABUS

EXPERIMENT NO: 1

FREQUENCY RESPONSE OF BAND PASS AND BAND REJECT ACTIVE FILTERS

AIM: To design, construct and study the frequency response of

APPARATUS REQUIRED:

1. Bread Board / CDS Board.


3. Cathode Ray Oscilloscope




1. IC741 :1No

2. Resistor ----- 1KΩ :3No

10KΩ :4No

100KΩ :1No

3. Decade Resistance Box (DRB) :3No

4. Capacitor ----- 0.01µF :1No

0.1 µF :1No

THEORY:

BAND PASS FILTER:

A Band Pass Filter (BPF) has a pass band between the lower cut-off frequency, fL & the

higher cut-off frequency fH, such that fH > fL. When the input frequency is zero, the gain of

the filter will be zero. As the input signal frequency increases from zero to fL, the gain will

increase at a rate 20dB/decade up to 3dB less than its maximum value. If the input signal

frequency increases beyond fL, the gain will reach its maximum value and remains constant

up to high frequencies as shown in the Fig.3. When the input signal frequency reaches the

higher cut-off frequency, fH, the gain will fall 3dB less from its maximum value. If the input



signal frequency increases beyond fH, the gain will decreases to zero at rate of 20dB/decade.

After reaching the total pass band region, the gain of the filter is constant up to its designed fH

(high cut off frequency).

There is a phase shift between input and output voltages of BPF as a function of

frequency in its Pass Band region. This filter passes all frequencies equally well i.e. the

output and input voltages are equal in amplitude for all frequencies. This highest frequency

up to which the input and output amplitudes remain equal is dependent of the unity gain

bandwidth of Op – Amp. At this frequency, the phase shift between input and output

becomes maximum.

BAND REJECT FILTER:

A Band Reject Filter (BRF) has a stop band between the cutoff frequencies fH & fL

such that fH < fL. When the input signal frequency is zero, the gain of the BPF will be

maximum and will remains constant as the input signal frequency increases. At the higher cut

off frequency fH, the gain becomes 3dB less than its maximum value. As the input signal

frequency increases beyond fH, the gain of the filter decreases & becomes zero at the central

(fC) or operating frequency (fO). After this center frequency fC, the gain increases to 3dB less

than its maximum value at the lower cut-off frequency, fL. As the input signal frequency

increases beyond fL the gain increases to the maximum value and becomes constant.

There is a phase shift between input and output voltages of BPF in its “Pass band region”.

This filter passes all the frequencies equally well i.e. output and input voltages are equal in

(magnitude) amplitude for all frequencies. This highest frequency up to which the input and

output amplitude remains equal is dependent on the unity gain bandwidth of the Op- Amp.

However at this frequency, the phase shift between the input and output is maximum.

DESIGN:

a) BAND PASS FILTER

1. Select the cutoff frequencies, fH = 5KHz & fL =1KHz of BPF.

Where fH = Higher cutoff frequency & fL = Lower cutoff frequency

2. The central or operating frequency, fC = HL ff

3. i) For Low Pass Section

Using the formula1

2 'Hf

R C=

1'

2 H

Rf C

= , estimate the value of R’.

ii) For high pass section



Using the formula 1

2Lf

RC=

1

2 L

Rf C

= , estimate the value of R.

If the band pass gain is 4 the gain of the high pass as well as low pass section could be set to

2 i.e. input and feed back resistors must be equal in value. The magnitude of voltage gain is

given by

Where AFT = Total Pass band gain

f = Signal input frequency (Hz)

fL= Low cutoff frequency

fH= High Cutoff frequency

b) BAND REJECT FILTER

Select the cutoff frequencies of BPF fH =200Hz & fL = 1KHz

fh = Higher cutoff frequency

fL = Lower cutoff frequency

fC = HL ff

and 1

1

RFA

f R= +

If Af = 2 RF = R1. and Let Rf = R1 = 10 KΩ

i) For Low Pass Section

1

2 ' 'Hf

R C=

1'

2 'H

Rf C

=

ii) For high pass section

1

2Lf

RC=

1

2 L

Rf C

=

There is no restriction on the pass band gain. Use a gain of 2 for each section.

Hence R1 = RF the gain of the summing amplifier is set at 1, therefore

Ra = Rb = Rc =1KΩ and the value of RCM = Ra|| Rb || Rc= 333Ω.

The complete circuit is shown in figure. The voltage gain changes at the rate of 20dB/decade

above fH and below fL. With a maximum attenuation occurring at fC, where fC = center

frequency.

CIRCUIT DIAGRAMS:



BAND PASS FILTER:

Fig.1 Circuit Diagram of Wide Band-Pass Filter

BAND REJECT FILTER:

Fig.2 Circuit Diagram for Wide Band-Reject Filter

PROCEDURE:

1. Make the circuit connection as shown in figure.

2. Connect the signal generator to input terminals. And connect the C.R.O at output

terminals of the trainer & switch on the trainer.

3. Apply the input signal frequency from 100Hz to 10 KHz.



4. Record the input frequency, Input voltage and Output voltage. Find the gain of the

BPF using the formula. The gain magnitude in dB is equal to 20 Log (Vo/Vi).

OBSERVATION TABLES:

Band Pass Filter:

Input

Frequency(Fin)

Vin

Input volatage

Vout

Output Voltage

GAIN


Magnitude in dB’s

Band Reject Filter:

Input

Frequency(Fin)

Vin

Input volatage

Vout

Output Voltage

GAIN


Magnitude in dB’s



EXPECTED WAVEFORMS:

Fig.3 Frequency response of Band-Pass Filter



Fig.4 Frequency response of Band-Reject filter

RESULT: The band pass & band reject filters have been designed for chosen fL, fH and

frequency responses were plotted between voltage gain (in dB) and input frequency.

REVIEW QUESTIONS:

1. A second order band pass filter is to have midband voltage gain of 60. fo. The centre

frequency required is 50 Hz, and Band width must be 10 Hz. Determine the component

values.

2. Design a band pass filter using a single op-amp to meet the following specifications.

Center frequency f0 = 2 KHz, 3db Bandwidth = 400Hz & Q=5.

3. A two-pole band pass filter has a center frequency of 800Hz and a Q of 20.

Determine i) 3db bandwidth ii) 3db frequencies f1 and f2.

4. Design a wide band reject filter having FH = 400Hz and FL=2KHz having pass band

gain as 2. (Let C= C’ = 0.1 µF & R1 ≅ Rf).

5. Design a second order BPF using op-amps, given 2K = 1.414; to pass signals in the band

of 2 kHz to 20 kHz.

WORKSPACE



EXPERIMENT NO: 2

FUNCTION GENERATOR USING IC 741 OP – AMP

AIM: Study of op-Amp as function generator that produces various specific waveforms for

test purpose over a wide range of frequencies.

APPARATUS:

1. Function Generator Trainer kit.

2. C. R.O.



THEORY:

Function generator is a signal generator that produces various specific waveforms for test

purposes over a wide range of frequencies. In laboratory type function generator generally

one of the functions (sine, square & triangle) is generated using dedicated chips or standard

circuits and converts it in to required signal.

This consists of

1. Sine wave generator Using IC 741.

2. Square wave generator (Astable Multivibrator using IC 741)

3. Active integrator using IC 741

SINE WAVE GENERATOR:

Fig.1. Sine wave generator

The sine wave generator circuit is shown in fig.1. The operational amplifier (IC 741) used in

the circuit is provided with a positive feed back through two 47KΩ resistors and a 0.047µF



capacitor. This positive feed back provides a fraction of output signal in phase(00 or 3600)

with the input at the non-inverting terminal (pin No.3) of Op-Amp 741. Once the loop gain

(Aβ) of the circuit equals to 1 the circuit produce oscillates. The frequency of the oscillations

can be controlled by varying the feed back network components. However a negative feed

back is also provided to the Op-Amp 741 to improve the stability of the circuit.

SQUARE WAVE GENERATOR (ASTABLE MULTIVIBRATOR)

In comparison to sine wave oscillations, square wave signals are generated when the Op-Amp

is forced to operate in saturated region. That is the output of the Op-Amp is forced to swing

between +Vsat & -Vsat, resulting in square wave output. The circuit arrangement of a square

wave generator using IC 741 is shown in fig.2.

Figure .2 Square & Triangular Wave Generators

TRIANGULAR WAVE GENERATOR:

The circuit arrangement of a triangular wave generator is shown in Fig.2. A square wave

from the square wave generator is fed to the integrator. The RC time constant of the

integrator has been chosen in such a way that it is very small value compared to the time

period of the incoming square wave. For the basic operation of integrator, it is known that the

output of the integrator for a given square wave input is a triangle wave.

PROCEDURE:

1. Connect trainer kit to the 230V AC mains and switch on the supply.

2. Observe the output of the sine wave generator. If signal is not coming or distorted in shape

adjust the gain trim pot provided on the kit until a good signal is obtained. Measure the signal

frequency using Oscilloscope.

3. Observe the output of the square wave generator and measure the output signal frequency.



4. Observe the output of the Integrator (triangular wave generator) by varying the input signal

frequency (square wave is internally connected to the circuit).

5. Measure the frequency of the triangular wave using CRO.

RESULT: Hence studied op-Amp as function generator that produces Sine, square and

triangular waveforms for test purpose over a wide range of frequencies.



WORKSPACE



EXPERIMENT NO: 3

ASTABLE MULTIVIBRATOR USING 555 TIMER

AIM: To design an Astable Multivibrator using IC 555 timer to generate a square wave of

6.9 KHz with 52.38 % Duty Cycle.

APPARATUS:

6. C.R.O





COMPONENTS:

4. IC 555 Timer : 1 No.

5. Resistors ------ 10 KΩ : 1 No.

1KΩ : 1 No.

6. Capacitor ---- 0.01 µF : 1 No.

0.1 µF : 1 No.

PIN CONFIGURATION OF 555 TIMER:

Fig. 1



CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

Fig. 2

THEORY:

The 555 Timer is used in number of applications; it can be used as monostable, astable

multivibrators, DC to DC converters, digital logic probes, analogy frequency meters, voltage

regulators and time delay circuits. The IC 555 timer is 8-pin IC and it can operate in free-

running (Astable) mode or in one-shot (Monostable) mode. The pin configuration of NE 555

Timer is as shown fig (1). It can produce accurate and highly stable time delays or

oscillations.

Astable Multivibrator often called a free-running Multivibrator. External Trigger

input is not required to operate the 555 as an Astable Configuration. However, the time

during which the output is either high or low is determined by two external components

Resistor & Capacitor. Fig (2) shows the 555 as Astable Multivibrator. Initially, when the

output is high, capacitor C starts charging towards Vcc through resistor Ra and Rb. As soon as

voltage across the capacitor equals to 2/3 Vcc, comparator-1 triggers the flip-flop, and the

output is low. Now capacitor discharges through Rb and transistor Q1. When the voltage

across capacitor C equals to 1/3Vcc, comparator-2’s output triggers the flip-flop, and the

output goes high. Then the cycle repeats. The output voltage waveforms are as shown in fig



(3).In this way capacitor periodically charges and discharges between 2/3Vcc and 1/3Vcc

respectively.

The time during which the capacitor charges from 1/3Vcc to 2/3 Vcc is equal to the

ON time of the timer (i.e. the output is HIGH) and is given by

tc =0.69(R1+R2)C ---- (1)

The time during which the capacitor discharges from 2/3 Vcc to 1/3Vcc is equal to the OFF

time of the timer, during which the output is LOW and is given by

td =0.69(R2)C --- (2)

The total time period of the output is the sum of charging time( tc )and discharging time(td)

and is given by

T = tc + td = 0.69(R1 + 2R2) C --- (3)

Therefore the frequency of oscillations of Astable multivibrator is given by

F = 1/T = 1.45/ (R1 + 2R2) C --- (4)

DUTY CYCLE:

This term is in conjunction with Astable Multivibrator. The duty cycle is the ratio of the ON

time, tc during which the output is high to the total time period T. It is generally expressed as

a percentage.

Duty cycle,D = (TON /TON+ TOFF) = tc /T = (R1 + R2) / (R1 + 2R2) --- (5)

DESIGN:

Step1: Choose C=0.01 µF

Step2: using the formula, F = 1.45/ (R1 + 2R2) C, Get a relation between R1 & R2.

Step3: Consider the expression for duty cycle, D= (TON /TON+ TOFF) = (R1 + R2) / (R1 +2R2)

& obtain a relation between R1 & R2.

Step4: Using the relations between R1 & R2., obtained in step2 & step3, solve for R1 & R2.

PROCEDURE:

1. Connect the IC 555 timer in Astable mode as shown in fig.2

2. Connect the C.R.O at the output terminal (pin 3) and observe the output.

3. Record the waveforms at pin3, across the capacitor & compare them with the

sample output waveforms as shown in fig (3)

4. Measure the charging time (tc), discharging time (td) and total time period/ Frequency from

the output waveform.

5. Calculate tc, td, time period (T), frequency (f) of the square wave output and percentage

duty cycle theoretically.



6. Compare the theoretical values charging time (tc), discharging time (td) ,total time period/

Frequency & % Duty cycle with the practical values.

OBSERVATION TABLE:

S.NO Theoretical Values Practical Values

tc

(m.sec)

td

(m.sec)

T

(m.sec)

f

(in Hz)

D tc

(m.sec)

td

(m.sec)

T

(m.sec)

F

(inHz)

D

EXPECTED WAVEFORMS:

Fig.3

RESULT: Hence designed & studied IC 555 timer as an Astable multivibrator and also

calculated the frequency of oscillations & time period of output waveform.

REVIEW QUESTIONS:

1. List the important features of the IC555 Timer. 2. Define Duty cycle.

2. Consider the Astable multivibrator with R1=10KΩ,R2=200KΩ and C=0.1µF. Determine

a) High state interval b) Low state interval c) Period d) Frequency e) Duty cycle.



3. Design an Astable 555 timer circuit to produce a 2kHz square wave with a duty cycle of

70%. 6. What is the function of control input (pin5) of 555 timer?

4. Compare the time period ‘T’ of the Astable multivibrator using IC555 timer& op-amp

IC741.

5. Why do we connect pin 4 of IC 555 timer to supply pin when it is not used.

WORKSPACE



EXPERIMENT NO: 4

VOLTAGE CONTROLLED OSCILLATOR (IC 566)

AIM: To construct and study the voltage controlled oscillator-using IC 566.

APPARATUS REQUIRED:

1. Function Generator.

2. C.R.O.

3. CDS Board/ Bread Board

4. Connecting Patch chords.


1. IC 566 : 1 No.

2. Resistors --- 1.5KΩ : 1 No.

10KΩ : 1 No

20KΩ : 1No

3. Capacitors --- 0.001µF :1 No

0.1µF :1 No

1µF :1 No

CIRCUIT DIAGRAM:

Fig.1

THOERY:

Fig.1 shows the circuit diagram of VCO. This arrangement R1C1 combination determines the

free running frequency and the control voltage Vc at terminal 5 is sent by the voltage divider

formed with R2 and R3. The initial voltage Vc at terminal is

( ) ( )+ +3

4cc ccV V V

c ------- (1)

Where +V is the total supply voltage.



The modulating signal is ac coupled with the capacitor c and must be less than

3Vp-p.The frequency of the output waveform is given by

( )( )

+ −=

+

2

01 1

cc

cc

V Vc

fR C V

------ (2) Where R1=R2+R3

Fig.2 shows square wave & triangular wave outputs of the Voltage Controlled Oscillator (IC

566) measured at pin no3 & pin no.4 respectively.

PROCEDURE:

1. Connect the circuit as shown in fig.1.

2. Switch on the power supply of 12V DC & observe square wave output at pin no.3 &

triangular wave output at pin no.4.

3. Keep the product of R1 C1 as constant.

4. By varying the control voltage Vc, between ¾(Vcc) and Vcc observe the output frequency.

WAVEFORMS:

Fig.2

RESULT: Voltage controlled oscillator-using IC 566 is constructed and the frequency of

oscillations is estimated. Also observed the variations in the output signal frequency in

accordance with the modulating or control valtage, Vc.



WORKSPACE



EXPERIMENT NO: 5

DIGITAL TO ANALOG (D/A) CONVERTERS

a) WEIGHTED RESISTOR DAC

AIM: To obtain analog output voltages for the digital input data using 4- bit D/A converter

using weighted resistors method.

APPARATUS REQUIRED:

1. 4 – bit D/A converter (weighted resistors) Trainer kit.

2. Multimeter.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect trainer to the mains and switch on the power supply.

2. Measure the power supply voltages in the circuit as +12V & -12V.

3. Calculate V0 theoretically for the digital I/P data using formula.

= − + + +

0 31 2 82 4o f

b bb bV R

R R R R

Use Rf = 1 kΩ & R= 10kΩ.

4. Note down O/P voltages for different combinations of digital inputs and compare it with

theoretical value.

For Example:

When b3 is high and all other inputs are low then the output voltage is

= − + + + =

0 0 0 54

/ 2 / 4 / 8o fV R V

R R R R



TABLE:

Digital Input Data Theoretical (V0) Practical (V0)

b1 b2 b3 b4

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

RESULT: Obtained analog output voltages for the given digital input data using 4- bit

weighted resistor D/A converter.

REVIEW QUESTIONS:

1. How many resistors are required in 12 bit-weighted resisters DAC?

2. Mention different techniques for D/A conversion

3. What is the main disadvantage of weighted resistor DAC over others?

4. A 5-bit D/A converter is available. Assume that ‘00000’ corresponds to an output of 10V

and that the D/A converter is connected for 0.1 V for increment. What output voltage will

be produced for’11111’?

5. Define the terms full-scale voltage and one least-significant bit for a D/A converter.

6. Consider the 4-bit D/A converter with Vr=10V,Rf=10KΩ. Determine



a) Number of possible output levels b) Full scale voltage c) Value of 1 LSB

7. Determine the out put voltage for the following input digital words when 4-bit D/A

converter with Vr=10V, Rf=10KΩ is considered

i) 0001 ii) 0110 iii) 1010

8. Derive Vo of 4-bit D/A converter.

b) R-2R LADDER NETWORK DAC

AIM: To obtain analog output voltages for the digital input data using 4-bit R-2R ladder type

D/A converter.

APPARATUS REQUIRED:

1) 4 – bit D/A converter (R-2R) Trainer Kit.

2) Multimeter.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the trainer to the mains and switch on the power supply.

2. Measure the supply voltages of the circuit as +12V & -12V.

3. Calculate theoretically Vo for all digital Input data using formula.

= − + + +

3 02 10

2 4 8 16f

b bb bV R

R R R R

In this experiment Rf = 1 1kΩ & R= 11kΩ.

4. Note down Output voltages for different combinations of digital inputs and compare it with

theoretical values.

For Example:



When b3 is high and all other inputs are low then the output voltage is

= − + + + = − = −

5 0 0 0 511 2.5

2 4 8 16 2 *11V R K Vo f R R R R K

TABLE:

Digital Input Data Theoretical Value of

the output,V0 (in volts)

Practical Value of the

output,V0 (in volts) b1 b2 b3 b4

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

RESULT: Obtained analog output voltages for the given digital input data using 4- bit R-2R

ladder network D/A converter.

REVIEW QUESTIONS:

1. Consider the 4-bit D/A converter with Vr=10V,Rf=10KΩ. Determine

a) Number of possible output levels b) Full scale voltage

c) Value of 1 LSB



2. Determine the out put voltage for the following input digital words when 4-bit D/A

converter with Vr=10V,Rf=10KΩ is considered

i) 0001 ii) 0110 iii) 1010

WORKSPACE



EXPERIMENT NO: 6

DUAL SLOPE ANALOG TO DIGITAL CONVERTER

AIM: To verify the analog to digital conversion using Dual slope A to D converter.

APPARATUS REQUIRED:

1. Analog to Digital Converter Trainer Kit

2. Power Supply

3. Digital Multimeter


CIRCUIT DIAGRAM:

THEORY:

The most natural occurring phenomenon is analog in nature. With the introduction of

digital devices and computers, it has become necessary to convert the data taken in physical

system to digital form. The data to the digital device, namely appears in analog form:

Ex: a temperature difference would be represented by the voltage output of a thermo

couple, therefore the need arises for a device that converts analog information into digital

form. The process of concerting an analog voltage into an equivalent signal is known as

analog to digital conversion. There are so many methods to achieve this. One of the method

dual slope A/D converter is used. The block diagram of dual slope A/D converter is given in



Fig.1. It has four major blocks Integrator, Comparator, a Binary counter and a Binary to 7

Segment decode & driver.

The conversion process begins at t=0 with the switch S1(assume as it has built in auto

switching) in position 0,there by connecting the analog voltage Va of the integrator. This

result in high Vc, thus enabling the AND gate and the clock pulses reach the clock (ck) input

terminals of the counter which was initially clear. The counter counts from 00…00 to

111…11 when (2-a) clock are applied. At the next clock pulse (2) the counter is cleared and 0

becomes 1.This controls the state of S1 which now moves to position 1 at T1. There by

connecting Vr to the input of the integrator. The output of the integrator now starts to move

in the positive direction. The counter continues to count until Vo=0V. As soon as V0 goes

positive at T2, Vc goes low disabling the AND gate. The counter will stop counting in the

absence of the clock pulses.

The time T1= 2N Tc -------- (1)

Where Tc is the time period of the clock pulses. When the switch is in position 1, the o/p

voltage of the integrator is given by.

( )1 1o a rV V T V t T= = − ----------- (2)

Vo= 0 at t = T2

( ) ( )− = = N

2 1 a r 1 a r cT T V V * T V V *2 T ----------- (3)

Let the count recorded in the counter be ‘n’ at T2

Therefore T2-T1 = n.Tc = ( )N

a r cV V *2 .T ------------------ (4)

which gives ( )=a r

n V V *2 ---------------- (5)

This shows the output of the counter is proportional to the analog voltage Va.

The count recorded in the counter is numerically equal to the analog voltage, If Vr= 2.

PROCEDURE:

1. Connect analog output voltage to input of A/D converter at Va

2. Connect Ref. voltage at VR.

3. Measure the voltages Va and VR with digital multimeter.

4. Now the display will show a reading of

Display = [ Va/VR] *1000

5. Fix the reference voltage at 100 mV

6. Now vary the analog input & note down the readings for different values.

7. Verify the display reading with the theoretical value that will come by using the above

formula.



RESULT: Studied the analog to digital conversion using Dual slope Analog to Digital

converter.

WORKSPACE



EXPERIMENT NO: 7

ADJUSTABLE VOLTAGE REGULATORS USING FIXED VOLTAGE

REGULATORS

AIM:

1) To construct and study the adjustable voltage regulator (10V) using fixed voltage.

regulator IC7805

2) To construct a constant current source using three terminal voltage regulator.

APPARATUS REQUIRED:

1. Digital Multimeter

2. Regulated DC Power supply

3. Breadboard / CDS Board

4. Connecting wires


1. Capacitors –-- 0.33µF :1 No.

2. IC 7805 :1 No

3. Resistors ---- 10 Ω : 2 No.

CIRCUIT DIAGRAM:

Fig.1 Constant Current Source using IC 7805

THEORY

In the laboratory, one may need variable regulated voltages or a voltage that is not available

as standard fixed voltage regulator. This can be achieved by using a fixed three terminal

regulator as shown in Fig .1. Note that the ground (GND) terminal of the fixed three terminal

regulator is floating. The output voltage

Vo = VR + VL ________________ (1)

= VR + ( IQ + IL) RL ______________ (2)

= VR + IQ RL + VRRL/ R ____________ (3)



Or

Vo = (1+ RL / R) VR + RL IQ ________ (4)

Therefore Vo=(1+ RL / R) VR ------------ (5) (Since IQ is negligible )

Where VR is the regulated voltage difference between the OUT and GND terminals. The

effect of IQ is minimized by choosing RL small enough & the term IQ R2 can be neglected.

The minimum output voltage is the value of the fixed voltage available from the regulator.

The LM117, 217,317, IC78XX positive regulators and LM137, 237,337, IC 79XX negative

regulators have been specially designed to be used for obtaining adjustable output voltages. It

is possible to adjust output voltage from 1.2V to 40V and current up to 1.5 A. Adjustable

voltage regulators provided the answers to the excessive inventory and production costs

because a single device satisfies many voltages requirements from 1.2 up to 57 V. In

addition, they have the following performance and reliability advantages over the fixed types.

• Improved system performance by having line and load regulation of a factor of 10 or

better.

• Improved overload protection allows greater output current over operating

temperature range.

• Improved system reliability with each device being subjected to 100% thermal limit

burn-in.

Thus, adjustable voltage regulators have become more popular because of versatility,

performance, and reliability. The IC 78XX & LM317 series are the most commonly used

general –purpose adjustable positive voltage regulators. IC 79XX and LM 337 series are the

most commonly used adjustable negative voltage regulators.

PROCEDURE:


2. Apply the unregulated voltage to the IC 7805 and note down the regulator output voltage,

vary input voltage from 12V to 30V and record the output voltages.

3. Vary the load resistance in steps (by keeping i/p voltage constant) & measure the regulator

output.

4. Calculate the load current in the circuit by varying the input voltage & load Resistance in

steps.

5. Calculate the line regulation & load regulation of the regulator using the formulae

Line Regulation = ΔVO / ΔVi

Line Regulation = ΔVO / ΔIL



6. Plot the curve between unregulated input voltage and the regulated output voltage &

compare it with the expected wave form shown in Fig.2.

OBSERVATION TABLES:







EXPECTED WAVE FORMS :

a. Line Regulation

b. Load Regulation

Fig.2 Line & Load Regulation curves



RESULT: Hence constructed and studied the adjustable voltage regulator (10V) & constant

current source using fixed voltage regulator IC7805 .

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department of electronics and communication …aim: to study the pin configurations, specifications...

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