1

Peter Nilsson

Digital IC-Design

Peter Nilsson

Professor

Digital ASIC GroupDigital ASIC Group

Department of Electrical and Information Technology

Digital ASIC Group

Department of Electrical and Information Technology

Circuits & Systems

Electromagnetic Theory

Broadband Communications

Mixed Mode

Digital ASIC

Signal Processing

Networking & Security

Communication Analog/RF

1 Professor1 Associate Professor1 Assistant Professor

Research in Digital ASIC

1 Assistant Professor1 Adjunct ResearcherSystem

Algorithm

Architecture

Arithmetic

8 PhD Students

Arithmetic

Logic/Layout

Digital IC-Design

Course Information

www.eit.lth.se

www.eit.lth.se/course/eti130

2

Digital IC DesignImportant locations

Silicon LabBlåtunga & Rödnäbba

E:2435

Seminars

Stefan MolundCAD-toolsE:2334

E:2311

Student Expedition(”Studieexpedition”)

Second floor

Park

ing

Peter NilssonCourse Manager

E:2337

LecturesE:C

In BasementN

Examination

Three laboratory worksWritten examination 2010

Thursday October 21, 2010, 14.00 - 18.00 in MA9 C - FTextbook and calculator are allowedNext time is in January 11, 2011, 14.00-18.00, in E:2311

Digital IC Design (or Analog IC Design) is a prerequisite to IC-project

& Verification, in period 2.

Digital IC-Design

Lectures E:C

Seminars & Exercises E:2311

Laboratory work E:2435BlåtungaRödnäbba

Tuesdays at 10.15-12.00

Digital IC-Design - Lectures

Tuesdays at 10.15 12.00

Wednesdays at 13.15-15.00

E:CIn the Basement

3

Thursday 16/9 at 13.15-17.00Thursday 16/9 at 18.15-22.00 Monday 20/9 at 08.15-12.00

Digital IC-Design - First Lab Work

E:2435Blåtunga Rödnäbba

Note that they are equal so you should only take one

Sign up at the course web page

Rödnäbba

p g

Print and read the lab manual,solve the preparation problems

before the lab

Thursday 9/9 at 10.15-12.00

Digital IC-Design – First Seminar

That is, next week

E:2311

Digital IC-Design

Chapter 1Introduction

What is Digital IC Design about?

Design, and optimization of digital circuitsFocus on CMOSFocus on CMOS

Important metrics

Speed pPower consumptionReliabilityArea

4

Introduction to digital integrated circuits

CMOS devices

What is Digital IC Design about?

CMOS devicesManufacturing technologyCMOS inverters and gatesPropagation delayNoise marginsPower dissipationS ti l i itSequential circuitsArithmetic InterconnectMemories

History: The First “Computer”

The Babbage The Babbage Difference Engine from 1832

25 000 25,000 parts

ENIAC - The first electronic computer (1946)

19000 vacuum tubes

The Transistor Revolution

The first transistorBell Labs, Bell Labs, 1948 by Shockley

The Nobel Prize in Physics 1956

5

The Nobel Prize in Physics 2000

Jack Killby – 1958

The first integrated circuit (oscillator)1 active and 4 passive components on a piece of germanium

12 mm

The First Integrated Circuits

Transistors

Bipolar logic

From 1960’s

3-input ECL GateMotorola 1966

The MOS-transistor: An old invention

Julius Edgar Lilienfeld showed the first MOSFET-structure in 1925 - U.S. Patent 1930

In parallel, Oskar Heil described a similar structure in early 1930’s - British Patent 1935

None of them made a working component

The first working MOS-transistor was shown in the beginning of the 1960’s

The First Micro-Processor: Intel 4004

1971

1000 transistors

1 MHz operation

6

Intel Pentium IV Microprocessor

2000

42 Million

Transistors

Processor Evolution

Number of transistors over 30 years

19992000

1989

1985

1982

1997

1993Pentium 4 processor

42 000 000 Transistors486-processor

1 200 000 Transistors

Source: Intel

19711972

1978

1974

40 Millions30 Millions20 Millions10 Millions

4004

2 000 Transistors

Where are we 1016?

[nm]Vi

Channel length decrease by 7Oxide thickness

Technology100

10

1

9nm

[ ]Virus

ProteinMolecule

DNA

decrease by 5

Thickness of a few atoms

Oxide thickness OxidMetal

Halvledare(semiconductor)

2001 2003 2005 2007 2010 201620130.1

1

Atom

Molecule

0.4nm

Source: ITRS 2002 Update (High performance logic technology)

Example: 30 nm Transistor

Gate

p-

n+ n+

DrainSource

substratSource: Intel

7

In 1965, Gordon Moore predicted the increase of transistors on a chip

Moore’s Law

Gordon Moore

The prediction is still valid

Moore’s law was formulated in 1965

”The complexity for minimum component minimum component costs has increased at a rate of roughly a factor of two per year”

”… no reason to believe it will not remain nearly constant for at least 10 constant for at least 10 years”

Source: Electronics, Volume 38, Number 8, 19 April 1965

Moore’s law until 2016?

Brake point 2001Milion transistors

1000

10000

6 Billion transistors

How does that

Dubbling every1.5 year

Dubbling every3 year

0.1

1

10

100

1000

Source: ITRS 2002 Update

How does that affect the power consumption?

1971

1974

1977

1980

1983

1986

1989

1992

1995

1998

2001

2004

2007

2010

2013

2016

0.1

0.001

0.01

High performance:

Total power per function

How about Power Consumption?

P [W]300

Low power: Doubling

over 15 years

High performance:

Doubling over 15 years

Idag, 150W

2016,290W

300

100

200

158W

Today,

Source: ITRS 2002 Update

Standby: Constant over

15 years

2001 2003 2005 2007 2010 201620130

100

3W

8

25

Moore’s lag: Total power?

100 W today

25 kW the year

10

15

20

25P

(kW

)

25 kW per chip!!!

25 kW the year2020

2008 2010 2012 2014 2016 2018 20200

5

P

ÅrYear

Cost of Integrated Circuits

NRE (Non-Recurrent Engineering) costs- Design time and mask generationDesign time and mask generation- One-time cost factor

Recurrent costs- Silicon manufacturing, packaging, testing- Proportional to volumeProportional to volume- Proportional to chip area

Manufacturing Costs

Initial cost is increasingWafer cost is constant

3030

15

22.5

Cost Ratio Mask

Cost

Around 40 masks are

used

0.5 0.180.250.35

7.5

Feature size [micron]

Wafer Cost

usedtoday

Continuous Scaling –> New Methods

Each generation can integrate 2x more functions per chipCost of a function decreases by 2xCost of a function decreases by 2x

However- How can we design chips with more and

more functions?- Design engineering population does not

increase with 2x

Need for more efficient design methods- Engineers must exploit different levels of

abstraction - SoC

9

Design Abstraction Levels

System

Module

VDD

Module

Gate

Circuit

ADD

SUB

Engineers must exploit different levels of abstraction

Device

Integrated Circuit (IC)

IC

Standard - IC ASICApplication Specific IC

Low Cost

Proven (reliable)

High Performance

Low Power

Off-the-Shelf Available

Many Sources

Replace many IC:s

IC

Integrated Circuit (IC)

Standard - IC ASICApplication Specific IC

Semicustom

Some parts are pre-made

All transistors and connections

are designed

Full Custom

Integrated Circuit (IC)

Semicustom

Pre-wired

P diff d

Standard cell

M ll

Cell based Gate Arrays

AND, NAND, MUX, ADDER

etc.

Pre-diffusedMacro cell

Multiplier, RAM, etc.

Pre-made transistors

FPGA(Programmable)

10

An IC: a lot of MOS-transistors

MOS = Metal Oxide Semiconductor

Polysilicon

SiO2

Polysilicon

Silicon, doped

OxideMetal

Semiconductor

Manufacturing: A Lithographic Process

Photographic glass plate (mask)

Each layer is projected to the silicon die

Intel use 30cm

Wafer consisting of many dies

(chips)

te use 30cwafers in 90nm

technology,“Pizza wafers”

Mask

For us: MPW (Multi Project Wafer) to keep the costs down

Several prototypes on the prototypes on the same reticule

Manufacturing

Each mask is repeated with a stepper

Reticule

Identical dies for large volume designs

Silicon dies (chips) after die

i sawing

11

Yield

Number of good chips 100%Total number of chips

Yield = ×

Reticule There are always defect dies

The yield is a quality measure

Defect die

quality measure

Some Examples (1994)

Chip Line width

Wafer cost

Area mm2

Dies/wafer

Yield Die cost

386DX 0.90 $900 43 360 71% $4

486 DX2 0.80 $1200 81 181 54% $12

HP PA 7100 0.80 $1300 196 66 27% $73

DEC Alpha 0.70 $1500 234 53 19% $149

Super Sparc 0.70 $1700 256 48 13% $272

Factor100

Pentium 0.80 $1500 296 40 9% $417

Low yield – high cost

N-MOS Transistor

DrainSourceGate

Bulk Silicon St t

p-

p+ n+ n+p+

ThinOxide

Structure

Each box in the layout represents a mask or a step in the process

Mask Layout

Example: CMOS Technologies

Thin oxide

only a few atom layers

Source: Intel

12

P-MOS Transistor

DrainSourceGate

Bulk Technologies

N Well

p-

p+ p+ p+n+

N-Well

n-

N-Well

P-Well

Twin-Tub

The minimum The minimum drawn gate length sets the name of the technology

CMOS - Complementary MOS

A technology with both NMOS and PMOS transistors

p-

OUTVDD

n+ n+ p+ p+

n-

GND ININ PMOSNMOS

Lightly doped p-substrate

Lightly doped n-well

Fabrication Flow

Layout

Mask Generation

Input from us

Silicon fabricationMask Generation

Sili Di

Die Sawing

Fabrication

e.g AMS & Alcatel

Deep Submicron:Intel, IBM, TSMCand UMC (80% inTaiwan)

Silicon Dies

Packaging

Chips Back to us

Design Rules

Masks are lithographic glass plates used in the fabrication process

The fabrication process have limitations in accuracy

The design rules specify the geometry of masks which give a reasonable yield

The design rules are determined by experience

Yield = Relative number of working chips

13

Example: Design Rules Examples from a 0.35 micron technology

Metal 1 DiffusionPoly

Tool:

DRC (Design Rule Checker)

A th T l

0.6

0.4

0.6

0.3

0.6

0.5

Another Tool:ERC (Electr. Rule Checker)

0.40.3

0.10.4

0.2

0.1

0.4

0.4

Layout styles

VDD

A B

NANDf ANDfA

VddVdd Vdd

B

GND

VddVdd

PMOSANDNAND

PMOS

AGND

B

ANDNAND

NMOSA

GND

B NMOS

GND

Two Input AND-NAND

AND

VddVdd

NAND

PMOS

NMOS

0.8 μmCMOS

AGND

B

CMOS

NAND Inverter

Circuit Representation

Layouty- Boxes, graphical or coordinate based list- Abstract (subset)

Schematic- graphical or component based netlist

Symboly- For simulation and hierarchical schematics

14

Circuit views - layout

(CIF file 11-Mar-2003);DS 1 1 1

PhysicalText based (0.35um tech.)

DS 1 1 1;9 INVERTER;L prBoundary;B 450 1500 225,750;L CONT;B 40 40 100,340;L DIFF; B 100 240 320,420;L POLY1;B 80 35 190,425;

Cell name

Cell size

Box

Layer

Symbolic

B 80 35 190,425;L MET1;B 60 360 70,800;B 450 200 225,100;

Layer

Length Width Xcenter,Ycenter

Abstract view

VDD

A QB

Physicalcell size

Terminalswith physicalplacement

GND

Extracted from physical layout to be used in “place & route”

Schematic/Netlist

VDD

fNAND

A

A

B

B

*nand gate* d g s bM1 2 1 0 0 NMOS L=0.35U W=0.6UM2 4 3 2 0 NMOS L=0.35U W=0.6UM3 4 3 5 5 PMOS L=0.35U W=0.9UM4 4 1 5 5 PMOS L=0.35U W=0.9UC1 3 0 1E-14

GND

Circuit Chart Schematic view (Graphical netlist)

Netlist (List based schematic)

Symbol View

Gate based on schematics

For simulation & hierarchical schematics

Capacitor (load)

Signal source

15

Simulation

When do you perform simulation ?

Before layoutBefore layout- To check if there is are logic errors in the circuit

- To estimate timing

After layout- To check if there where mistakes when translating the

i it i t l tcircuit into layout

- To check if the layout parasitics change the behavior of the circuit

Simulation Models

Circuit simulation

- Based on transistorsBased on transistors

Timing simulation

- Less accurate but faster transistor model

Switch simulation

- Treat transistors as ideal switches

Gate (logic) simulation

- Based on logic gates

Simulation Models

Switch Model

Circuit Model

Timing Model

Often used when simulating HDL code

Cell(INVERTERcPin(A Pintype(Data) Pindir(Input))Pin(Q Pintype(Data) Pindir(Output))Function(!(A)))

Model(DelayA01Q10 ModelS (Spline (( 0.15 0.23 0.4 0.73 1.4 )( 0.29 0.41 0.59 0.92 1.58 )( 0.38 0.52 0.76 1.13 1.79 )( 0 49 0 69 0 99 1 48 2 22 )

CL

{0,1,x} Based on physical model

( 0.49 0.69 0.99 1.48 2.22 ))))Model(DelayA10Q01 ModelS (Spline (

( 0.14 0.23 0.4 0.75 1.43 )( 0.25 0.36 0.53 0.87 1.55 )( 0.33 0.46 0.68 1.03 1.7 )( 0.43 0.6 0.86 1.31 2.02 )

))))

Simulation Models - Timing

Switch Model

RC based Switch Model

Circuit Model

CL

Ron-p

CL

Model

Ron-n

td = 0 or unit td = 2.2 RonCLtd = CL/knVdd

16

Design Flow

Simulation

Schematic

Extraction

DRC

Layout

DRC = Design Rule Checker

LVS

Post Lay Mod

LVS = Layout Versus Schematic

MOS Circuit Structures

VDD VDDVGS

ll

PUN

VDD

Pull-Up Net

VDD VDD

VOut-Max =VDD-VT

VDD

VGS

GND GND

StaticCMOS

Pull-Down Net

GND

PDN

N-channel have a good connection to GND

P-channel have a good connection to VDD

GND GND

Out Max DD T

GND

CMOS

Important Dimensions

Gate

Source Drain

L and W are design parameters

tox

L

WSource

A wide (W) transistor is able to drive high currents

A long (L) transistor have less L

The technology is named after the

gate length L

driving capability

Digital IC-Design

Chapter 1Introduction

cont.

17

Web Page

htt // it lth / / ti130http://www.eit.lth.se/course/eti130

Sign up should work now

If you got your Stil accounty g y

Courses for IC Project, Fall Period 2

Note:At least 2 courses are needed for the IC ProjectDigital IC is needed for Advanced Digital ICDigital IC is needed for Advanced Digital ICAnalog IC is needed for Integrated Radio

IC Project and Verification, HT2Digital VLSI

Project

RISC Processor

VLSI Project

Analog/Mixed

Signal Project

DigitalIC Design

Computer Architecture

Intro. to Struct. VLSI

AnalogIC Design

DigitalIC Design

Intro. to Struct. VLSI

DigitalIC Design

Recommended

Recommendation

RISC processor VLSI project:

Read Digital IC design, as well, if you would like to

take Advanced Digital IC Design next spring

That is, Read three courses this study period

IC Project and Verification, HT2Digital VLSI

Project

DigitalIC Design

Computer Architecture

Intro. to Struct. VLSI

AnalogIC Design

RISC Processor

VLSI Project

Analog/Mixed

Signal Project

DigitalIC Design

Intro. to Struct. VLSI

DigitalIC Design

Recommended

Parallel-Serial Transistors

W 3WVDD

L 3L==GND

Pull Up Network (PUN) ⇒ Driving Capability × 3

Pull Down Network (PDN) ⇒ Driving Capability × 1/3

18

Large MOS Transistors

Increases the driving capability

Several contacts give low R

Increases the driving capability

Finger FoldedCircular

Circular Transistors (Buffer)

p-channel

D

G

S

n-channel

S

Metal 1

Folded Transistor

Folded Transistor

Pad Surface

Bond Wire

Cell Library – Reuse of the same block

Basic functions are organized in cells such as Inverter, Buffer, AND, NAND, Adder, Register, Counter, Shifter etc.Counter, Shifter etc.

The cells perform bit-wise operations.

A five bit adder is thus made by five adder cells:

a0 b0 a1 b1 a2 b2 a3 b3 a4 b4

FAFA FA

s0 s1 s2

FA

s3

FA

s4

FA = Full Adder

19

Cells in a Bit-sliced Layout

R i C llRegister Cells

XOR Cells

Adder cellsAdder cells

Place & Route (2-3 Metal Layers)

Placement of library cells Routing cell

Routing

Tools:

- Placer

- Router

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

gchannel

Routing

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

LeafCell

Leaf Leaf Leaf Leaf Leaf Leaf Leaf

Place & Route (3-10 Metal Layers) No Routing channels needed

VDD

Placement of library cells Routing

Leaf Leaf Leaf Leaf Leaf Leaf Leaf

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Cell CellCell CellCell Cell Cell

GND

VDD

Upside-down

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Cell CellCell CellCellCell Cell

GND

VDD

Upside-down

Filler Cell

Filler Cells in a Typical 0.13 um Tech.

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell Leaf

Cell

Leaf Cell Leaf CellLeaf

CellLeaf Cell

Leaf Cell

VDD

Leaf Cell

VDD

Decoupling C capacitance when there is space left

20

Standard Cell – Routing

Cell-structurehidden underinterconnect

layers

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Standard Cells and Macro Cells

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Macro Cell

Macro cells are used for regular structures like

RAM:s and sometimes

lti li

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell e.g. Memory

multipliers

Power rings are often used on large cells

SoC – A Question of Reuse

Reused Architecture

Custom block in Radio

Embedded RAML

eaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf C

Leaf Cell

Leaf C

Leaf C

Leaf C

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf C

Leaf Cell

Leaf C

Leaf C

Leaf C

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Acelerator

Macro Cell

block in Standard

Cell

Analog IP-Block Analog

Radio Baseband

RAMPLL DA

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

ell

ell

ell

ell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf Cell

Leaf CellLeaf Cell

ell

ell

ell

ell

ARM Processor

RAM

Macro Cell

IP BlockIP-Block

Digital IP-Block

IP = Intellectual Propertyi.e. a block that designed and put on to the market

DA

In 1965, Gordon Moore predicted the increase of transistors on a chip

Why System-on-Chip: Moore’s Law

Gordon Moore

The prediction is still validTo be able to handle the enormous number of transistors, we need a new design methodology:

System-on-Chip

21

SynthesisSystem-on-Chip

Why SoC: Design Methodology

Schematics

Layout

DesignCompilers

Layout

Synthesis

Layout

Analog

ProcessorCore

MEMS?

20KGates

3μ 0.18μ0.5μ1μ

50KGates

3 MillionGates

500KGates

( MEMS = Micro Electro Mechanical Systems )

Modules(FFT DSP

System-on-Chip(Single chip Radio)

Example: Designs at EIT Department

Gates, Cells(And, Adder,

Mult etc.)

Modules(Filter Mpeg

DSP etc.)

(FFT, DSP,uProc. etc.) PLL

Radio Baseband

RF ADC20K

Gates

3μ 0.18μ0.5μ1μ

50KGates

3 MillionGates

500KGates

Why SoC: Design Gap

System-on-Chip(Design Reuse, IP Reuse,

Platform based design etc )

Gates

10M

Synthesised

DesignerCapability

Moore's Law

Platform based design etc.)

20101970 1980 1990 2000

10

10K

YearSchematic

y

Why SoC: New Design Paradigm

S ft

Hardware

Software

ASIC CPU

Software OS

Software

Communication

CPU

Analog

Digital

Analog

AD/DA

RF

AD/DA

MEMS

AD/DA

22

Reuse comes in Generations

G ti R l t St tGeneration Reuse element Status1st Standard cells Well established

2nd IP blocks Being introduced

3rd Architecture Emerging

4th IC Early Research4th IC Early Research

Source: Theo Claasen

Standard Cell & Macro Cell

”Automatic” often flat

Structured, hierarchical

FFT

Graphic Processor

Set-Top Box – A SoC

Macro Cell(standard

Macro CellMemory

Synthesized

cell based)

Processor IP-block

IP-blocks

Synthesizedstandard

cellsAnalog-IP

blocks

Source: Broadcom

Untimed

Algorithm(floating point)

Algorithm(fixed point)

Trade-offBit Error Rate

Verilog

Algorithm to ASIC Flow

G

BehavioralLevel

C &

ArchitecturalLevel

VHDL/VerilogVHDLVerilog

BehavioralSynthesis

Architectural

Synthesis

Circuit &

Clocked

GateLevel

Circuit & LayoutLevel

Layout

ToSilicon

ToFPGA

VDD

23

Conclusion

A chip is not a chaotic collection of billions of transistorsbillions of transistors

It is a structured hierarchical system built of modules

I hope that we can show that in this course