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E. Pop 1 Power Dissipation in Nanoscale CMOS and Carbon Nanotubes Eric Pop Dept. of Electrical & Computer Engineering http://poplab.ece.uiuc.edu E. Pop 2 Power and Heat: The Big Picture 1 10 100 1000 1990 1994 1998 2002 2006 2010 AMD Intel Power PC Trend Power Density (W/cm 2 ) Hot Plate Rocket Nozzle Nuclear Reactor Sun surface? 6000 W/cm 2 http://phys.ncku.edu.tw/~htsu/humor/fry_egg.html

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Page 1: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 1

Power Dissipation in Nanoscale CMOS and Carbon Nanotubes

Eric Pop

Dept. of Electrical & Computer Engineering

http://poplab.ece.uiuc.edu

E. Pop 2

Power and Heat: The Big Picture

1

10

100

1000

1990 1994 1998 2002 2006 2010

Po

wer

Den

sit

y (

W/c

m2)

AMD

Intel

Power PC

Trend

Pow

er

Density (

W/c

m2)

Hot Plate

Rocket Nozzle

Nuclear Reactor

Sun surface? 6000 W/cm2

http://phys.ncku.edu.tw/~htsu/humor/fry_egg.html

Page 2: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop

• IBM S/390 refrigeration

• Grid computing: power plants co-located near computer farms

3

Thermal Management Challenges

E. Pop 4

Power and Heat: The Tiny Picture

Carbon nanotubes burn at high enough applied voltage

(they also emit light when they get this hot)

Suspended On substrate

Page 3: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 5

Power, Thermal Management Methods

System Level Active Microchannel Cooling (Cooligy)

Circuit + Software Level active power management(turn parts of circuit on/off)

IBMIs there a bottom-up approach?

From the device and materials level?

E. Pop 6

Chip-Level Thermal Network

Intel 65 nm

Ttransistors

Rconvection

Ctransistor

Cchip

Cheat sink

Tchip

Rchip

Theat sink

Cinterconnect

Tinterconnect

Tcoolant

heat spreader

Si chip

chip carrier

fan

fin array heat sink

heat spreader

Si chip

chip carrier

fan

fin array heat sink

Rdielectric

Rspreading

Top viewHottest spots > 300 W/cm2

Intel Itanium

Cross-section8 metal levels + ILD

Transistor < 100 nm

Page 4: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 7

Thermal and Electrical Resistance

Ohm’s Law (1827)Fourier’s Law (1822)

∆ V = I × R∆T = P × RTH

P = I2 × R

R = f(∆T)

E. Pop 8

Device-Level Thermal Challenges

1.4SiO2

13Si (10 nm)

40Silicides

60Ge

148Si

k (W/m/K)Material

Device Level:

Confined Geometries, Novel Materials• Small geometry

– High power density (device-level

hot spot)

– Higher surface-to-volume ratio, i.e.

higher role of thermal interfaces

between materials

• Lower thermal conductivity

• Lowering power (but can it

ever be low enough?!)

• Device-level thermal design

(phonon engineering)

Source: E. Pop (Proc. IEEE 2006)

Page 5: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 9

0.1

1

10

100

1000

10000

100000

0.01 0.1 1 10L (mm)

RTH (

K/m

W)

Thermal Resistance of a Single Device

GST

Cu

Si Bulk FET

Cu Via

Phase-change Memory (PCM)

Single-wall nanotube SWNT

Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006).

SiO2

Silicon-on-Insulator FET

L ~ channel length

or via diameter

High thermal resistances:

• SWNT due to small thermal

conductance (very small d ~ 2 nm)

• Others due to low thermal

conductivity, decreasing dimensions,

increased role of interfaces

Power input also matters:

• SWNT ~ 0.01-0.1 mW

• Others ~ 0.1-1 mW

E. Pop 10

Modeling Device Thermal Resistance

• Steady-state models

– Lumped: Mautry (1990), Goodson-Su

(1994-5), Pop (2004), Darwish (2005)

– Finite-Element models

1/ 2

1

2

BOXTH

BOX Si Si

tR

W k k t

1 1

2 4TH

Si Si

Rk D k LW

L W

D

tBOX

tSi

Bulk Si FET SOI FET

0.1

1

10

100

1000

10000

100000

0.01 0.1 1 10L (mm)

RTH (

K/m

W)

SOI FET

Bulk FET

Page 6: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 11

A More Detailed Look

3. Self-heating and lessons

from carbon nanotubes

2. Self-heating in thin-body

SOI and GOI devices

1. Monte Carlo heat generation

in bulk and strained silicon

Silicon substrate

Gate

Buried oxide

2 μmnanotube on

substrate suspended

over trench

E. Pop

)](exp[),( tiit rkAru

transversesmall k

transversemax k=2p/a

k

Graphene Phonons [100]

200 meV

160 meV

100 meV

26 meV =

300 K

Fre

qu

en

cy ω

(cm

-1)

12

Quick Recap of Phonons

• Phonons = lattice vibration waves

• Phonons are responsible for heat transport in semiconductors

• “Hot phonons” = highly occupied modes above room temperature

CO2 moleculevibrations

silicon

Page 7: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 13

Fre

q (

Hz)

En

erg

y (m

eV

)Details Picture of Joule Heating

High ElectricField

Hot Electrons(Energy E)

Heat Conductionto Package

t ~ 1 ms – 1 s

Wave vector qa/2p

E < 50 meV

Acoustic Phonons

t ~ 0.1ps

acoustic

(vac ~ 9000 m/s)

10

20

30

40

50

60

Optical Phonons

t ~ 5 ps

t ~ 0.1ps

E > 50 meV

optical(vop ~ 1000 m/s)

Note: optical phonon energy

in CNTs (180 meV) about 3x

higher than in Si (60 meV)

E. Pop 14

2D Thin-Body SOI Simulation

Me

sh

Cu

rre

nt

E-f

ield

Study of device matching

LG = 18 nm ITRS specs

Monte Carlo (MONET)

if W/L = 4 then Nelec ~ 2500 total!

E. Pop et al., Proc. IEEE, 2006

Notice heat is dissipated

in device drain

Page 8: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 15

L=500 nm 20 nm100 nm

• Monte Carlo vs. Medici (drift-diffusion commercial code):

– “Long” (500 nm) device: same current, potential, nearly identical

– Importance of non-local transport in short devices

– Heat dissipation in DRAIN (optical, acoustic) of shortest devices

Heat Gen. (eV/cm3/s)

DLMonte Carlo

Medici

Error: DL/L = 0.10 DL/L = 0.38 DL/L = 0.80

Monte CarloMedici

source channel drainsource channel drainsource channel drain

E. Pop et al., SISPAD 2005

Heat Generation in Quasi-Ballistic Devices

E. Pop 16

Phonon Generation Spectrum in Silicon

• Complete spectral information on phonon generation rates

• Note: effect of scattering selection rules (less f-scat in strained Si)

• Note: same heat generation at high-field in Si and strained Si

E. Pop et al., Appl. Phys. Lett. 86, 082101 (2005)

Page 9: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 17

ThermalConductivity

Design andScaling

Monte CarloAnalysis

What About Device Design?

E. Pop 18

Thin Film Thermal Conductivity

Intel DST/SOI Transistor

• Phonon boundary scattering and confinement

• Strong decrease in thin film or nanowire thermal conductivity (k), up to

10-100x lower than bulk

• How does this affect nanometer scale devices?

E. Pop et al., Proc. IEDM 2003-2004

0

10

20

30

40

50

60

70

80

0 50 100 150d (nm)

k (

W/m

/K) Thin Si

SiGe NW

Si NW

Thin Ge

Bulk Si ~ 150, Ge ~ 60 W/m/K

Page 10: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop

Boundary Thermal Resistance

19

• Thermal interface resistance at solid-solid material interfaces

• Caused by phonon dispersion mismatch b/w materials (~Cv/4), electron-

phonon energy conversion at boundary, roughness at boundary

• Approximately equivalent to ~10-100 nm additional SiO2

Al/SiO2/Si

GST/ZnS/SiO2

Intel DST/SOI Transistor

E. Pop et al., Proc. IEEE (2006)

Lyeo, Cahill(2006)

E. Pop 20

Self-Consistent Electro-Thermal Model

ntdd VVI m~

4.1T

mV/K7.0

Geometry

R

C

P=VI

T=PR

P=VI I

t=CV/I

p //1ln2 oxexswex tLC

cosdQexxd RRRRR (RQ due to heat source position)

E. Pop et al., Proc. IEDM 2004

Page 11: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 21

SOI/GOI Device Design Optimization

• Larger Source/Drain (S/D) volume will help heat spreading in drain

• BUT… no improvement for S/D thickness tSD > 3-4 x tfilm = Effect of

parasitic side-wall capacitance on Intrinsic Delay

• Optimized, “well-behaved” GOI devices 30% faster than optimized SOI

Intr

insic

Dela

y (

ps)

Gate Length Lg (nm)

tSD = ntfilm

n = 1... 5

CV/I

tfilm

tSD

Lex

E. Pop et al., Proc. IEDM 2004

E. Pop

Transient Device Thermal Modeling

• Compact thermal device model including:

– Non-equilibrium heat generation from Monte Carlo

– Phonon relaxation parameter-matched to Boltzmann Transport Eq.

• Capture spatial and temporal temperature excursions

• What is the effect on leakage & reliability?

22

Z.-Y. Ong and E. Pop, submitted (2008)

0 20 40 60 80 100

72 nm

315 nm

1633 nm

100 nm900 nm

Silicon Dioxide

Silicon

Heat Generation

0 50 100 150 20020

30

40

50

60

70

Time elapsed (ps)

TL in

ce

nte

r o

f h

ots

po

t (K

)

Fourier (ton

=5.04ps)

TTM (ton

=2.52ps)

Fourier (ton

=2.52ps)

TTM (ton

=5.04ps)

Temperature Swings

ITRS 2014device specs

0 50 100 150 2002

3

4

5

6

7

8

9

Time elapsed (ps)

(T

L)

TTM (Steady)

Fourier (Pulsed)

Fourier (Steady)

TTM (Pulsed)

Re

lative

Le

aka

ge

Page 12: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 23

0.1

1

10

100

1000

10000

100000

0.01 0.1 1 10L (mm)

RTH (

K/m

W)

Onto Carbon Nanotubes…

Single-wall nanotube SWNT

Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006).

SiO2

Silicon-on-Insulator FET

E. Pop

Where Carbon Nanotubes Fit In

24

Allotropes of Carbon:

Diamond

Buckyball(C60)

Amorphous(soot)

Graphite (pencil lead)

Single-Walled Nanotube

Page 13: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 25

• Carbon nanotube = rolled up graphene sheet

• Great electrical properties

– Semiconducting Transistors

– Metallic Interconnects

– Electrical Conductivity σ ≈ 100 x σCu

– Thermal Conductivity k ≈ kdiamond ≈ 5 x kCu

back gate

(p++ Si)

HfO2

S (Pd) D (Pd)

SiO2

top gate (Al) CNT

Carbon Nanotubes for Electronics

d ~ 1-3 nm

• Nanotube challenges:

– Reproducible growth

– Control of electrical and thermal properties

– Going “from one to a billion”

E. Pop 26

Nanotube Back-of-the-Envelope Estimates

• Typical L ~ 2 mm, d ~ 2 nm

• On insulating solid substrate

• Heat dissipated into substrate

– Moderate power ~ 10 mW/mm

– Peak DT ~ 60 K

SiO2

kDT

Pt

• Thermal conductivity k ~ 3000 W/m/K

• Freely suspended nanotube

• Heat dissipated along tube length

– Moderate power ~ 10 mW (10 mA @ 1 V)

– Peak DT ~ 400 K!

g

DT

Pt

SiO2

Page 14: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 27

Transport in Suspended NanotubesE. Pop et al., Phys. Rev. Lett. 95, 155505 (2005)

SiO2

Si3N4

nanotube Pt

Pt gate

2 μmnanotube on

substrate suspended

over trench

• Observation: significant current degradation and negative

differential conductance at high bias in suspended tubes

• Question: Why? Answer: Tube gets HOT (how?)

E. Pop 28

1

, ,

1 1 1eff

AC OP ems OP abs

Include OP absorption:

Transport Model Including Hot Phonons

),(

),(

4),(

2 TV

TVL

q

hRTVR

eff

eff

C

0( )OP AC ACT T T T

Non-equilibrium OP:

T0

TAC = TL

TOP

RTH

ROP

I2(R-Rc)

0 0.2 0.4 0.6 0.8 1 1.2

300

400

500

600

700

800

900

1000

V (V)

Ph

on

on

Te

mp

era

ture

(K

)

oxidation T

Optical TOP

Acoustic TAC

I2(R-RC)

TOP

TAC = TL

2( ) ( ) / 0CA k T I R R L

Heat transfer via AC:

Landauer electrical resistance

E. Pop et al., Phys. Rev. Lett. 95, 155505 (2005)

Page 15: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 29

Extracting SWNT Thermal Conductivity

• “Inverse” numerical extraction of k from the high bias (V > 0.3 V) tail

• Comparison to data from 100-300 K of UT Austin group (C. Yu, NL Sep’05)

• Result: first “complete” picture of SWNT thermal conductivity from 100 – 800 K

E. Pop et al., Nano Letters 6, 96 (2006)

Yu et al. (NL’05)This work

E. Pop 30

Light Emission from Metallic SWNTs

• Joule-heated tubes emit light:

– Comes from center, highly polarized

– Quasi-metallic = small band gaps

– Emitted photons at higher energy than

applied bias (high energy tail)

D. Mann et al., Nature Nano 2, 33 (2007)

~ σT4

Polarization

Energy (eV)2.2

suspended

1

0

2

1.4 1.6 1.8

3

2.0

on substrate S

S

D

γ(a

.u.)

Vds = 1.4 V

Vds = 7 V

900 750 600Wavelength (nm)

angle0 90

γ(a

.u.)

1

0

-5

5

0

1 2

source

drain

Dis

tance (m

m)

γ (a.u.)0

trench

Page 16: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 31

Return to SWNTs On Substrates

• SWNT on insulating solid substrate

• Heat dissipated into substrate rather than along tube length

• Q: How do I model heat loss into substrate?

• [A: need some gauge of the tube temperature]

g

DT

Pt

E. Pop et al., Proc IEDM 2005; Proc IEEE 2006

SiO2

E. Pop 32

Nanotube Temperature Gauge

g

Pt

SiO2

Page 17: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop 33

Nanotube Temperature Gauge

g

Pt

• Doesn’t exist

• But… oxidation (burning) temperature is known

O2

SiO2

TBD ~ 600 oC

Suspended On substrate

E. Pop 34

Breakdown of SWNTs in Air (Oxygen)

• Data shows SWNTs exposed to air break down by oxidation at

500 < TBD < 700 oC (800–1000 K)

• Joule breakdown voltage data shows VBD scales with L in air

• Supports cooling mechanism along the length, into the substrate

E. Pop, Proc. IEDM (2005)A. Javey, PRL 92, 106804 (2004)

0)(')( 0 TTgpTkA

BDBDBD ITTgLV /0

At breakdown: LVIp BDBD /'

Page 18: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop

Electrical Breakdown of SWNTs

• SWNT exposed to air from the top

• Sweep voltage low to high

• Temperature peaks in the middle

• When Tmax = TBD V = VBD and PBD = IBDVBD

35

VBD

SiO2g

L

PttOX

d

tSISi(a) (b)

E. Pop et al., J. Appl. Phys. 101, 093710 (2007)

E. Pop

Electrical Breakdown of SWNTs

• SWNT exposed to air from the top

• Sweep voltage low to high

• Temperature peaks in the middle

• When Tmax = TBD V = VBD and PBD = IBDVBD

36

-1 0 1 2300

500

700

900

X (mm)

T (

K)

Tmax

ΔTCVBD

E. Pop et al., J. Appl. Phys. 101, 093710 (2007)

Page 19: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop

Breakdown Data from Literature

• “Short” vs. “long” breakdown: Compared to thermal “healing” length ~ 0.2 µm

• Note: There is a minimum breakdown power ~ 0.05 mW

• We can learn a lot more about electrical and thermal properties

37

1)2/sinh()2/cosh(

)2/sinh()2/cosh(0

HTHH

HTHHBDBD

LLgLLL

LLgLLLTTgLP

R

R

0

0.05

0.1

0.15

0.2

0 0.5 1 1.5 2

L (µm)

Zoom into L < 2 mm

"long""short"

PBD = 88.8L

R2 = 0.87

0

0.2

0.4

0.6

0.8

1

1.2

0 2 4 6 8

PBD

(mW

)

L (µm)

Stanford

CaltechInfineon

E. Pop, DRC (2007)

E. Pop 38

SWNT Compact Model Up to Breakdown

• Thermal “healing length” along SWNT ~ 0.2 mm

• Current saturation ~ 20 mA in long tubes (> 1 mm) due to self-heating

• Self-heating not significant when p’ < 5 mW/mm (design goal?)

• More current in short nanotubes = less heating?

Understanding transport

in a 3 mm metallic SWNT

up to breakdown:Tmax ~ 600 oC = 873 KVmax ~ 15 V

Model

Data

E. Pop et al., J. Appl. Phys. 101, 093710 (2007)

Page 20: Dept. of Electrical & Computer Engineering ...poplab.stanford.edu/pdfs/EPop_UIUC_NDslides_Apr2008.pdf · Dept. of Electrical & Computer Engineering ... 4 nanotube Pt Pt gate ... =

E. Pop

Summary

• Small device dimensions, high local

power densities

• Increased device thermal resistance with

decreasing dimensions

• Physics-based models to capture:

– Size effects

– Phonon non-equilibrium

– Transient temperature effects

• Opportunity for “bottom-up” thermal

device and materials design

39

0.1

1

10

100

1000

10000

100000

0.01 0.1 1 10L (mm)

RTH (

K/m

W)

SOI FET

Bulk FET

SWNT

PCM

http://poplab.ece.uiuc.edu