UNIVERSITÀ DEGLI STUDI DI PAVIA

FACOLTA’ DI INGEGNERIA

DOTTORATO DI RICERCA IN INGEGNERIA ELETTRONICA,

INFORMATICA ED ELETTRICA

XXI CICLO

DESIGN AND CHARACTERIZATION OF MIXED-SIGNAL

ICs FOR MOTOR DRIVE APPLICATIONS

Tutor:

Chiar.mo Prof. Enrico Dallago

Tesi di Dottorato di:

STEFANO RUZZA

I

Contents

Chapter 1 Introduction .................................................................................... Pag. 1

1.1 – Integrated circuits for motor drive applications ............................... Pag. 4

1.1.1 – Introduction .......................................................................... Pag. 4

1.1.2 – Need of a current feedback for motion control..................... Pag. 5

1.1.3 – Current sensing method for otor drive applications ............. Pag. 6

1.1.4 – Objectives in motor current measurements .......................... Pag. 7

1.1.5 – Traditional measurements method ....................................... Pag. 8

1.2 – Technologies for high voltage integrated circuits ............................ Pag. 11

1.2.1 – Introduction .......................................................................... Pag. 11

1.2.2 – Junction isolated HVIC ........................................................ Pag. 12

1.2.3 – Adopted high voltage integrated technology........................ Pag. 13

1.2.4 – Reduced Surface Field (RESURF) technology .................... Pag. 15

References ............................................................................ Pag. 20

Chapter 2 Integrated low voltage floating power supply in high voltage technology for high dV/dt applications......................................... Pag. 22

2.1 – Introduction ...................................................................................... Pag. 23

2.2 – Ways to implement the LVFS ..........................................................Pag. 24

2.3 – The proposed LVFS structure........................................................... Pag. 26

2.4 – Performances of the prototype.......................................................... Pag. 30

2.5 – Improved output stage: description and simulations ........................ Pag. 33

2.6 – Measurement setup and experimental results from

the second prototype......................................................................... Pag. 35

2.7 – Bandgap voltage reference for high side floating pocket ................. Pag. 42

2.8 – Sources of error in a bandgap voltage references............................. Pag. 43

II

2.9 – Implemented bandgap circuit ........................................................... Pag. 44

2.10 – Analytical description of the proposed offset

compensation technique ................................................................... Pag. 47

2.11 – Simulation results ............................................................................. Pag. 50

References ........................................................................................ Pag. 52

Chapter 3 Fast-responding integrated over-current detector for motor drive applications ................................................................ Pag. 54

3.1 – Introduction ...................................................................................... Pag. 58

3.2 – Proposed idea of integrated over-current detector............................ Pag. 59

3.3 – Implemented high voltage power supply ......................................... Pag. 59

3.4 – High voltage level shifting for fault communication ....................... Pag. 60

3.5 – Low losses continuous-time level shifting technique....................... Pag. 62

3.6 – Complete over-current detector IC...................................................Pag. 63

3.7 – Simulation results ............................................................................. Pag. 66

3.8 – Implemented IC and experimental characterization......................... Pag. 69

References ........................................................................................ Pag. 73

Chapter 4 Development of a single shunt front-end for current sensing IC .......................................................................... Pag. 75

4.1 – Introduction ...................................................................................... Pag. 76

4.2 – Parasitic effects on the DC- bus current signal................................. Pag. 79

4.3 – Existing front-end prototype............................................................. Pag. 85

4.4 – Implemented front-end circuit .......................................................... Pag. 86

4.5 – Input filter for the implemented front-end........................................ Pag. 88

4.6 – Design of the fully differential operational amplifier....................... Pag. 91

4.7 – Simulations on the complete front-end circuit ................................. Pag. 96

References ........................................................................................ Pag. 100

III

Chapter 5 Integrated current amplifier with track and hold function for low side current sensing in three-phase inverter ................... Pag. 102

5.1 – Introduction ...................................................................................... Pag. 103

5.2 – Evaluation of the current sensing architecture ................................. Pag. 105

5.3 – Proposed sensing solution ................................................................ Pag. 106

5.4 – Timing of the track and hold block ..................................................Pag. 109

5.5 – Evaluation of the current amplifier prototype .................................. Pag. 111

References ........................................................................................ Pag. 113

Conclusions .......................................................................................................... Pag. 115

1

...non v’è nulla di nascosto

che non debba essere svelato

e di segreto che non debba

essere manifestato.

Matteo 10, 26-33

1

1. Introduction

Nowadays energy saving is becoming a real problem. Energy is an input to industrial

production and seeking productivity gains has always been among the basic goals of

industrial firms. Therefore, energy is progressively converted and used by means of more

advanced equipment. The optimization and the increase of the efficiency that have been got

in all industrial processes are the most significant factor in decreasing energy required by

the industrial activity.

(a) (b)

Figure. 1 Energy consumption trend: (a) Fuel mix in industry; (b) World electricity consumption.

The fuel mix has changed significantly in industry, between 1990 and today, as shown in

Fig. 1 [1]. The share of solid fuels in industrial energy consumption declined from 21.5%

in 1990 to 13.1% in 2005, while gas and electricity attained shares of 34.5% and 29.9% in

2005, up from 30.5% and 22.9% in 1990, respectively. The projected changes in the fuel

mix in industry continue past trends. The shares of coal and oil decline, albeit at a slower

pace than in the past. Gas penetration slows down as a result of high gas prices. The

electrification trend, however, is projected to continue in the future. During 2005-2030 the

growth of electricity demand is forecasted to be almost twice as high as the growth of total

energy consumption in industry. By 2030, electricity is projected to attain 34.3% of total

energy consumption in industry.

2

The worldwide electricity consumption can be divided in different slices, referring to

different applications as showing in the diagram in Fig. 2:

Figure 2. How people use electricity worldwide

It can be seen, a very large part of energy consumption in the world is dedicated to motion

[2]. The most common environments which can be included in this segment of the

electricity market are appliances, industrial applications and automotive. Due to this

incident, all motor manufacturer, in particular for consumer and appliance products

decided in the last year to switch to permanent magnet motors: in fact, this class of motor

has a really improved efficiency compared to synchronous or induction motor (see Fig. 3).

(a) (b)

Figure 3. Performances of a 750W motor: (a) losses comparison; (b) efficiency comparison;

3

Moreover considering the electrical drive which controls this motor, large improvements

have been done from the electro-mechanical drive to the actual electrical drive which

allows to control the motor in a intelligent and energy saving way. The improvements have

been obtained both from the control technique (i.e. SVPWM) and from the hardware point

of view (power switch and electronics controller) developed to drive the motor as

efficiently as possible.

4

1.1 Integrated circuits for motor drive applications

1.1.1. Introduction

Integrated circuits are becoming more and more popular in power electronics and motor

drive applications, allowing a large number of features that were traditionally realized

using discrete components or multi board system to be implemented using a small and

reliable IC.

Today’s motor drive applications require an increasing level of performances in a usually

limited space and integrated motor-control systems (so called IMDs i.e. Integrated Motor

Drivers) are becoming the real challenge for the future. The benefit of this new approach

has to be seen in a lower system cost, in a cost effective performances improvement

(thanks to the easier matching of the motor–driver system) and in EMI reduction due to the

elimination of long and noisy connections between the two parts. Moreover, the designer

can benefit from area saving on the board and better performances with respect to discrete

solutions. Power products today available on the market give motor driver manufacturers

the opportunity to directly develop their own driver, leaving to designers the possibility to

define all control electronics. The obtained Intelligent Power Modules (IPMs) often

integrate IGBTs, Diode and Gate Drivers [3].

In voltage source inverter used in electrical drives in a range up to some kilowatt, junction

isolated high voltage integrated circuit (HVIC) are becoming more and more popular for

the implementation of Gate Drivers and Current Sensors. These ICs are usually exploited

to properly control motor speed and torque (motion control) in modern appliance,

consumer, automotive and industrial applications.

Figure 4. Typical applications where motion control is required.

5

In fact, as will be better explained in the following, these technologies provide the

possibility to diffuse in a single substrate, monolithic IC, both the high voltage parts which

can move up to 600-1200V with respect to the system substrate referred to ground (e.g. the

drive circuit for the inverter high-side power switches) and a low voltage mixed-signal part

used for the data processing and to interface the DSP which usually control the system

(whose supply voltage depends on the technology). An example is reported in Fig. 5.

Figure 5. Example of applications where HVIC are exploited.

The possibility to implement advanced functions or control algorithms with a signal

processing circuitry floating with respect to the system ground is fundamental in motion

control ICs as will be explained later. Moreover, the cost of these ICs results to be lower

with respect to the same features implemented with a Silicon On Insulator (SOI)

technology, due to capability to reach an high reverse voltage using a junction based

insulation instead of an additional silicon layer between the substrate and the circuitry

parts. However, some disadvantages occur with respect to the SOI solution as will be

explained.

1.1.2 Need of a current feedback for motion control

Three-phase pulse width modulation (PWM) voltage source inverters (VSI) are widely

used in many industrial and commercial applications such as variable-speed ac motor

drives and uninterruptible power supplies (UPS) under 5kW market segment. In these

6

applications, the current feedback is fundamental to realize and obtain the best control of

both motor speed and torque: in fact, the knowledge of the amplitude of the motor currents

gives the customer the possibility to directly control the motor torque.

Fig. 6 Fundamental blocks for motor control.

A typical motion control scheme is reported in Fig. 6. Generally, it’s important monitoring

the variable that has to be controlled in the considered application. Using speed and/or

position transducer, such as encoder or tachometer, the control bandwidth would result

really limited, rising the response time of the system. On the other side, the possibility of

monitoring the motor’s currents allows to know directly the sinusoidal voltages that are

provided by the inverter and modify them frequency and amplitude as needed. Therefore,

while simple AC drives only use current limit control, motor phase current is used as the

primary feedback variable in more advanced drives.

1.1.3 Current sensing method for motor drive applications

Even though motor drives are increasingly digitally controlled, motor current measurement

has traditionally remained analog-based. In fact, most motor current sensing today,

whether magnetic or resistive shunt based provides outputs that are an analog signal.

Modern motor drives, however, are predominantly digitally controlled [4, 5] and the

control element (microprocessor or DSP) needs current feedback in a digital format. This

means that additional processing steps are required. Unfortunately, each processing step

adds delay, reduces signal integrity and adds to the overall cost of the system. Furthermore,

traditional sensors attempt to recreate the full bandwidth motor current (including high

frequency ripple), when only the fundamental motor current is needed for control purpose.

7

Unfortunately, bandwidth is expensive and therefore, having unnecessarily wide

bandwidth makes current sensor more costly than it need be.

1.1.4 Objectives in motor current measurements

Talking about accuracy for current measurement in motor drive, absolute accuracy is not as

important as resolution. In other words, less “torque per bit” and more bits is the goal.

Typical drives have been working with 10 bits of resolutions, but new design are targeting

to 12. Linearity is also important and the combination of resolution and linearity make it

possible to create smooth torque over a wide range of motor load condition. Temperature

performance is also an important factor in motor current sensors: an offset drift versus

temperature adds errors to the velocity/position control loop and gain changes over

temperature also make it difficult to maintain consistent closed-loop performance.

Another issue in motor current measurement is to deal with ripple current generated by the

PWM which control the VSI. As mentioned, conventional control strategies would need

the fundamental motor current as feedback variable, while the PWM ripple is undesired

noise. Drives with a low-bandwidth current loops can use conventional filtering techniques

to eliminate the PWM ripple from the measured motor one. However, the intrinsic phase

delay of a filter makes this method unsuitable for drives where the current loop bandwidth

is greater than 1/20 of the PWM frequency.

One common method of dealing with ripple current is to sample at specific moment in time

when the value of the ripple happens to be zero. This requires separate sample and hold

circuits, in addition to the current measurement transducers, whose timing is not straight

forward. This objective can be achieved by sampling the current at the peaks of the PWM

carrier waveform. The effectiveness of this method is largely dependent on the ripple

magnitude and on the accuracy of the sample timing. For motors with large inductance

values, like typical AC induction motors, the magnitude of the ripple current is small

compared to the current of interest. For higher performance permanent magnet AC motors

with low inductance, the magnitude of the ripple current can be quite large. To extract

useful motor current information for feedback purposes, the system must either filter out

8

the ripple current (which adds phase delay), or sample at the proper instant to effectively

cancel-out the ripple.

1.1.5 Traditional measurement methods

Current is typically measured with one of two methods: voltage drop across a resistor

(resistive shunt), or magnetic transducer.

Resistive shunt sensing has the advantage of a relatively low-cost sensor. The disadvantage

is that there is a trade-off between sensitivity and power dissipated in the resistor. At

higher currents, and therefore lower shunt resistance values, the inductive component of

impedance begins to dominate. The transmission zero formed by the series RL

combination therefore falls at a lower frequency. This can be compensated somewhat by

canceling with a suitably matched pole of an RC filter. Even with compensation, however,

the useable upper frequency limit is reduced as the resistance value drops.

The second issue with resistive current sensing is where to measure the current. Since

actual motor current is the desired value, the obvious choice is to put the sense resistor in

series with the motor phase (see shunt a in Fig. 7).

Figure 7. Current measurement methods

9

The complication of that choice is that the signal of interest is a millivolt differential value

across the sense resistor, but the common-mode voltage of the motor phase is typically

hundreds of volts switching at high frequency with rapid dV/dt (up to 50V/us) . There isn’t

a practical differential amplifier capable of rejecting that much common-mode voltage

with the required bandwidth, so an alternative approach is required.

One common approach is to use an optically isolated amplifier in which the differential

signal is modulated and communicated across the isolation barrier via infrared signal. The

optical isolation effectively eliminates the common-mode voltage problem, but now the

floating side of the isolator needs an isolated power supply. A further problem is that

performance of typical optocouplers changes with temperature and degrades over time. An

often overlooked issue is that the optocoupled amplifier output is a differential signal

which requires a differential amplifier for scaling, and a level-shifting stage to work with

the input of most analogue to digital (A/D) converters. This external amplifier can easily

become the limiting factor for overall system performance. For example, to achieve 12-bit

resolution, a high performance op-amp is a necessity. The cost of adding high performance

op-amps to each current measurement channel rapidly increases the cost of this solution.

Another common alternative is to measure current through resistors on each low-side

transistor emitter in the three-phase inverter (see shunt b in Fig. 7). As long as the

measurement circuit is referenced to the DC bus common, this approach eliminates the

common-mode voltage problem. However, a second problem arises: the measured current

is no longer motor phase current, but half-bridge current. If the low side switch is

conducting (through either the transistor or freewheeling diode) then the current is equal to

that motor phase current. This certainly occurs periodically throughout the PWM cycle, but

now a reconstruction circuit including a sample and hold amplifier is required. Moreover,

in order to sample all three motor phase currents simultaneously (for zero phase-shift), all

three low side switches must be conducting. This only happens at a zero vector state in

which all three low side switches are on.

Even for conventional modulation methods like sinusoidal or space vector modulation, the

width of the pulses to be measured can become very narrow, placing an increasing

performance burden on the sample and hold circuit. When the modulation index meets and

exceeds unity (as it does for overmodulation methods), however, the current pulses

disappear altogether. Overmodulation methods require a different and more complex

strategy for motor current reconstruction if this method of sensing is used.

10

Another method to overcome the common-mode rejection problem is to use a single shunt

on the DC bus (see shunt c in Fig. 7), typically in the negative side to avoid level shifting.

As for the previous case, this method gives the total bus current, not motor phase current. It

is possible to reconstruct amplitude-only motor current but it requires a complex circuit

and DSP calculation.

Magnetic sensors, on the other hand, are isolated by their nature. This means that motor

phase current can be directly measured without the common mode voltage and

reconstruction circuit problems just discussed. Traditional current transformers cannot be

used because of the DC or very low frequency current components present in motor drives.

Hall-effect current transducers solve that problem [6]. They use a ring-type magnetic core

with a Hall-effect semiconductor element placed in an air-gap to measure magnetic flux

resulting from the current through the centre of the core. However, these so-called “open-

loop” Hall-effect sensors suffer from several serious limitations. The magnetic flux in the

core depends upon the magnetic properties of the core material, which is non-linear and

temperature dependent. Moreover, the Hall element itself has temperature dependence, and

does not exhibit wide bandwidth. Overall, the accuracy and bandwidth of open-loop Hall

effect current sensors is not suitable for high performance AC drives.

A clever solution to the aforementioned limitations is found in the “closed-loop” Hall-

effect current sensors. In these devices, a cancelling coil (of e.g. 1,000 turns) is wound

upon the magnetic core described above. A built-in feedback amplifier drives current

through the canceling coil such that the flux (measured by the Hall-effect sensor) is always

driven to zero – thus canceling the ampere-turns generated by the current through the

centre hole. The output of the current transducer is then that canceling current, which is

equal to the measured current scaled-down by the turns ratio. The majority of temperature

dependent gain and core nonlinearities are also cancelled using this method, although some

offset issues remain. The overall bandwidth and accuracy of these transducers has proven

to be very good for motor drive applications. However, the complex construction and large

magnetic cores required make these transducers larger and more costly than the

alternatives. These transducers do not have any built-in over-current sensing, so additional

reference threshold circuits and comparators (for + and -) must be added, further increasing

the size, cost and complexity.

11

1.2 Technologies for High Voltage Integrated Circuits

1.2.1 Introduction

In the latest years, the rapid growth of microprocessor based electrical drives, coupled with

advances made in power semiconductor devices, have spurred the semiconductor

community to focus more in integrating the power conditioning section of these systems.

This has led to the need of Power Integrated Circuit (PIC) or High Voltage ICs (HVIC),

defined as ICs combining high voltage and/or high current components monolithically with

low voltage/low current control components [7].

These ICs are largely use for motor control for industrial and appliance market, but also in

application such as power converter, electronics ballast, automotive and audio/video

amplifiers.

In spite of this large range of applications, the grown of these technologies in the latest two

decades has been much slower than expected. Different reasons can be found to justify this

trend:

1. initially, the costs of these technologies until last years, has been 5-10 times higher

then the corresponding discrete solutions.

2. with the advances of semiconductor physic and technologies, the cost of discrete

power devices has decreased rapidly thereby posing a severe competition to HVIC.

3. finally, in the beginning only a limited number of special purpose applications have

been explored, without a general purpose standard product (such has been memory

chips for the development CMOS technology) which supported an high volume

production.

However with the increasing thrust for miniaturization, new applications are emerging and

advances in power devices and technologies are bringing the cost down.

Several approaches have been explored developing technologies for HVICs. Typically two

approaches have been prominent. The first involves starting with an optimized high

voltage device structure and building low voltage devices around it. The second approach

starting with a low voltage CMOS technology and incorporating high voltage devices in it.

12

The former approach is more popular than the latter. In fact, the low voltage devices are

typically CMOS or Bipolar and design considerations include minimizing the total mask

count, process complexity and the total resulting cost. The consequences of the approach

followed are reflected in the performance and cost trade offs in the resulting technologies.

Devices isolation and reduction of unwanted interaction between circuit components are

key elements to obtain a reliable and predictable operation in HVICs. IC technologies are

classified in terms of type of isolation technique employed. Three types of isolation

schemes are encountered:

• junction isolation (JI), as in bipolar process

• self-isolation (SI), as in MOS process

• dielectric isolation including Silicon-On-Insulator (SOI)

Of these, junction and self-isolation technologies have received the higher attention in the

industry. Examples of these technologies are seen in Bipolar CMOS and DMOS (BCD)

process ranging in maximum voltage rating from 200V to 700V. Other approaches include

thin epi RESURF concept (explained in the following) based on high voltage lateral

DMOS transistor and CMOS and Bipolar low voltage devices for the mixed-signal parts. JI

and SI technologies cover all the voltage rating mentioned before and are commonly

employed where a limited number of high voltage devices are required on the same chip.

Applications include switching converters, automotive electronics, motor control and

display drivers.

Unlike Junction isolation, dielectric isolation technologies provides superior performance

but usually at higher cost, determined primarily by the starting material. For this reason,

these technologies have been used where the cost pressures are less severe: for example

telecommunications ICs where multiple high voltage devices are integrated into the same

chip. More recently, direct wafer bonding technique has given rise to increased interest in

SOI, which promises a lower cost solution to large class of HVICs.

1.2.2 Junction isolated HVIC

In JI processes, devices are electrically isolated from each other by reverse based p-n

junction as in bipolar process. In SI, common in MOS technologies, thick field oxides on

13

the surface between active devices coupled with adequate doping below the oxide prevent

field inversion at the maximum voltage and thereby provide the required isolation. Within

JI and SI technologies, further classification occurs, based on whether the power devices

are implemented vertically, as in discrete devices, or laterally. The vertical technology is

has also been termed smart power as opposed to high voltage IC or power IC which refers

primarily to lateral technology. This terminology reflects to the fact that vertical

technologies are primarily based on vertical power devices processes with added elements

to provide signal parts.

1.2.3 Adopted high voltage integrated technology

Generally a typical structure for an HVIC is the one reported in Fig. 8.

Figure 8. Simplified block scheme for an HVIC

The different parts which can be identify in this circuits have been indicated with a number

in Fig. 8 and can be classified as:

1. A low voltage zone referred to ground that includes circuits which interface the

IC with a DSP, a microcontroller or a low voltage external circuitry.

2. A medium voltage zone supplied at 10-20V and referred to ground.

3. One or more medium voltage zone supplied at 10-20V but referred to a floating

voltage which can be up to 600V.

4. Level shifting circuitry allowing the communication between the two zones

which are referred to different voltage nodes.

14

The parts indicated as 1 and 2, are commonly indicated as the low side (LS) of the IC,

while part 3 is indicated as high side (or HS). The part indicated as “external low voltage

circuit” can be either the microprocessor or the DSP which controls the drive. Instead, the

part indicated as “External device” can be the gate of either an IGBT/MOSFET of the

inverter or the shunt resistor which transduces the motor phase current.

As can be seen in Fig. 8, a part of these IC is not referred to ground, but it has to move

referred to what is commonly called floating ground. This need is due to the typical

working conditions environment of a inverter leg which drives the motor phase. To better

understand this requirement refer to Fig. 9, where a gate driver and a current sensor ICs are

directly connected with the inverter leg.

Figure 9. Single leg of the three phase inverter.

Let us focusing on the Gate Driver: the high side of the IC contains the buffer circuit which

turns on/off the IGBT2. The buffer has to be able to turn on this power devices

independently from the voltage value on the floating ground S, which represents also the

IGBT emitter and can move between 600V and 0V depending on the state of the inverter

leg. Referring the driving circuit to S, is the only way to provide to the power devices the

required VCE which turns them on/off for any condition of the inverter leg.

As far as the Current Sensor is concerned, the HS circuitry has to detect the voltage Vin

provided by the shunt on the motor phase rejecting VS which is a common-mode voltage.

Also in this case, to obtain this results, the HS circuitry has to move referred to the S node.

Having demonstrated the need of a signal processing circuitry floating with respect to the

system ground, it’s now important to understand how it is possible to generate a supply for

15

this part of the IC. In fact, while the LS can be fed from a classical voltage source referred

to ground (VCC in Fig. 9), it’s easy to imagine that the supply for the HS will have to move

referred to the floating ground S. Typically, a bootstrap circuit is used to supply the HS of

the ICs. A bootstrap capacitor, called CB in Fig. 9, is charged by a 15V source (VCC)

through DB when the low side switch is closed and provides VB=15V referred to VS when

the high side switch is closed. The voltage value 15V is chosen to comply with power

transistors drive requirements. This external supply VB is characterized by ripple noise due

to the charging and discharging phases on CB. Thus, its use as a supply for the signal

processing circuitry would not be straight forward.

1.2.4 Reduced Surface Field (RESURF) technology

The junction isolated high voltage technology that has been used to develop the large part

of the circuits which will be presented in this work is based on Resurf technique [8-11]

and has been developed by International Rectifier Corporation.

It’s important understanding also what is the silicon structure both of these IC and of some

particular devices, as are the HV DMOS devices.

(a)

(b)

Figure 10. Adopted technology: (a) cross-section; (b) planar view.

16

The high side and the low side of the IC are realized in two different n- epi pockets which

are epitaxialy grown on a single p- type substrate normally connected to the global ground

of the system (VSS in Fig. 9). As it can be seen in Fig. 10, the floating pocket, which is

referred to the S node, is characterized by a particular geometric shape that allows the

n- epi/p- sub junction to withstand a high reverse bias voltage. Resurf technique is

generally employed to properly shape the electrical field. Therefore, the junction

breakdown can be tuned to reach as much as 600V.

In junction isolated HVIC, this technique has allowed the integration of HV devices,

ranging from 20V to 1200V, with bipolar and MOS transistors. The basic principle of this

technique can be explained as follows: a higher breakdown voltage in vertical devices

usually requires a thicker and lower doped epitaxial layer. However, in experimental IC

samples with a lateral isolation diffusion, a much higher breakdown voltage is obtained on

a thinner layer: here the surface field at the isolation junction is decreased by 2-D

depletion.

Fig. 11 Cross-section of a Resurf diode

The basic devices structure is shown in Fig. 11: it consist in an high voltage diode on a

high-ohmic p- sub with an epitaxialy grown n- layer on it, which is laterally bonded by a

p+ isolation diffusion. The diode thus formed consists in two parts:

1. a lateral diode with a vertical n-/p+ boundary and possible lateral breakdown

2. a vertical diode with the horizontal n-/p- boundary and possible vertical breakdown

For a thick (50µm) epitaxial layer the breakdown voltage is 470V and the maximum field

is at the surface at the n-/p+ junction (see Ec in Fig. 12a). This is a critical zone, because of

impurity and broken tie which normally affect the surface of a silicon slice, making it more

sensitive versus electrical field which could damage it. For a much thinner epitaxial layer

17

(15µm) the lateral depletion layer is influenced by the depletion layer of the vertical

n-/p junction and the surface field is reduced: a 2D-effect. At the higher voltage of 1150V

(Fig. 12b) the field at the surface has two peaks: one originating from the n-/p+ junction

and another just below the surface at the curvature of the n+/n- junction, with a moderate

field in between. If the lateral distance is sufficient, breakdown occurs now vertically in the

semiconductor body under the n+ region: here, the problems highlighted for the surface

zone are not present making Ec less effective. The voltage drop is distributed in the epi

layer from the p+/n- junction to the n-/n+ junction (as shown also by the equipotential lines

in Fig. 12b).

(a)

(b)

Fig. 12. Equipotential lines and Electric field (E) in bulk and at the surface for various epi

thickness: (a) for 50µm at BV=370-470V; (b) for 15µm at BV=1200V.

18

As mentioned before, in this technology, different devices are available:

• CMOS (p channel with Lmin=4.5µm, n channel with Lmin=2µm).

• Bipolar: a) the vertical pnp exploits the substrate as collector and therefore is usable

only in the low side of the IC; b) the vertical npn exploits the n- epi as collector

layer and therefore if it is used in the high side of the IC, it has to be connected to

the external supply provided by the bootstrap capacitor.

• Resistors: (both diffused and polisilicon based).

• Capacitor: (two types, with different poly doping)

• Zener diode

• DMOS p and n channel with voltage withstand up to 600V

The characteristics of the DMOS devices have to be explained in details, in order to

understand their properties and how they are exploited in a HVICs. As far as the

HV n channel is concerned, it has been realized and implemented exploiting a two-field

reduction layers [12].

Figure 13. Lateral 600V n channel MOSFET structure using two field-reduction layers

The device structure is shown in Fig. 13. Being a double diffusion MOS (DMOS), the

channel size is fixed and is given by the difference between the limit of the ptubmv layer

which constitute the body of the device and the n+ layer which constitute the source. The

device uses a p type field-reduction layer (ptubmv in Fig. 13) over a n- type field-reduction

layer (the epitaxial layer, n- epi).

The device has both the source and gate terminal in the medium voltage zone of the low

side, while the drain terminal is provided by the floating epi pocket. Therefore, it can be

exploited to implement the communication over the two pockets: in particular, the

n channel device provides the communication from the low side to the high side of the IC.

19

Unfortunately, being the epitaxial layer connected to the external floating supply VBS

(which biases the HS pocket), the device would have its drain at a fixed drain voltage and

the detection of the communicated data would not be possible. This condition, is avoided

implementing the DMOS with the layout of Fig. 14: giving the device this particular shape

the n- epi part which constitutes the drain region results very narrow creating a parasitic

resistive path (about 10kΩ) between the drain contacts and the epi bias contacts which are

connected to VBS. Therefore, when the DMOS turns on, its current creates a voltage drop

on this resistive path which can be detected with a comparator or triggering a flip flop.

Fig. 14 Layout cell of the 600V n channel DMOS.

A complete pocket including both p and n channel DMOS is shown in Fig. 15: as can be

seen, in addition to these devices, the pocket is implemented using parts which are called

HV terminations (HVterm), whose structure is reported in Fig. 16. These parts provide the

isolation of the HS through the high resistive polisilicon spiral which shape the electrical

field all around the pocket avoiding the breakdown at the surface. In fact this spiral has a

terminal connected to VB and the second connected to substrate voltage: this allows to

distribute the voltage drop all along the border of the floating pocket.

Other important characteristics and properties of this technology will be highlighted and

explained in the following chapters, being closely tied to the different applications which

will be take in consideration and therefore not straight forward.

20

(a) (b)

Fig. 15 Complete high voltage pocket: a) Layout view; b) Identified blocks;

Fig. 16 Layers structure of the high voltage termination.

.

References

[1] European Commission Directorate-General for Energy and Transport, “European Energy and Transport Trends to 2030 - update 2007,” online available: http://ec.europa.eu/dgs/energy_transport .

[2] Energy Information Administration, “International Energy Outlook 2006,” online available: www.eia.doe.gov/oiaf/ieo/index.html.

[3] D. Giacomini, E. Bianconi, E. Martino, M. Palma, “A Fully integrated power module for three phase servo motor drive applications,” in Proc. IEEE Industry Applications Conference, 2001, pp. 981-987.

21

[4] E. Persson, “A new approach to motor drive current measurement,” in Proc. IEEE International Conference on Power Electronics and Drive Systems, 2001, pp. 231-234.

[5] E. Persson, T. Takahashi, “Eliminate Ripple Current Error from Motor Current Measurement,” Application notes online available: www.irf.com/technical-info/whitepaper/motorcurrent.pdf

[6] M. Pastre, M. Kayal, and H. Blanchard, “A Hall Sensor Analog Front End for Current Measurement With Continuous Gain Calibration,” IEEE Sensor Journal, Vol. 7, no. 5, pp. 860-867, May 2007.

[7] B. Murari, F. Bertotti, G. S.Vignola, Smart power ICs. Sprinter-Verlag, Berlin 1996.

[8] A. W. Ludikhuize, “A review of RESURF technology,” in Proc. IEEE International Symposium on Power Semiconductor Devices and ICs, 2000, pp. 11-18.

[9] A. W. Ludikhuize, “A Versatile 700-1200-V IC Process for Analog and Switching Applications,” IEEE Transaction on Electron Devices, Vol. 38, no. 7. July 1991.

[10] U. N. K. Udugampola, R. A. McMahon, F. Udrea, K. Sheng, G. A. J. Amaratunga, E. M. S. Narayanan, S. Hardikar, M. M. De Souza, “Dual gate lateral inversion layer emitter transistor for power and high voltage integrated circuits,” IEE Proc. Circuits, Devices and Systems, vol. 151, pp. 203-206, June 2004.

[11] K. Ishikawa, K. Suda, M. Sasaki, H. Miyazaki, “A 600V driver IC with new short protection in hybrid electric vehicle IGBT inverter system,” Proc. IEEE International Symposium on Power Semiconductor Devices and ICs, 2005, pp. 59-62.

[12] J. S. Ajit, D. Kinzer, N. Ranjan, “1200V high-side lateral MOSFET in junction-isolated power IC technology using two field reduction layers,” in Proc. IEEE International Symposium on Power Semiconductor Devices and ICs, 1993, pp. 230-235.

22

2. Integrated low voltage floating power supply in high

voltage technology for high dV/dt applications

This chapter presents an integrated floating power supply in junction isolated high voltage

technology. This circuit is used for generating a low voltage supply and feeding signal

processing circuit inside the floating pocket of either a current sensor or gate driver ICs,

used in motor drive applications. The main feature of this supply is that the floating n- epi

pocket it is realized in, is biased with a voltage lower than the maximum voltage value

present in the pocket itself. Therefore signal processing circuits inside it would be realized

using signal MOSFET devices instead of 20V devices. Another important feature of the

proposed scheme is an effective immunity to the charge injection problem caused by high

dV/dt typical of these applications.

23

2.1 Introduction

Nowadays, servodrive applications driven by MOSFET and IGBT based inverters are

becoming more and more sophisticated in response to the needs of the market. As

mentioned in the first chapter, to allow advanced functions or control algorithms to be

implemented it is useful to have a signal processing circuitry floating with respect to the

system ground. For example, the phase current is often sensed using a shunt resistor

connected between node S and the motor phase (see Fig. 2.1) [1-3].

Figure 2.1. Single leg of the three-phase inverter.

This strategy makes the current signal continuously available to the controller, allowing an

easier regulation of the motor torque, while the current signal provided by a shunt resistor

on the return wire of the inverter [4-6] or in series with the IGBT emitter terminal [7, 8] is

available only for short periods of time alternated with blind intervals. Another advantage

of having the shunt signal continuously available is the possibility to realize an effective

input filter which removes current harmonic components useless to the controller .

The voltage signal across the motor phase shunt needs to be read with a front-end circuitry

floating with respect to the system ground. This is usually performed with a current sensor

chip realized in junction isolated (JI) high voltage technology. The front-end circuitry is

included in a floating n- epi pocket referred to node S (see Fig.2.1) which swings from 0V

to 300V/600V depending on which IGBT is closed on the inverter leg: thus VS becomes a

common mode signal.

24

The floating part of this ICs is usually supplied using either a bootstrap capacitor [9] or a

charge pump circuit [10]. The high and the low side (HS and LS in Fig. 2.1) of the

Integrated Circuit (IC) can be implemented with a galvanic insulation or in two separated

ICs; in this case the use of low voltage devices (5V, 3.3V) in the floating part is

straightforward [11] but this approach is quite expensive. Moreover, due to the large noise

provided by the applications noise coupling, become an issue added to area consumption

on the board.

On the other hand, with junction isolated high voltage technology, the use of low voltage

devices in the floating part is not an easy task. In fact, using the VBS=15V provided by a

bootstrap capacitor to feed the floating pocket, the signal processing circuitry would need

to be realized with 20V MOSFETs. The used technology provides also 0.5µm, 5V

MOSFETs, which would allow higher performances in the signal part.

In a floating n- epi pocket the n channel signal MOSFETs are implemented in a p well,

while the p channel signal MOSFETs are diffused directly into the epitaxial layer. This

means that n- epi pocket constitutes the body for p channel devices. Using VBS to bias the

epi pocket, the body of the p channel is biased at 15V. As a consequence, the working

range for the 5V devices should range in VB ÷ (VB-5V), while the shunt voltage (Vin in

Fig.1) is referred to node S: this makes a voltage shift of the input data Vin necessary, but

such operation could worsen the signal to noise ratio. This problem can be avoided only

referring the working range of the sensing circuitry to node S.

To do this, a structure called Low Voltage Floating Supply (LVFS) must be realized which

is capable of deriving from VBS a stable low voltage supply VOUT referred to node S, while

at the same time biasing the floating pocket.

2.2 Ways to implement the LVFS

Different ways can be considered and evaluated to implement the LVFS as reported in

[12]: it is necessary to highlight the advantages and disadvantages of these solutions to

understand the reasons behind the choice that has been made.

Solution a) The first way to obtain the 5V supply voltage is to perform a regulation

without integrating it in the current sensor chip. This can be implemented with an external

LVFS IC, referred to the S node. The regulator would regulate the VOUT starting from VB.

25

In this manner there are no topology limits for the LVFS circuit. The disadvantages are the

presence of another chip in the system and noise coupling on the board.

Solution b) The second solution is to diffuse in the current sensor chip a second floating

n- epi pocket that contains the LVFS. It is possible to use VB to bias this epi pocket so also

in this case there are no restrictions on the supply’s topology. However, when VS=600V,

some problems arise while providing VOUT to the second floating epi pocket that contains

the current sensing circuits.

Figure. 2.2. Breaking problem providing the regulated supply through a metal.

The first approach, uses a metal which crosses the field oxide zone between the two epi

pockets (see Fig. 2.2). Being the p- substrate connected to the global ground of the system

(VSS), some oxide breakdown problems occur when VB=615V. For modern technology,

this solution has a number of disadvantages, because it is necessary to depose a thicker

than usual field oxide to guarantee the integrity of the IC. This prolongs the field oxide

deposition step increasing time and costs. Moreover, any modification to a process step

requires very expensive and time consuming reliability and quality tests. Hence, this

solution can be considered viable only for high volumes.

Figure 2.3. Internal bonding between the floating pockets:

1) LVFS; 2) Sensing circuits; 3) Low Side.

26

Another way to provide VOUT to the second epi pocket is using two dedicated pads placed

in the two pockets and bonded together internally (see Fig. 2.3). The bond is surrounded by

plastic mould and guarantees dielectrical isolation. This solution increases the IC cost,

because it need two additional pad and internal bonding

Solution c) Finally, a fully integrated LVFS can be diffused in the same n- epi where

signal processing circuitry is implemented. This allows the n- epi pocket to be biased

directly by the output VOUT voltage of the LVFS circuit and not by VB, which is the

maximum voltage value we have in the pocket. This is the cheapest solution and the one

that was chosen.

2.3 The proposed LVFS structure

To bias the n- epi pocket with a voltage lower than VBS, a circuit solution is required which

guarantees all isolated junctions are reverse biased under any working condition.

Figure 2.4. The base-structure of the supply is reported in bold.

This result is obtained by connecting to VB only the drain of a 20V n channel MOSFET

and a polisilicon resistor (insulated because of its physical structure) as reported in

Fig. 2.4. The n channel provides the LVFS output VOUT=5V by its source terminal. The

27

remaining circuitry (regulation loop and all the hypothetical circuits to be supplied) are

implemented by 5V MOSFETs and supplied directly by VOUT.

Figure 2.5. All isolation junctions are reverse-biased for each value of VS.

Fig. 2.5 shows how using this structure all the insulation junctions (J1-J4) are reverse biased

for each value of VS.

The basic structure of LVFS reported in Fig. 2.4 can be easily modified to obtain lower

than 5V supply (e.g. 3.3V or 1.8V). The use of a n channel device in 20V technology is

mandatory because this MOSFET will provide VOUT through its source terminal. This

means that under usual working conditions its VDS will be higher than 5V.

In this way, VOUT=5V biases the floating pocket and feeds the current sensing circuits by

moving their working range where the data provided by the shunt resistor is available

(VOUT ÷ VS).

Figure 2.7. Schematic of the first prototype of LVFS.

28

The schematic cell implemented to prove the idea of LVFS is shown in Fig. 2.7 [tesi]. As

can be observed, only the drain terminal of a n channel MOS (Mb) in 20V technology and

a polisilicon resistor (R0) were connected to VB, as required due to the considerations

outlined above. This circuit was inserted in a test chip. It is an open loop topology which

allowed a VOUT to be realized based on the equation:

VOUT = VZ + VGSa - VGSb (1)

where VZ is the reverse bias voltage of the Zener diode D1. The load current Iload=1mA, is

the maximum consumption forecast for the current sensing circuits. Experimental results

for the test chip lay between the limit curves obtained by the Spectre® environment,

showing VOUT=5,243V with a maximum deviation of 6.2%. However, this circuit did not

provide a VOUT with the required precision because of the open loop topology.

Figure 2.8. First prototype of floating power supply (regulation loop in dotted line).

29

a

b

c d

Figure 2.9. Microphotograph of the IC, Area=640×380 µm2:

a) current source; b) bandgap; c) regulation loop; d) ESD on VB.

Therefore, a second version of the supply using a closed loop topology to improve

performance was realized [12]. The schematic and microphotograph of this supply are

shown in Fig. 2.8 and Fig. 2.9. This circuit was included in a test chip as well. It had the

same base-structure as the first supply circuit with only a polisilicon resistor (R2) and a

n- channel MOSFET (M1) in 20V technology connected to VB. The regulation loop was

implemented using a two stage amplifier. It was realized in 5V MOSFET technology and

supplied directly by the same output voltage that the circuit provided. The non inverting

input of the differential stage is biased by a bandgap reference, whose characteristics and

topology will be explained in the second part of this chapter. The bandgap’ s output

VBG=1.2V showed a precision of ±2.8% over a temperature range -40°C≤Temp≤140°C. A

bandgap reference was included because the technology used did not provide a Zener-

diode that could be biased by 5V. The bandgap circuit also guaranteed better temperature

compensation and precision than the Zener-diode solution. In the correct working point the

inverting input of the amplifier (V-) was also forced to 1.2V. In this manner it was

possible, after choosing the values of R3 and R4, to obtain the quiescent bias current of the

output stage (IM1) and the desired value of Vout. Thus, the bias current for M1, which

constitutes the buffer output stage, can be written as:

IM1=V- / R3 = 1,2V / R3 (2)

While, the value of VOUT can be written as:

VOUT=V- · (1 + R4 / R3) (3)

30

The second gain stage of the regulator amplifier was implemented as a common-source

stage. It was realized with a MOSFET in 20V technology (M2), because under normal

working conditions its VDS is higher than 5V. Both the bandgap and the current source

(inserted in the IC to feed the Opamp and the bandgap) were supplied by VOUT and

implemented in 5V technology. Therefore, some restrictions were placed on their topology.

In fact, the collector of the NPN devices included in these circuits was the n- epi pocket

layer and for this reason it has to be connected at 5V.

2.4 Performances of the prototype

A comparison between the simulations in the Spectre® environment and experimental

results for the implemented IC when VS=0 (DC condition) is reported in Tab. I: simulation

column reports worst case limits, while test column reports the behavior measured on

about 40 samples.

The first four lines of Tab. I shows how the measured values fall within the predicted

corner cases. Moreover, being VBS a noisy voltage because of the periodical charging and

discharging phases on the bootstrap capacitor, the Power Supply Rejection Ratio (PSRR)

of the circuit has been evaluated by superimposing a 2V peak to peak sinusoidal signal

over a steady VBS.

TABLE I SIMULATION VS. TEST: SIMULATION COLUMN REPORTS WORST CASE LIMITS; TEST

COLUMN REPORTS THE AVERAGE BEHAVIOUR OF OBSERVED CHIP.

Conditions Simulated VOUT [V] Tested VOUT [V]

T=27°C,VBS=15V, Iload=1mA 5.001 4.977 – 5.019

10V≤ VBS ≤20V, Iload=1mA 4.889 – 5.175 4.968 – 5.089

0.5mA≤ Iload≤1.5mA, VBS=15V 4.902 – 5.193 4.889 – 5.172

-40°C≤T≤ 140°C, VBS=15V, VBS=15V

4.766 – 5.226 4.873 – 5.192

PSRR @ 100KHz 46 dB 41 dB

PSRR @ 1MHz 40 dB 36 dB

PSRR @ 10MHz 22 dB 19 dB

Power dissipation 2.4 mW 2.5mW

31

The experimental results are slightly worse than simulations, but the disturbances reduction

is enough for the applications. Therefore, it is possible to conclude that there is good

agreement between the simulations and experimental results and the proposed LVFS

structure works correctly.

A problem appears when the floating pocket swings and it can be already highlighted

working in a voltage range (0-30V) well below the typical one. In fact, during the negative

dV/dt of VS, VOUT showed a voltage spike followed by a drop well below the nominal

value which can persist as long as 2.5µs (see Fig. 2.10). The amplitude and the duration of

this phenomenon were connected both to the swing slope and the current sunk by the load:

in particular, at the nominal dV/dt (some tens of Volt per nanosecond) and for DC+=300V

the IC typically fails.

Figure 2.10. Experimental voltage waveforms for negative swing:

a1) VS (4V/div), b1) ∆VOUT (2V/div) @ dV/dt= 60V/µs;

a2) VS (4V/div); b2) ∆VOUT (2V/div) @ dV/dt= 300V/µs;

Time scale 500 ns/div.

The problem as been investigated with additional tests and simulations (see Fig. 2.11): a

charge injection phenomenon from the substrate into the n- epi pocket has been identified.

In fact, when VS=300V, J3 is reverse biased and the junction capacitance stores a large

amount of charge. When VS drops to 0V a positive charge is injected in the epi from J3: the

higher the dV/dt, the higher the current required to deplete the charge. Considering that the

capacitance of a p- sub/n- epi junction (J3 in Fig. 2.5) decreases with the applied reverse

32

voltage, the main amount of charge injection can be evaluated with a limited swing

(0-30V). With the available instrumentation it was also possible to change the dV/dt up to

1V/ns.

Figure 2.11. Spectre® voltage waveform for negative swing:

c1) VS (7.5V/div); d1) VOUT (7.5V/div) @ dV/dt=60V/µs;

c2) VS (7.5V/div); d2) VOUT (7.5V/div) @ dV/dt=300V/µs;

Time scale 1µs/div.

The problem was due to the fact that the bias for the n- epi pocket was provided by a

source-follower stage (MOSFET M1 in Fig. 2.8): this type of output stage is able to source

current, but not to sink it. Therefore, this charge injection increased the value of VOUT. The

peak amplitude on VOUT could be reduced by increasing the current sunk by the load.

Moreover, as one can see in Fig. 2.10 and Fig. 2.11, VOUT remained lower than 5V after the

end of the discharge phase. This behavior was due to a slew-rate problem on the

differential stage. In fact, if VOUT increases, the regulator loop tries to turn it at its right

working point. But for a value of VOUT higher than VB, loop control is lost. As the

regulator was not optimized for slewing, it needed some microseconds to recover this

error.

33

2.5 Improved output stage: description and simulations

In order to reduce and possibly eliminate the effect of the charge injection, an output stage

with improved current sink capability is needed. In particular, we focused on a class AB

output stage [13] which can be implemented by adding MOS M3 to the previous schematic

obtaining the one of Fig. 2.12. The current reference IBIAS, together with M4 and M5, acts

as biasing branch. These are 20V devices because the biasing branch has to withstand a

voltage higher than 5V.

Figure 2.12. Supply with class AB output stage.

Since we are mainly interested in evaluating the performance of the class AB output stage,

a simplified version of the LVFS was diffused (see Fig. 2.6), in order to save area. In

particular the bandgap reference was replaced with a simple voltage reference VREF

obtained using a polisilicon resistor (Rpoly2) in series to M6 in diode configuration. While

the precision of this internal reference in not comparable to the one of the bandgap, it is

still suitable for our purposes. However, the bandgap reference was improved with a

innovative technique for offset compensation and diffused in a separated test IC.

To understand how this scheme reduces the injection problem let us consider a current

injected in VOUT. This charge injection initially increases the value of VOUT. If the

regulation loop works correctly also the voltages on V- and VDIFF increase, raising the

34

overdrive of M3. Therefore, device M3 can sink the injected current, keeping VOUT at the

nominal value.

In order to test the current sink capabilities of the new output stage by the simulator, the

charge injection phenomenon has been modeled, measuring the junction capacitance of J3

on the first chip: all pads included in the n- epi pocket were shorted together and the

capacitance between these pads and the one connected to the p- sub was evaluated using a

FLUKE PM6306 LCR meter. The capacitance was about 110pF. A p/n junction was sized

trying to obtain the same capacitance value and it has been connected between VOUT and

VSS.

Figure 2.13. Simulation voltage waveforms for negative @ dV/dt=300V/µs:

VOUT (2V/div); VS (2V/div); Time scale 50 ns/div.

Fig. 2.13 shows the simulation results obtained under the worst conditions of

Fig. 2.10-2.11: the perturbation of VOUT and the duration of the phenomena were

significantly reduced. The value of VOUT is always above 2.5V: this is important to avoid

loss of information stored in an hypothetical logic part supplied by VOUT. Moreover the

positive peak has been reduced by about 80%. The total bias current required by the class

AB output stage in nominal DC conditions was about 0.3mA

35

2.6 Measurements setup and experimental results from the second

prototype

Simulations are promising, but the test bench is the only reliable way to test this new

solution since a precise model of the charge injection is not straightforward.

The first issue that has to be faced is the implementation of a good measurement setup, in

order to avoid the large noise coupling that typically affect this kind of environment and

thus could heavily affect our measurements. This is particularly true because of the high

dV/dt and the large swing used.

Figure 2.14. First experimental setup for measurements in switching conditions.

Figure 2.15. Example of negative ramp generated for VS: dV/dt=32.2 V/ns;

VS (50 V/div); Time scale 20 ns/div.

36

Exploiting a custom ramp generator (see Fig. 2.14), the experimental characterization was

performed under nominal working conditions: DC+=300V and dV/dt up to 32V/ns (see

Fig. 2.15). In particular, this very fast slope makes the measurements a difficult task.

Now a second problem is the generation of the floating supply VBS. The first setup used to

obtain our scope is reported in Fig. 2.14: a power supply has been used to generate

VBS=15V, referring is ground to the VS provided by the ramp generator.

To observe the VOUT generated by the IC together with the ramp applied to VS, a battery

TPS2014 oscilloscope with isolated channels has been used: in this way, each channel can

be referred to a different voltage node. The first experimental waveforms are reported in

Fig. 2.16.

(a) (b)

Figure 2.16. a) VOUT (5V/div DC coupling); VS (100V/div); b) VOUT (5V/div AC coupling);

VS (100V/div); Time scale 250 µs/div.

As can be seen, the generated VOUT=5V is maintained by the power supply even while

swinging VS between 0V and 600V. Moreover, the disturbances superimposed on the

generated output voltage, are lower than 500mV; thus disturbances are significantly

reduced with respect to those provided by the charge injection phenomenon in the first

prototype.

Unfortunately, moving on a reduced time scale an unwanted behavior is observed on the

same waveforms.

VOUT

VS

VOUT

VS

37

(a) (b)

Figure 2.17. VOUT (1V/div DC coupling); VS (50V/div); VB (1V/div); Time scale 250 µs/div.

As shown in Fig. 2.17a, the generated VS shows a ringing at the end of the ramp. The same

ringing is reported on VOUT making it unsuitable to be used as supply voltage for the

sensing circuit. But this unwanted behavior on VOUT could also be provided by the charge

injection problem highlighted in the previous prototype and it is what we want to evaluate

to understand if the class AB output stage works correctly. However, being a similar

disturbance observed also on VB (see Fig. 2.17b) the detected disturbance wouldn’t be a

charge injection problem.

A first hypothesis to justify these waveforms was that the disturbances observed both on

VS and VB were coupled to VOUT due to a bad power supply rejection ratio (PSRR) of the

designed circuit. To verify this first hypothesis, a sinusoidal signal with characteristics as

similar as possible to the observed disturbances (VSIN=10Vpp, f=13MHz) has been

imposed both on VB and VS, observing its influence on VOUT.

The experimental waveforms are reported in Fig. 2.18. As can be seen, the hypothesis of a

bad PSRR is not confirmed: in fact, measurements shows a good PSRR with a very low

residual noise on VOUT in both cases.

An alternative justification for the disturbance on VBS during the fast swing of VS can be

identified in the use of a GW GPC-3030DQ supply to generate the VBS. In fact, while the

negative terminal of this device can easily be referred to a desired voltage, it is uncommon

to stress it with a fast voltage slope which can create unwanted coupling between the

internal part of the device and the external environment.

VOUT

VS

VB AC coupled

VS

38

(a) (b)

Figure 2.18. PSRR: a) VSIN (5V/div AC coupling); VOUT (20mV/div AC coupling);

b) VSIN (5V/div AC coup); VOUT (100mV/div AC coup); VBS (500mV/div AC coup);

Time Scale (25ns/div).

Figure 2.19. New ways to generate the floating VBS.

This situation lead us to realize a new measurement setup [15], in which the floating VBS is

generated by either a bootstrap circuit as in the real application or a couple of stacked 9V

batteries (see Fig. 2.19) which would be quite insensible to a fast voltage slope applied to

their negative terminal. Moreover, since the oscilloscope used for the previous experiment

presents limited performances in term of bandwidth and sampling a battery operated

oscilloscope was used (Tektronix TDS3034B, 300MHz 2.5GS/s) where all channels have

now to be referred to the node voltage. The advantage of this instrument is that the ramp on

VOUT

VS VOUT

VS

VBS

39

VS is not seen as a common mode signal as with the TPS2014 oscilloscope, isolated

channels oscilloscope.

Nevertheless, all the capacitive couplings to ground and all other parasitics still have an

influence. To see their effects on the measurements during the voltage swing of node S,

refer to Fig. 2.20 where a test using a real bootstrap circuit has been performed: trace a)

shows the voltage waveform measured by a probe connected between nodes B and S,

while trace b) shows the waveform seen by a second probe with both the terminals

connected to just node S. (called VSHORT). In principle, this second trace should have been

zero, while the acquired waveform is practically the same as the disturbance superimposed

on the DC level of the first trace. This allows to conclude that most part of the disturbances

highlighted by a direct measurement of VBS are not real. It is possible to get the same

conclusion watching the waveforms obtained using a 9V battery to generate the VBS (also

shown in Fig. 2.20).

Real bootstrap circuit Single 9V battery

Figure 2.20. Generated VBS

a) VSHORT (5V/div); b) VBS (5V/div); c) math channel=VBS-VSHORT (10V/div);

d) VSHORT (2V/div); e) VBS (2V/div); f) math channel=VBS-VSHORT (2V/div);

Time scale 100 ns/div.

Furthermore, this conclusion is coherent with the negligible variations one would expect to

see on the voltage generated by either a bootstrap circuit or a battery, even if the potential

of one of its terminals is exposed to a fast voltage swing. Concluding, the real behavior of

VBS was obtained by subtracting VSHORT to the directly measured VBS. The result is shown

b

a

c f

d

e

40

by the math traces in Fig. 2.20. As mentioned before, the more the disturbances on the two

channels are similar, the more this waveform is realistic.

Figure 2.21. Board used for the measurements.

Thus for the final measurement, the input voltage for the LVFS was obtained by

connecting two 9V batteries in series. As Fig. 2.21 shows, the experimental setup was kept

as compact as possible: the two 9V batteries were placed right under the board and the

length of the cables was minimized. The probe wires were twisted and followed paths as

similar as possible, so that couplings to ground for both probes are similar. This last aspect

was crucial for the above explained measurement approach.

Figure 2.22. Supply output VOUT:

g) VOUT (5 V/div); h) VSHORT (5 V/div); j): math channel=VOUT-VSHORT (1V/div);

Time scale 40 ns/div.

j

h

g

41

The same considerations reported to explain the waveforms in Fig. 20, can apply to the

output voltage VOUT. The directly measured VOUT, the corresponding VSHORT and the

reconstructed VOUT are given in Fig. 2.22. As it can be seen, the residual noise on VOUT is

much smaller than with the class A output stage.

Not only this small ripple cannot make the LVFS to fail, but its entity and time duration are

perfectly compatible with the application requirements.

42

2.7 Bandgap voltage reference for high side floating pocket

Since the feasibility of the floating supply was demonstrated, we decided to continue also

with the development of a bandgap voltage reference. As seen before, the proposed

floating supply requires a voltage reference for the Opamp within its regulation loop. The

implementation of this reference using a resistor and a diode connected MOS is the easiest

way to obtain the desired reference but at the cost of a lower precision in the generated

voltage value.

The bandgap is the most common CMOS voltage reference. It is a derivation of bipolar

bandgap architectures exploiting a parasitic lateral BJT [15-18] and is used to provide a

voltage output which has minimum dependence on temperature variation. In the

meanwhile, the adopted junction isolated high voltage technology has been updated with

the implementation of 3.3V instead of 5V low voltage devices for signal processing parts.

Therefore the bandgap has been developed with this new CMOS devices.

Figure 2.23. Silicon profile of npn bipolar transistor

Figure 2.24. Basic structure of bandgap reference available in the floating epi.

43

The pnp device is not usable in our circuit: in fact, we need to implement the bandgap

inside the floating pocket while the pnp exploits the p- substrate as collector terminal.

Therefore, the npn bipolar transistor is used. This device has its collector connected to the

supply voltage (see Fig. 2.23 and 2.24) of the floating n- epi, because it exploits the epi

itself as collector. Therefore, it is supplied directly by the VOUT generated by the floating

supply circuit.

The basic topology usable for the bandgap circuit is the one reported in Fig. 2.24 (note that

VDD=VOUT).

In general, it is known that, if two BJTs operate at unequal current densities, the difference

between their base-emitter voltages is directly proportional to the absolute temperature. It

is also recognized that the base-emitter voltage of BJTs (forward voltage of a pn junction)

exhibits a negative temperature coefficient (TC) [19]. In Fig. 2, the area of transistor Q2 is

a multiple of the area of Q1 and they are biased by the same current which is regulated by

choosing the value of resistors indicated as R. Resistor Rb is used to trim the curvature of

the output voltage (VBG) versus temperature. In fact, VBG can be written as:

)RbR(1∆VVV BEBE2BG +⋅+= (4)

Therefore, in (1) it is possible to compensate the behaviour of the VBE2 versus temperature

by trimming of coefficient of ∆VBE.

2.8 Sources of error in a bandgap voltage reference

Common process and supply variations can introduce an error on the generated reference

[20]. A very relevant problem that usually affects a bandgap reference are the offset

between the input terminals of the Opamp (indicated as VOFF1 in Fig. 2.24) and the offset

due to the mismatch between resistors R (indicated as VOFF2 in Fig. 2.24) which causes a

mismatch between the bias currents of the reference diodes [21].

These are recognized as the biggest influence on the precision of output voltage, thus

changing both the absolute output value and its curvature versus temperature

Different types of compensation techniques have been presented up to now [22, 23]. The

proposed topology of bandgap reference which a simple technique [24] based on a sample

44

and hold (S&H) stage to cancel the aforementioned effects. This compensation technique

does not depend on the properties of this technology and it can be used in a plain CMOS

bandgap reference as well. Other techniques are used to compensate second and higher

order effects (i.e. finite input resistance of the base in the BJTs) which are not our goal.

Some of these exploits an external trimming which modify the resistors value changing the

residual bandgap curvature. This solution is really effective but has also a really high cost,

since external bits are needed for the trimming.

To implement the desired offset compensation technique some modifications of the basic

circuit of Fig. 2.24 have to be done as explain in next paragraph.

2.9 Implemented bandgap circuit

In order to understand the offset compensation technique that has been implemented for

the circuit and will be analytically explained in the following, it is necessary to show the

changes that were implemented on basic bandgap circuit of Fig. 2.24: the modified

operational amplifier and the new bandgap structure are reported in Fig. 2.25 and Fig. 2.26

respectively.

The amplifier (see Fig. 25) was modified by introducing an auxiliary input stage,

implemented by MOS M1, M2 and M3, and two capacitors with same value, indicated as

C1 and C2; all resistors are made of polysilicon.

plus_aux

minus_aux

Figure 2.25. Opamp1: modified Opamp with auxiliary input stage.

45

Figure 2.26. Proposed topology of bandgap reference including S&H and switches.

Moreover, as shown in Fig. 2.26, a S&H stage including a switch, a capacitor (CHOLD) and

a buffer stage (Opamp2) stores the value of VBG evaluated during the normal operation

phase and holds it during the compensation phase. Opamp2, used in buffer configuration,

is a simple two stages scheme with differential input pair and common source second gain

stage. Devices Q1 and Q2 were chosen as a square array of equal elements, providing a

matched block during layout phase. Few switches have also been introduced in the circuit.

They are used to change the configuration of the circuit during the phase when offsets are

read and stored (indicated as compensation phase in the following) and the phase of normal

operation (when the bandgap loop is restored).

Since switched capacitors (C1 and C2 in Fig. 2.26) are used to store the offset components,

a clock with three non overlapping phases is needed to drive the switches (see Fig. 2.27).

In the test chip, these signals were generated exploiting standard library blocks and the

duration of T was few tens of µs. However, the value of T is not a critical parameter and if

the bandgap would be used in another applications (such as switched capacitors circuits or

ADCs), in which clock signals are already present, these signals can be used and there is

no need for any additional block.

46

Figure 2.27. Timing signal: O: compensation phase; N: normal operation phase;

O_a and O_b: select the two parts in which the compensation phase is divided.

Clock

INV

INV INV

INV

R R

Figure 2.28. Transmission gate with clock feedthrough compensation.

Signal N is used to select normal operation; when the circuit act as bandgap. Signal O is

used to select the compensation phase and is split in two parts, O_a and O_b. The critical

switches (which both have one of their terminals connected to the capacitors used to store

the offset components) were designed trying to minimize charge injection during their turn

off: as show in Fig. 2.28, two dummy MOS (with source and drain terminals shorted

together) were added to the drain and the source terminals of the n channel and the

p channel which constitute the transmission-gate, to compensate the injected charge (clock

feedthrough compensation).

47

2.10 Analytical description of the proposed offset compensation technique

It is very important understand how the proposed offset compensation technique works

because it is the key of the proposed bandgap architecture and it presents a innovation with

respect with other offset compensation technique patented or available in literature.

To understand the ideal schemes that will be reported in the following let us explain what

part of the circuit are included in the ideal blocks and provide some other definition:

• A1 Input pair of Opamp1

• AAUX Auxiliary input stage of Opamp1, constituted of M1, M2, M3

• A2 Second gain stage of Opamp1

• VE Common mode voltage provided by the emitter terminals of BJTs

Figure 2.29. Equivalent circuit for compensation phase.

During the compensation phase, the various offset voltages are charged on the capacitor C1

and C2: to understand the necessity to split this phase in two parts, consider the equivalent

circuit in Fig. 2.29 and the circuit of Fig. 2.26. During this phase, switch N is open: thus,

two equal BJTs are used to bias the resistor R with equal currents keeping nodes x1 and x2

at the same voltage (VE) and to read the offsets VOFF1 and VOFF2. The BJTs base terminals

are biased by the bandgap value stored by the S&H (VBG2) during the normal operation.

The auxiliary input stage and the second gain stage of Opamp are in a buffer configuration

to store the offset components on C1 and C2. Also the non inverting input of AAUX is

biased by VBG2.

48

Since the two equal BJTs used in this phase could be affected by a process mismatch, they

could provide different emitter voltage introducing an additional offset indicated as VOFF3.

Being this offset component not present during normal operation, it should not be stored

stored on C1 and C2; therefore, the emitter voltages are swapped when O_a goes low and

O_b goes high; consequently VOFF3 is stored with opposite sign on the capacitors C1 and

C2, while VOFF1 and VOFF2 are stored with the same sign. The charges stored on the

capacitors due to the offset components are:

( )[ ]AUX221OFF3OFF2OFF1C2 AAAA)VV(VV ⋅⋅⋅−+= (5) ( )[ ]AUX221OFF3OFF2OFF1C1 AAAA)VV(VV ⋅⋅⋅++= (6)

Figure 2.30. Equivalent circuit for normal operation phase.

The equivalent circuit during the normal operation is reported in Fig. 2.30. The effective

bandgap loop is restored; now C1 and C2 are in parallel and their charges add together:

QTOT = Q1+Q2 = 2C · (VOFF1 + VOFF2 + VOFF3 - VOFF3) A1·A2/(A2 · AAUX) (7)

As a result the components due to VOFF3 are cancelled. On the inverting input of AAUX

there is a voltage:

VC = QTOT/CP = .AA)V(VV AUX1OFF2OFF1C ⋅+= (8)

49

Consequently, the theoretical residual offset on VBG after the compensation phase is:

0.)A(AV)A(A)V(V AUX2C21OFF2OFF1 =⋅⋅−⋅⋅+ (9)

Thus, all the considered offset components that could influence the characteristics of VBG

have been eliminated. Some problems could occur if there is a mismatch between C1 and

C2. Given ∆C as the difference between the values of the capacitors C1 and C2, it is

possible to work out that the introduced error is proportional to the ratio ∆C/2C and it is

consequently negligible. In fact, a good matching between the capacitor in layout phase

and the insertion of dummy elements could minimize the problem. (the error could be

about 0,1%). The input offset for the buffer was not compensated in this release of the

circuit: however, it does not influence the curvature of the generated reference, but it only

could impose a shift of few millivolts between VBG and its replica VBG2. It will be taken in

consideration in a future version of the circuit.

2.11 Simulation results

The most relevant simulation in Spectre® environment was the analysis of the bandgap

output voltage versus the operating temperature. Moreover, to prove the effectiveness of

the proposed offset compensation technique, the analysis versus temperature was

performed while introducing both an offset between the input terminal of Opamp through

an ideal voltage source and a mismatch between the value of resistors R.

The added offset values fell in the interval 10mV≤VOFF1≤10mV, while the maximum

mismatch between resistors R (whose nominal value was 110kΩ) was 5%: this value is

very low for the common spread that normally affects a process. However a particular

layout structure has been used dividing resistors R in different modules and disposing them

in order to obtain the best matching. Curves for these simulations are reported in Fig. 2.31.

The precision of VBG is 12.7ppm/°C. The spread for the corner curves, which includes the

effect of the offsets, the variation of MOSFETs, resistors and capacitor models and the

variation of the supply voltage, is negligible. The residual offset value between node x1 and

x2 is reduced to 30µV (see Fig. 2.32).

50

1,2213

1,2215

1,2217

1,2219

1,2221

1,2223

1,2225

1,2227

1,2229

-40 -20 0 20 40 60 80 100 120 140 160

Figure. 2.31 VBG vs. Temperature: simulation parameters indicated.

.

Figure 2.32 Residual offset between x1 and x2 node after the compensation.

51

70 mV

VBG(V)

Figure 2.33 Bandgap output VBG with before and after offset compensation.

Figure 2.34 Zoom of Figure 2.33: VBG spread after compensation.

52

In the same circuit without offset compensation, the precision of the reference was about

245ppm/°C and the deviation of the corner curves from the ideal one was about 16% (see

Fig. 2.33 and 2.34).

The residual curvature is due to the characteristic of polysilicon resistor versus

temperature. A start-up circuit was necessary to pre-charge the capacitor CHOLD at the

circuit turn-on: a simple voltage divider brought the capacitor to a voltage near to 1.2V

allowing the first compensation phase to work correctly. After the first cycle the start-up

circuit was disconnected.

The total power consumption was about 150µW: the current required by the S&H buffer

stage increased the power consumption of the circuit by about 15%.

However, without the introduction of any offset compensation technique, a way to reduce

the offset of the Opamp is to size the input MOS significantly larger than in the present

case: but in this way area consumption limitation comes into play, and it is impossible to

achieve an offset <<1mV.

References

[1] M. Grasso, S. Morini, A. Rugginenti, “Input filter for A.C. motor phase current sensing,” Patent: US.6828753B2 - 7/12/2004.

[2] E. Persson, “A new approach to motor drive current measurement,” in Proc. IEEE International Conference on Power Electronics and Drive Systems, 2001, pp. 231-234.

[3] D. Giacomini, E. Bianconi, E. Martino, M. Palma, “A Fully integrated power module for three phase servo motor drive applications,” in Proc. IEEE Industry Applications Conference, 2001, pp. 981-987.

[4] H. Kim, T. M. Jahns, “Phase current reconstruction for AC motor drives using a DC link single current sensor and measurement voltage vectors”, IEEE Trans. Power Electronics, vol. 21, no. 5, pp. 1413-1419, September 2006.

[5] H. Kim, T. M. Jahns, “Current control for AC motor drives using a single DC-link current sensor and measurement voltage vectors,” IEEE Trans. Ind. Applications, vol. 42, pp. 1539-1547, November/December 2006.

[6] B. Saritha, P. A. Janakiraman, “Sinusoidal three-phase current reconstruction and control using a DC-link current sensor and curve-fitting observer,” IEEE Trans. Industrial Electronics, vol. 54, pp. 2657-2664, October 2007.

[7] V. Mangtani, “Circuit for sensing individual leg current in a motor controller using resistive shunts,” Patent: U.S.5825641 – 20/10/1998.

53

[8] S. Chakrabarti, T. M. Jahns, R. D. Lorenz, “Current regulation for surface permanent-magnet synchronous motor drives using integrate current sensor in low-side switches,” IEEE Trans. Ind. Applications, vol. 42, pp. 1080-1091, July/August 2006.

[9] J. Crébier, N. Rouger, “Loss free gate driver unipolar power supply for high side power transistors,” IEEE Trans. Power Electronics, vol. 23, no. 3, pp. 1565-1573, May 2008.

[10] S. Park, T. M. Jahns, “A self-boost charge pump topology for a gate drive high-side power supply,” IEEE Trans. Power Electronics, vol. 20, no. 2, pp. 300-307, March 2005.

[11] Y. Yin, R. Zane, “Integrated results for dual low voltage IC based high and low side gate drive,” in Proc. IEEE Applied Power Electronics Conference, 2005, pp. 759–765.

[12] E. Dallago, S. Ruzza, G. Venchi, M. Grasso and S. Morini, “A fully integrated floating power supply for high voltage technologies including n-epi biasing,” in Proc. IEEE Power Electronics Specialists Conference, 2006. pp. 1-5.

[13] E. Dallago, S. Ruzza, G. Venchi, S. Morini “Low voltage floating supply in monolithic high voltage technology for high dV/dt applications”, in Proc. IEEE Power Electronics Specialists Conference, 2007, pp. 1024 – 1028.

[14] S. Ruzza, E. Dallago, G. Venchi, S. Morini, “Integrated low voltage floating power supply in high voltage technology for high dV/dt applications” accepted for publication on the IEEE Transactions on Power Electronics.

[15] R. J. Widlar, “New development in Ic voltage regulators,” IEEE J. Solid State Circuits , vol. SC-6, pp. 2-7, Feb. 1971.

[16] A. Paul Brokaw, “A simple three terminal IC bandgap reference,” IEEE J. Solid State Circuits, vol. SC-9, pp. 288-293, Dec. 1974

[17] Y. P. Tsividis and R. Hulmer, “A CMOS voltage reference,” IEEE J. Solid State Circuits, vol. SC-13, pp. 774-778, Dec. 1978

[18] R. W. Ye and Y. P. Tsividis, “Bandgap voltage reference sources in CMOS technology,” IEE Electronics Letters, vol. 18, pp. 24-25, Jan. 1982.

[19] B. Razavi, “Design of analog CMOS integrated circuits” McGraw-Hill international edition.

[20] J. Michejda and S. K. Kim, “A precision CMOS bandgap reference,” IEEE J. Solid State Circuits, vol. SC-19, pp. 1014-1021, Dec. 1984.

[21] P. G. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and design of analog integrated circuits”, 4th edition. USA: Wiley 2001.

[22] B. Song and P. R. Gray, “A precision curvature compensated CMOS bandgap reference,” IEEE J. Solid State Circuits, vol. SC-18, pp. 634-643, Dec. 1983.

[23] S. Ying, L. Wengao, C. Zhongjian, G. Jun, T. Ju and J. Lijiu, “A precise compensated bandgap reference without resistor,” Proc. International Conference on Solid-State and Integrated Circuits Technology, 2004, vol.2, pp. 1583-1586

[24] S. Ruzza, E. Dallago, G. Venchi, S. Morini, “An offset compensation technique for bandgap voltage reference in CMOS technology”, Proc. IEEE International Symposium on Circuits and Systems, 2008, pp. 2226-2229.

54

3. Fast-responding integrated over-current detector for

motor drive applications

This chapter presents an over-current detector for motor drive application in junction

isolated high voltage technology. The goal of the IC is the detection of different types of

faults which can affect a triphase inverter used in motor drives applications. Different

solutions available in literature are considered and the proposed solution is largely

detailed.

The proposed circuit, detects the over-current condition due to a fault sensing a shunt

resistor on the DC+ bus of the inverter and communicates it to the DSP using an open

drain output pin.

To the lest of author’ s knowledge this is the first integrated fault detector presented up to

now. It is cheap and has a simple structure and can be used in application with the inverter

DC+ bus up to 600V. Moreover it exploits an innovative solution of high voltage level

shifter for the communication over the two epi pockets. The designed circuit and the most

significant simulations are reported. Experimental characterization performed on the

prototype confirms the desired performances.

55

3.1 Introduction

In voltage source inverter used in electrical drives in the kilowatt range, the prevention of

motor and inverter faults is an hot topic. In fact, due to the current and voltage values

available in these application a fault can be very dangerous both for the devices, which can

result permanently damaged, and for the operators who is working on it.

CrAC line Motor

Figure 3.1 Basic scheme of an electrical drive.

First of all, let ‘s go to consider some types of fault which can happens in a electrical drive:

as can be seen in Fig. 3.1 the system is made of a bridge rectifier, for the rectification of

the AC line voltage, a capacitor to reduce the ripple on the generated DC+ bus value and

three-phase inverter.

The first examples of fault that have been considered were the short on a inverter leg and

the short between two motor phases (indicated by the “s” switch in Fig. 3.2) which cause

the current to flow in the paths reported in dotted and in grey respectively. As it can be

seen, these current path can be cross the shunt on the DC- bus (shunt1), which is often used

for the current feedback needed for the microcontroller to realize the motor torque and

speed control [1-4].

Figure 3.2 Fault conditions detectable using shunt1 on DC- bus.

56

An approach reported in literature exploits the algorithm used for the motor control (e.g.

identifying the current vector trajectory) [5, 6] to get fault condition.

Since for both these method the value of three phase currents has to be reconstructed, the

main disadvantage of these solutions is that at least one switching period (the one of the

PWM fundamental frequency) to detect the fault condition is required: unfortunately,

considering the typical switching frequencies (10-16kHz), this time can become too long

(62.5-100µs), leading the system to a permanent damage, in particular from the power

switches point of view: in fact, some IGBTs/MOSFETs family can reach an over-current

condition only for few microseconds.

Another way to get information about a fault condition is to sense the voltage drop on the

low side switches that constitutes the inverter [7, 8]: this solution can be also implemented

inside modern gate driver ICs and is called desaturation protection.

Unfortunately, there are fault conditions which can not be detected with these solutions. In

fact, let us consider other types of fault: the first one is due to a short between the DC+ bus

and the motor frame, indicated by the “a” switch, providing the dotted current path. The

second fault condition is due to a short between a motor phase and the motor frame: it is

indicated by the “b” switch and the current path is indicated in grey. Being the motor frame

usually connected to ground, these current path does not cross neither the shunt1 on the

DC- bus nor the low-side switches of the inverter.

DC+ bus

DC- bus

Motor

a

b

shunt1

shunt2

Figure 3.3 Fault conditions detectable only using shunt2 on DC+ bus.

Therefore, they can be detected only sensing a shunt resistor (shunt2 in Fig. 3.3) placed on

the DC+ bus of the inverter. It is easy to observe that the need to detect a data referred to

57

DC+ bus makes the detection of these types of fault difficult task compared to the fault

detection based on the DC- bus: in fact, using shunt2, it is necessary to detect a signal

whose amplitude is up to few hundred of millivolts rejecting the DC+ bus value (300 or

600V). on the other hand the a signal on shunt1 would allow to exploits a very simple low

voltage circuit referred to ground.

An example of over-current detector used in industrial and consumer applications and

based on the use of discrete components is reported in Fig 3.4. It uses a power npn BJT,

some resistors, a Zener diode and a comparator (Comp_A). The BJT is used as sensing

device: in fact, the voltage drop on the shunt2 is filtered and imposed between the base and

the emitter terminals of the BJT. Thus, an eventual over-current condition turns the BJT on

raising, through its collector terminal, the voltage on the Zener diode. Therefore, the fault

signal triggers CompA which provides the fault bit to the DSP. The reference voltage for

CompA is also generated on the board. These solutions presents few discrete elements and

a very simple structure. Unfortunately, these advantages are paid with low reliability, area

consumption on the board and noise coupling which become an issue, due to the large

noise which normally affect these applications.

Figure 3.4. Example of detector using discrete components.

Other adopted solutions are implemented using two separated ICs which communicate

through either linear optocoupler devices or a transformer, which guarantee galvanic

58

insulation rejecting the common mode value given by the DC+ bus voltage (300 or 600V).

Finally, Hall effect sensors can be used to transduce the bus current. The main

disadvantage of these approaches is the significant impact they have on the cost of the

considered system.

3.2 Propose idea of integrated over-current detector

The proposed solution consists of a fully integrated scheme a floating sensing part which

sense the DC+ bus and a ground referred part which communicate with the control, both

diffused on a single IC, as reported in Fig. 3.5.

Figure 3.5 Idea of integrated over-current detector.

The fault is detected from the floating epi and is communicated to the LV zone using a

p channel DMOS. The low voltage zone communicates the fault condition through an open

drain output to the DSP and receives a reset signal (RST) from it.

With this type of approach the noise coupling issue would be largely reduced and the use

of expensive interface is avoided. To be competitive with the solution of Fig. 3.4, it is also

important to keep power consumption very low, to use a really small and cheap package,

and avoid the use of an external power supply.

59

3.3 Implemented high voltage power supply

The generation of the internal supplies is the first issue that has to be faced in the

implementation of the proposed IC. Being the signal processing parts of the IC

implemented with 20V MOS in both pockets, a supply voltage as high as 15V has to be

generated both for the LS and the HS of the IC.

Let us focus the attention at first on the HS. As seen in the previous chapter, the HS of

these ICs is typically feed using an external bootstrap capacitor. In this application, the HS

doesn’t have to move referred to the floating ground, but remains referred to the DC+ bus

voltage value to sense shunt2. Thus, the bootstrap capacitor already present to feed the

gate driver can not be exploited for our purpose.

DMOS_1

DC+ bus

R4

R5

R6

pmos_1

pmos_2

Rring

FG

IbiasHV

Figure 3.6 Generation of the internal floating ground.

However, since the current consumption inside the HS has to be largely lower than 100µA,

in order to limit power consumption, a fully integrated structure can be realized which

.generates the needed supply with a simple regulator that generates a voltage value FG few

Volts below the DC+ bus value. The implemented circuit [9] is reported in Fig. 3.6. As can

be seen it exploits a p channel DMOS _1 which can withstand a VDS and a VGD voltage

value up to 600V.

60

The FG point is maintained at about 12 Volts by the current flowing in the right branch of

the supply. The voltage drop across the Zener diodes, plus the voltage drop across R4 add

to make FG: this gives about 10V plus the threshold of pmos_1 (about 1.5V). The FG

value is regulated through a feedback mechanism as follows: say the FG value decreases

for some reason above its steady state value. This causes the voltage across R4 to increase,

causing pmos1 to turn on stronger, which then causes the gate node voltage of DMOS_1 to

increase. Therefore a reduction of the drain current of the DMOS_1 occurs, closing the

feedback loop by causing a raising on the FG value, which return at its starting value. The

opposite situation results if the change on the FG value is opposite.

The circuit includes also an additional feedback to obtain a short circuit (or over-current

protection) which turn-off the supply circuit if short problem happens inside the floating

pocket. The pmos_2 device senses the bias current through resistor R5: if an over-current

occurs, the source to gate voltage of the device increases and its drain raises the gate

voltage of the DMOS. Therefore, a reduction of the current which flows in R5 occurs. In

this way, the Power supply for the HS of the IC has been implemented: the current

consumption of the power supply stand alone is about 30uA at which the current

consumption of the HS circuits has to be added.

The supply VDD for the LV pocket can be generated using the complementary circuit.

3.4 High voltage level shifting for fault communication

In junction isolated technologies, the communication of a bit between the HS and the LS,

or in general over two pockets which have different reference nodes, is typically

implemented using short current pulses, in order to reduce the power dissipation. In fact,

these pulses carry a current whose amplitude can be up 50mA flowing between the two

buses whose voltage difference can be up to 600V.

The classical solution of transmitter and receiver system is implemented exploiting an high

voltage level shifter [10-12], whose basic structure is reported in Fig. 3.7. If the data has to

be communicated from high to the low voltage pocket, the current pulses are provided by

the p channel DMOS (HVp1) available in the HS. The provided current pulses is detected

in the LS of the IC clamping the raise of the drain terminal through a Zener diode (D1) and

triggering a flip-flop implemented in the low side of the IC. To keep the power

61

consumption as low as possible, a single current pulse is normally used to provide the Set

signal to the flip flop, which maintains the information as long as it is needed (for example

as long as a fault condition persists in the considered application); a second p channel

DMOS (HVp2) and a second Zener (D2) are needed to provide the Reset signal to the

flip-flop. Alternatively, the current pulses can be periodically repeated as long as needed,

avoiding the use of a flip-flop. Unfortunately, this last solution causes area and power

consumption inside the high side since an oscillator is needed and the power dissipation

increases because of the multiple current pulses. Moreover, an hard trade off between the

pulses timing and power consumption has to be evaluated: in fact, if consecutive pulses are

keep too far (in time) the fault condition could be communicated when the system is

already damaged. On the contrary, the use of multiple pulses very close in time, would lead

to a too large power dissipation.

HVp1

S

DC+ bus

HVp2

R

D1 D2

Figure 3.7 Basic scheme of classical high voltage level shifter.

A way to overcome this difficult trade off would be the use of a continuous time

transmission which start when the over-current condition is detected and stand for all its

duration. This solution has been studied and a circuit structure which exploits parts already

present in the IC has been implemented. It is explained in the next paragraph.

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3.5 Low losses continuous-time level shifting technique

The implemented level shifting technique [13], takes advantage of the power supply circuit

already present in the circuit to generate the supply voltage for the floating pocket. In

Fig. 3.6 a current IBIASHV is indicated: it is the sum of the quiescent current of the supply’s

leg, which include the DMOS, and the quiescent current of the sensing circuits inside the

floating pocket. The proposed level shifting technique uses this bias current to

communicate the bit of the over-current condition to the LS, exploiting the fact that this

current has to close to ground through the LS.

Figure 3.8 Proposed level shifting scheme.

As it can be seen in Fig. 3.8, an additional HV devices (DMOS_2) and two Zener

diodes(D1 and D2) are added to the structure of Fig. 3.6; a simplified circuitry have also

been included for the HS and the LS of the IC.

The basic idea is to divert the IBIASHV current into either D1 or D2, depending on the

system state. When the over-current condition is detected, Comp1 diverts IBIASHV in the

HV_pmos2: thus, the voltage on D2 raises, triggering a Comp2 which drives an open drain

63

output (OD). This condition is automatically maintained until the over-current remains,

making a flip-flop or a train of pulses useless.

With this approach, a single p channel DMOS has to be added to the circuit (which

includes two DMOS and two Zener as the solution of Fig. 3.7), the bias current of the HS

pocket remains the same and no additional power dissipation occurs during the data

transmission, since no extra current is required.

3.6 Complete over-current detector IC

The complete schematic of the implemented over-current detector is reported in Fig. 3.9

and has been presented in [14]. Three fundamental parts can be identified: the first is the

sensing circuitry diffused into the HS. The second is a very simple digital logic and an

open drain output inside in the LV pocket to interface the realized IC with the DSP.

Finally, the power supplies and the level shifter presented in the previous chapter have not

been included in Fig. 3.9 for convenience: the level shifter is here reported in a simplify

scheme which consist in a transmitter and a receiver blocks.

The sensing circuitry is implemented using an operational amplifier (Opamp) in inverting

configuration and a comparator (Comp1). The non-inverting input of Opamp is connected

directly to the DC+ bus which acts as voltage reference. Resistors R1 and R2, which set the

Opamp gain, have been put off chip allowing the customer to regulate the threshold for the

over-current condition: in this way it is possible to set the minimum over-current signal

which has to be detected by Comp1. The comparator has been implemented introducing an

hysteresis that avoids multiple transmissions of the fault condition. The schematics of the

Opamp and of Comp1 will be reported in following.

The LS circuitry is implemented using a comparator (Comp2) whose input terminal senses

the voltage on the two Zener diodes which are used to detect the current paths as explained

before. A Logic block is also present, which includes a latch and few CMOS logic gates.

The LS is interfaced with the DSP through the Open Drain (OD) and the Reset (RST) pins:

the OD communicates the fault condition to the DSP, while the RST receives a signal form

the DSP which restore the normal condition after a fault.

Moreover two external capacitors (C1 and C2) are also added to the system, whose goal is

to reduce noise coupling on the internal generated supplies.

64

OD

RST

Vdd

Vss

DC+

IN-

Op

out

FG

Opamp

R1

R2

+

_

D1

shunt2

I

Logic

DSP supply

R3

Open Drain

DSP

R R

Transmitter

block

Comp2

DC+ bus

D2

D3

Comp1

Receiver blockout1

out2

Vin

C1

C2

Figure 3.9 Implemented Over-current detector with adopted pinout (IC inside bold line).

The amplifier Opamp1 has been implemented as a simple two stages scheme with a source

follower as output stage. The resistor value has to be kept in the order of kohm, in order to

avoid high impedance nodes which would increase noise coupling. With this value of

65

resistor, the bias current that has to be provided by Opamp output node (out1) is in the

order of tens of microampere and therefore a source follower is needed.

Moreover, in order to limit the current consumption, no offset compensation was

implemented for Opamp1; thus, a great attention has to be paid in sizing the input stage of

the Opamp: in fact, an eventual input offset would be amplified by the same ratio R2/R1

used for the input signal, changing the value of the chosen threshold. Since the offset

decrease with the square root of the input pair area, a large input pair has been

implemented.

The comparator Comp1 is also based on a simple two stage scheme (see Fig. 3.10), with

n channel input differential pair and a common drain as second gain stage. To make the

sensing circuit less sensitive to noise on Vin an hysteresis has been introduced in the

comparator. This feature was obtained with the block highlighted with dotted line in

Fig. 3.10. The voltage provided by a Zener diode was split using a resistive partitioning

and two voltage thresholds Vp and Vm were created: when the output of the comparator is

high Vp is reported as a reference voltage (ref) on the comparator input, while the opposite

happens when the comparator output is low.

Figure 3.10a Schematic of Comp1.

66

3.7 Simulation results

As mentioned previously, the power consumption is one of the most important issues for

the proposed IC. The used SO8 package is really inexpensive and small (5 × 6.2 mm2)

package, but it has a high thermal resistance (130°C/W). For the considered applications,

the maximum working temperature is TAMB MAX =125°C, while the silicon can reach

TJ MAX=150°C. With these data it is possible to calculate the maximum bias current usable

in the circuit.

In fact, if

C25TTT MAXAMBMAXJ °=−=∆ (1)

than the maximum power consumption for the package is:

mW192WC130

C25PMAX =

°°= (2)

Therefore, being the DC+ bus voltage as much as 600V, the maximum current usable in

the circuit is:

Aµ320V600

mW192I MAX == (3)

Simulation showed that the total IC current consumption is about 170uA giving a good

margin with respect to the calculated IMAX . The external resistors R1 and R2 can be chosen

by the customer to change the gain of the input amplifier in the range 10÷50. With these

two gain values, the minimum Vin values detected as an over-current are 250mV and

52mV respectively.

For comparator Comp1 an hysteresis of 50mV has been included in order to prevent

multiple fault transmission. The open-drain MOSFET device used as output pin, is

connected through resistor R3 to the DSP supply. As mentioned before, the Logic block

includes a latch which is used to maintain the bit of the detected fault condition until the

DSP resets it through the RST signal.

67

Two significant simulations which can help to understand how the IC work are reported in

Fig. 3.11 and 3.12. The values of the external resistors are R1=5kΩ and R2=200kΩ,

providing a minimum value of Vin=52mV detected as an over-current.

Figure 3.11 Voltage waveforms on the key nodes of the circuit during over-current condition.

Figure 3.12 Response time as a function of Vin.

68

The first simulation (see Fig. 3.11) shows the waveforms at the most significant node of

the circuit when an over-current is detected. When a voltage drop Vin=65mV is detected

on shunt2, this signal is amplified by the Opamp whose output signal (out1) falls by about

3V from its bias voltage value. This condition is detected by Comp1 which changes its

state and its output node goes high, changing the path followed by the IBIASHV. Therefore,

this change is detected by the comparator Comp2 in the LS, whose output node goes high

turning on the Open Drain. As can be seen, the over-current condition remains latched until

the signal RST (provides by the DSP) resets the latch inside the Logic block.

The second simulation (see Fig. 3.12) presents a really important feature of the proposed

IC. As said before, some types of fault involves the inverter’s power switches in their

current path: unfortunately this devices, can withstand an eventual over-current condition

only for a limited time. In particular for the last family of IGBTs and MOSFETs (called

Trench), which are widely used in motor drive, this time has to be lower than few µs. It is

possible to see how the response time of the IC is reduced as the amplitude of Vin

increases: in fact, a larger value of Vin provides a larger unbalancing on the input of

Comp1, increasing its commutation speed. In any conditions the delay of the circuit

remains lower than 3µs, also for corner case simulations where the MOS, resistor and

capacitance models are randomly changed together with the temperature.

69

3.8 Implemented IC and experimental characterization

The layout of the implemented circuit is shown in Fig. 3.13 while the performance and the

feature of the IC are reported in Table.I.

Figure 3.13 Layout of the implemented IC: High side (blue); Low side (red);

Sensing circuitry (yellow).

70

TABLE I RESUME OF PERFORMANCES AND FEATURES OF THE PROPOSED IC.

Parameter Value

Technology 600V HVIC technology

IC area 1.7 mm2

DC+ BUS voltage 40 ÷ 600 V

Package SO8

Opamp settable gain 10 ÷ 50

Comparator Hysteresis 50 mV

Detection threshold 250 ÷ 52 mV

Current consumption 150 µA

Temperature working range -40 ÷ 150°C

Response time 0.7 ÷ 3 µs

Figure 3.14 IC size compared to 1cent of € and 10cent of $.

It is important to note the very small IC area. An idea of the size of the final IC is given by

Fig. 3.14.

An experimental characterization of the diffused test chip was performed to confirm the

validity of the simulation reported in the previous section and to demonstrate that the

implemented transmission technique works correctly [15]. The performances and the

features of the IC are reported in Table.I.

Some attention was paid in the realization of the experimental setup. In fact, a small signal

of few hundreds of millivolt (the over-current signal Vin) has to be detected and visualized

superimposed to a DC+ value which can be as high as 600V. For this reason we decided to

refer the DC+ bus to ground (0V) while moving the ground VSS in a negative voltage range

71

(VSS= -50V has been used for the reported measurements) exploiting an insulated voltage

source. The over-current signal has been provided using a waveform generator. A gain of

10 has been set for the gain stage, providing a detecting threshold as high as 250mV.

Moreover, Table I. shows how the response time of the IC is faster than the standard

required by the used power switches. The minimum DC+ value at which the circuit works

correctly is 40V, which is the minimum start up value for the integrated power supplies.

Let us now give some details presenting some specific measurements.

Figure 3.15 Measured voltage waveform for the external key node:

Vin (200mV/div); out1 (1V/div); open drain (5V/div);

Time scale: 2µ/div.

The first measurement (see Fig. 3.15) shows the behavior of the key nodes reported in

Fig. 3.11, which are accessible from the IC pads: the input signal Vin, the output node of

the gain stage out1 and the open drain OD. As explain before, due to the measurements

setup the node value have been observed referred to DC+ bus=0V. As can be seen, using

Vin=300mV, out1 drops by about 3V (coherently with the chosen gain value) and thus the

open drain is triggered.

Vin

out1

OD

72

Figure 3.16 Response time for an input voltage close to the threshold:

Vin (100mV/div); OD (2V/div);

Time scale: 2µ/div.

Figure 3.17 Response time for an input voltage larger than the threshold:

Vin (100mV/div); OD (2V/div);

Time scale: 2µ/div.

Vin

OD

Vin

OD

73

Fig. 3.16 and Fig. 3.17, report the response time of the IC as a function of the amplitude of

the input signal Vin. In this case only Vin and the open drain OD are showed. In Fig. 3.16

it is possible to see that for an input signal Vin close to the set threshold (250mV) OD goes

high with a delay of about 2.8µs. This delay, will be also the upper limit of the response

time interval. For an input signal Vin=300mV the response time results significantly

reduced compared to the previous case (see Fig. 3.17). Therefore, the timing required by

the considered applications is largely respected.

References

[1] B. Saritha, P. A. Janakiraman, “Sinusoidal three phase current reconstruction and control using a DC-link current sensor and curve fitting observer,” in IEEE Trans. Industrial Electronics, vol. 54, pp. 2657-2664, October 2007.

[2] T. Kobayashi, H. Kubota, “Investigation of IPMSM's position estimation in low speed region

with DC link current detection,” Proc. IEEE Applied Power Electronics Conference and Expo, 2007, pp. 1411-1416.

[3] A. M. S. Mendes, A. J. Marques Cardoso, "Fault diagnosis in a rectifier-inverter system used in variable speed AC drive, by the average current Park's vector approach," in hProc. International Conference on Power Electronics and Motion Control, 2000, pp. 1-9.

[4] C. Karl, K. Kafka, "Power electronics monitoring for a controlled voltage source inverter drive with induction machines" Proc. of the IEEE Power Electronics Specialists Conference, 2000, vol. 1, pp. 213-217.

[5] M. Matsushita, H. Kameyama, Y. Ikeboh, S. Morimoto, “Sine-wave drive for PM motor controlling phase difference between voltage and current by detecting inverter bus current,” Proc. of the International Conference on Electrical Machines and Systems, 2007, pp. 740-745.

[6] C. E. Konrad, R. M. Gamber, M. Polo, “Ground fault detection and protection method for a variable speed ac electric motor,” US Patent: 5945802 - 31/August/1999.

[7] K. Lee; N. Park; K. Kim; D. Hyun, “Simple fault detection and tolerant scheme in VSI-fed switched reluctance motor,” Proc. of the IEEE Power Electronics Specialists Conference, 2006, pp. 1-6.

[8] O. Yu, N: Park, D. Hyun, “A novel fault detection scheme for voltage fed PWM inverter,” Proc. of the IEEE 32nd Annual Conference on Industrial Electronics, 2006, pp. 2654-2659.

[9] M. Grasso, S. Morini, “Start up circuit for providing a start up voltage to an application circuit”, Patent US.60600046 - 9/ AUG/ 2004.

[10] D. Giacomini, E. Bianconi, U. Fantozzi, R. S. Filini ‘High voltage level shifting IC with under-ground voltage swing withstanding capability’, Patent U.S. 6967518, 22/ Nov/ 2005.

74

[11] M. Rossberg, B. Vogler, R. Herzer, ‘600V SOI Gate Driver IC with advanced level shifter concepts for medium and high power applications’, Proc. European Conference on Power Electronics and Applications, 2007, pp. 1-8.

[12] D. R. H. Carter, R. A. McMahon, ‘Electronic level shifter for use in half-bridges operating at 13.56MHz’, Electronics Letters, vol. 31, no. 16, August 1995.

[13] M. Giandalia, M. Grasso, S. Morini, D. Respigo, S. Ruzza, “Low current continuous time transmission”, Patent pending: U.S.60978808.

[14] S. Ruzza, E. Dallago, G. Venchi, M. Giandalia, S. Morini, D. Respigo, ”An Integrated Fault Detector in High Voltage Technology for Motor Drive Applications” Proc. IEEE International Conference on Electronics, Circuits and Systems, 2008, pp. 182-185.

[15] S. Ruzza, D. Respigo, E. Dallago, M. Giandalia, S. Morini, G. Venchi, “Fast-responding over-current detector circuit in high voltage technology for motor drive applications”, to be presented at the IEEE Industrial Electronics Conference (IECON’08), November 2008, Orlando, Florida, USA.

75

4. Development of a single shunt front-end for current

sensing IC

This chapter reports the development of an electronic front-end for current sensing in

single shunt, motor drive application. The circuit is aimed to sense the current signal on

the return wire of the three phase inverter which drives the motor.

A large experimental activity has been done to understand the characteristics of current

signal which has to be detected.

An analog front-end based on a switched-capacitor architecture has also been developed

and designed together with an input filter inserted to reduce the noise which affect the

shunt signal.

All circuit details and simulation results are reported.

76

4.1 Introduction

The regulation of sinusoidal phase currents in a three-phase voltage source inverter (VSI)

is typically achieved using high-bandwidth current sensors located at the output terminals

of the three inverter phase legs, as shown in Fig. 1. According to this approach, a DC- bus

current sensor (also shown in Fig. 1) would be used only for protection purposes, if used at

all.

Figure 4.1 VSI showing both output phase current sensors and single dc-link current sensor.

Recently the interest in techniques for eliminating the current sensors at the inverter output

terminal in favour of using the single DC- bus current sensor to regulate all three phase

currents [1-9] has increased significantly. Motivations for this research efforts include cost

savings associated with reducing the number of current sensors and elimination of potential

load unbalances caused by unequal gains of the output terminal current sensors.

The first step to understand the proposed activity is to understand the relationship between

the DC- bus and the motor phases currents.

A Space Vector Modulation strategy is typically used to control the inverter in these

applications. The principle of the phase currents derivation based on the DC- bus current

measurements is resumed in Fig. 2. For each of the six active states of the inverter (v1-v6),

the DC- bus current is equal to one of the phase currents (or to its opposite), while during

the two zero states ( v0 and v7 ) the bus current is zero since all motor currents are free

wheeling. Therefore, it is possible to calculate the current in two of the motor phases in

each modulation cycle T by sampling the IDC current at certain defined instants during the

cycle.

77

Figure 2. Examples of inverter configurations during a switching period.

tTPWM

t

t

t

0

0

0

0

0

0

0

1

0

1

1

0

0

1

0

1

0

0

1

1

1

1

1

1

v0v0 v7 v7 v6 v4v6v4

T1 T2

-I3

I1

-I3I1

Figure 3. Ideal DC-bus current for a generic switching pattern.

78

For example, by sampling the IDC during T1 and T2, as shown in Fig. 3, it is possible to

obtain the estimates of I1 and –I3; I2 is finally obtained by observing that the sum of the

three currents is always zero.

Being the PWM frequencies comprised between 10 and 16 kHz, the limits for TPWM would

results to be between 100 and 62.5 us respectively. The maximum value for Vshunt depends

both on the current value (and consequently on the considered motor class) and on the

shunt ohmic value. Since the shunt is normally chosen in order to reduce the power

dissipation on it, Vshunt usually does not exceed 250mV.

However some limitations exist: one active vector must be applied for a minimum time to

ensure a reliable sampling of the IDC. A large number of parasitic currents and coupling

effects give rise to parasitic currents flowing in the DC- bus of the inverter during its

normal switching: these currents cause components of Vshunt which can be of the same

order of the one that has to be detect. Of course, they are useless for the control, heavily

degrading the accuracy of the sampled data. Furthermore, even if these currents are caused

by switching transients, in certain situation their duration can be comparable to the

duration of a particular switching state especially when it is applied for a very short

interval. In some cases the sampled data can be completely corrupted.

Different solutions have been presented in literature which involve the manipulation of the

switching patterns [10–11] so that the active states comply with the necessary minimum

time constraints for obtaining reliable DC- bus current samples. However, each of these

schemes produces undesired side effects in one or more performances, including increased

current ripple, higher switching losses, and acoustical noise on the application. These

limitations have reduced the overall desirability of the DC- bus shunt in favour of

conventional current regulator configurations using two or more phase current sensors.

Our approach is aimed to realize and implement a sensing front-end which is able to

transduce a current information as accurate as possible without modifying the PWM

timing, also for those active vectors with a duration lower than 1µs.

The proposed current sensing front-end is included into a motor control IC which is largely

digital, in order to reach a large flexibility versus the customer needs. Furthermore, the

clock generation block was implemented using an all digital phase locked loop (ADPLL)

becoming pretty digital: this solution allows to largely reduce the area consumption

compared to a classical analog PLL. However, the read-out channel remains “analog

based”. Also the internal generated voltage reference was realized with a bandgap

structure, resulting in an analog part.

79

4.2 Parasitic effects on the DC- bus current signal

A large part of the noise that usually affects the DC- bus is due to the motor and to the

switching of the various parasitic inductances and capacitances during the normal inverter

operation [12-13].

In fact, considering all the effects which become significant implementing the inverter on a

PCB, the single inverter cam be represented as in Fig. 4.4. Unfortunately, the effects due to

the parasitic elements is very difficult to be modeled and numerically evaluated: this is

because their values can change according to the PCB routing or other issues which are not

under the direct control of the designer and they can only limited but not cancelled them.

Figure 4.4 Parasitic elements on the inverter leg

On the other hand, there are other current components which cross the shunt resistor even

if they are not motor’s current; they are caused by the turn-on/off of the power switches of

the inverter and by the gate driver. These components can be quantified and their

characteristics are related both to the used gate driver and to the switches. Some of these

are reported in following.

An experimental setup was used to observe and quantify these currents in order to

understand how they can affect the ideal current signal detected on the DC- bus shunt. The

setup exploits a platform provided by IR which allows to develop a customize control for

asynchronous and brushless motors.

The platform basically includes a microcontroller, a rectifier circuit to provide the inverter

supply and an integrated module (IRAM [14]) containing the three-phase inverter, a driver

and a shunt on the DC- bus of the inverter. Being an integrated module, it wasn’t possible

80

to get the required information directly from the driver due to the fact that most of the

connections were not available externally: for example, the use of a current probe to

measure the IDC was not possible because only the shunt terminals were available off chip.

For this reason, a first approach for the detection of the IDC current was the use of an

external shunt, equal to the one inside the module, with a piece of wire in series which

could accommodate the current probe. Unfortunately this approach lead to problem on the

electrical drive which was fooled by the inductive voltages contributed by the external

wiring of the shunt, detecting them as a faulty over-current condition. After having tried

some alternative approaches the use of two separate boards was adopted: in this way, the

first board was used simply to rectify the AC line current providing the ground wire an the

DC+ bus for the inverter, while the IRAM module of the second board was used to feed a

motor. Now the current probe can be used on the DC- wire which connects the boards (see

Fig. 4.5a and Fig. 4.5b).

(a)

(b)

Fig.4.5 Implemented setup.

81

Figure 4.6 DC- bus current:

ch1) Lin1 (2V/div); ch2) IDC (500mA/div);

ch3) Lin2 (2V/div); ch4) Lin3 (2V/div); Time scale:200us.

The detected IDC current is reported in Fig. 4.6. As it can be seen it has the characteristics

seen in the previous paragraph but with a large noise over imposed to the current values

that has to be detected. Some of the source of this noise and parasitic component are

reported in the following.

• Low side turn-on

The first current we consider is the one due to the turn-on of the low side IGBT in a

inverter leg.

As it can be seen in Fig. 4.7, to turn-on the low side switch, Lin goes low; after a delay of

400ns (which is the turn-on time of the gate driver) the Lout of the driver goes high turning

on the IGBT1. As shown, the current used to charge the IGBT gate is directly supplied by

Vcc, giving raise to a current path (reported in gray) which crosses the shunt. The

amplitude and the duration of this phenomena have been measured using a current probe

on Vcc and are reporter in Fig. 4.8.

82

Figure 4.7 Current path during the low side turn-on.

Figure 4.8 Current due to low side turn on:

ch1) current (50mA/div);ch3) Hin (2V/div); ch4) Lin (2V/div); Time scale:200us.

83

• Bootstrap capacitor recharge

Another current which can affect our measurement is the one during the bootstrap

capacitor recharge.

The bootstrap capacitor is usually recharged by Vcc when the Vs is low (IGBT1=ON or

phase current crossing D1).

Figure 4.9 Current path due to the bootstrap capacitor recharge.

Figure 4.10 Current due bootstrap recharge:

ch1) current (50mA/div); ch3) Lin (2V/div); ch4) Hin (2V/div); Time scale:200us.

84

Also in this case the recharging current gives raise to a current path which crosses the

shunt on the DC- bus (see Fig. 4.9). The characteristics of this current have been observed

experimentally and are reported in Fig. 4.10.

While their duration is a few hundreds of nanoseconds, this currents become significant in

some particular conditions: for example, when a low torque is applied to the motor the

phase currents is very small and therefore comparable to the showed ones. It means that

during the first part of the Ti a wrong current value can be detected, drastically reducing

the time window where the real signal can be detected.

Different other currents, which have not been reported here for convenience, can affect the

DC- current measurement. These currents are due to the high side switch turn on, or to

diode recovery, or to the level shifter circuit inside the gate driver.

In order to evaluate the front-end performances directly in the Spectre® environment, a

simulation framework has been developed using only ideal components, implementing an

inverter, a driver and a motor. In this way a signal as similar as possible to the real one can

be obtained directly by the simulator, setting the value of the parasitic elements and the

inverter switching characteristics. Two figures are reported (Fig. 4.11 and 4.12) to show

the generated signal: the first one shows the current signal detectable on a PWM period,

while the second one highlights the ripple superimposed to the ideal waveform. This

undesired behaviors really reduces the “clean window” where the data can be detected

without problem (125ns) with respect to the duration of Ti (600ns).

Figure 4.11 Vshunt generated by the implemented framework.

85

Figure 4.12 Ringing on the generated Vshunt waveform due to parasitics.

4.3 Existing front-end prototype

The implemented front-end circuit has been developed in TSMC 0.18µm RF technology.

The choice of a switched capacitors architecture is due to different considerations on both

the characteristics of the signal that has to be detected and on the limitations of a first

prototype of front-end (reported in Fig. 4.13) which worked in continuous-time mode.

Figure 4.13 First prototype of single shunt front-end.

Ti=600ns

125ns

86

Unfortunately, in this scheme a large bandwidth is required for the opamp (OPA) to be

able to follow the current signal previous showed, while the need of an external resistor

network to set the gain contrast the previous requirement, creating an in-bandwidth pole

which largely limits the response time of the system.

On the other hand, the use of a fully integrated discrete-time solution would allow to

sample the signal before to amplify it, drastically reducing the bandwidth requirement.

Different solutions have been evaluated in order to obtain the desired results, trying to

avoid the problems which usually affect SC circuits (e.g. stray capacitance).

4.4 Implemented front-end circuit

The proposed circuit solution allows to sample the input signal and shift it directly on the

common mode of the fully differential opamp on a first phase (Ø1). Thus, the signal is

amplified and the gain factor can be changed directly by the DSP on the second phase (Ø2):

in this way, it is possible to exploit the output dynamic of the opamp for all input values

and both resolution and complexity of the analog to digital converter can be reduced. The

complete front-end circuit is reported in Fig. 4.14.

Figure 4.14 Proposed front-end circuit.

87

As it can be seen, one of the sampling network is directly connected to ground while the

second one will get Vshunt. The disadvantage of this structure would be the loss of the half

part of the opamp output dynamic. However a possible workaround to this behavior is to

implement a variable gain for the opamp and it will be explained in the following. The

sampling of the input signal happens in Ø1 while the amplification happens in Ø2.

As far as the sampling phase is concerned, only the network part that gets the signal is

highlighted. An offset voltage on the input pair of the opamp is also considered. As it can

be seen in Fig. 4.15, a plate of C1 is connected to Vshunt while the second one is connected

to the opamp input which is in buffer configuration. At the same time C2 is charged at

Voffset in order to compensate the offset in next phase. Once the input data has been

stored on C1 and the offset has bee charged on C2, in the next phase the data is transferred

on C2 which is connected to Vout, as shown in Fig. 4.15. Thus, transferring the charge

from C1 to C2, the offset is cancelled and the opamp unbalances its output terminals by a

quantity equal to Vshunt/2. In order to avoid the loss of half output dynamic, the

possibility to change the gain was introduced as reported in Fig. 4.16.

The gain selector block was implemented using as C2 three capacitors and combining them

in parallel through switches to obtain the desired gain value. These capacitors are a fraction

of the one acting as C1. The switches are selected by the DSP using two bit (b0 and b1):

since the DSP evaluates the motor current at each PWM cycle, it can set the gain value for

the expected one in order to exploit the opamp’s output dynamic at its best.

Indicating as C the capacitor resulting by the gain selector block the possible gain value are

reported in Tab.I.

Vcom

Vcom

C1

C1 C2

C2Vin

Vout+

Vout-

+

+

+

+

Vcom+Voffs

et

+ Voffset -

Figure 4.14 Phase Ø1 – Signal sampling and shifting.

88

Figure 4.15 Phase Ø2 – Signal amplification and offset compensation.

Figure 4.16 Gain selector block

Tab.I

b0 b0 C/CX Gain 0 0 8 4 0 1 X X 1 0 4 2 1 1 2 1

89

4.5 Input filter for the implemented front-end

Since the signal Vshunt is largely noisy, it’s very important to implement an effective input

filter which is able to eliminate or heavily reduce the effects of the noise on the sampled

data.

Solution a) RC filter which variable time constant.

The first idea for an input filter is based on a simple low pass filter whose resistive part can

be selected among a discrete number of steps at each data sample (see Fig. 4.17a). This is

fundamental in order to adapt the filter time constant to the settling time of the signal,

obtaining a effective reduction of the ringing component.

C1

Logic

ø1

ø2

Opamp

input

Vin

(a)

(b) (c) (d)

Figure 4.17 (a) Low pass filter with selectable RC; b) c) d) Example of filter time response vs. RC.

The case in Fig. 4.17b reports an example of a short active vector, where a low resistance

value has to be selected for the filter, in order to allow it to follow the signal reducing the

90

ringing. In Fig. 4.17d, the time are relaxed and a large resistive value can be selected to

obtaining an effective filtering. This technique is based on the knowledge of the active

vectors duration (Ti) from the DSP: in this way it would be able to select R as a function

of Ti.

A possible variation to the filter structure of Fig. 4.17 is reported in Fig. 4.18. It represents

a way to improve the filter characteristics during the first part of the active vector. In fact a

“pre-charge phase” was included to increase the response time of the filter: during the first

part of Ti the capacitor is directly connected to Vin: this allows the voltage value on it to

raise faster than for the first filter, rapidly getting a value near to the expected one. After a

time (indicated as “delay” in Fig. 4.18) a resistor is inserted to filter the remaining ringing.

This allows to improve the response time of the filter for reduced value of Ti.

Figure 4.18 low pass filter with pre-charge function.

Solution b) F.I.R.-like input filter.

The second solution of input filter that has been evaluated is based on a F.I.R.-like

topology; its basic scheme is reported in Fig. 4.19. It realizes a discrete-time sampling of

the input signal, getting different samples whose distance in the time domain can be

indicated as D and can be implemented by the delay of an inverter chain.

The samples are stored one for each capacitor and in the end the capacitors are put in

parallel, obtaining a weighted sum of the stored samples. Being a discrete-time sampling

method, a resistor in series with the capacitors has to be used as anti-aliasing filter.

The number of samples has to be chosen as a trade-off between the data accuracy and the

time needed to get all the samples. A good approach would consists in the possibility to

91

make the value of D variable, allowing to change the number of samples as a function of

the duration Ti of the active vector.

C1 Ci CnCn-1

Vin

Opamp

input

ø1

ø2D t

Figure 4.19. Scheme of the FIR-like input filter

It is important to note that the complexity of such a filter is significantly higher with

respect to the RC one: the time required to optimize its performances in simulation are

longer, due to both the number of parameters of the structure and the large spread of the

input signals characteristics depending on the considered application. The choice of the

number of capacitors that has to be used and the sampling timing depends not only on the

active vector duration (Ti), but it is largely related to the noise frequencies which

characterize the data and are typically due to the parasitics on the application board. As

discussed, these components are not under the designer’s control, making this choice an

issue.

On the other hand, the R value for the RC filter is simply linked to the active vector

duration (Ti) only: for this reason, if the RC solution provided an effective noise reduction

it would be largely preferred to the F.I.R.-like solution.

4.6 Design of the fully differential operational amplifier

In order to best satisfy the requirements of the considered front-end circuit, the

performances required for the Opamp are:

• Gain > 80dB.

• Bandwidth >50MHz

92

No specification is given for the input offset because of the compensation technique that is

directly implemented by the external gain network.

The structure that was considered is based on a two stage topology where the first stage

would provide the desired gain, while the second one would be added to improve the

output dynamic (see Fig. 4.20).

As far as the first stage is concerned, the chosen structure is a folded cascode topology. It

is a single stage structure where the frequency of the dominant pole is given by

0

1RCL

D =ω (1)

Consequently, the frequency for the unit gain is:

L

mDt C

gA 1=⋅= ωω (2)

The circuit also contains two other poles at higher frequency. The main characteristics of

the folded-cascode structure are the possibility to provide an high gain, a large dynamic for

the input common mode while it provides a limited the output dynamic for the output node

as reported in eq. 3.

( )3361 ODMCODMODMCODMDC VVVVV +++− (3)

As mentioned before, by inserting a second gain stage based on a common-source

topology, the output dynamic will be increased, resulting:

( )1921 ODMODMDC VVV +− (4)

Moreover, two High Compliance mirror structure have been used to provide the bias

voltage required by the folded cascode. This structure allows to improve the output

dynamic of the cascode of about a threshold voltage with respect to the Vdd and the

ground voltage.

93

Figure 4.20 Fully differential Opamp.

94

The common feedback block has not been included in Fig. 4.20 for convenience. However

it represents a fundamental part for the correct operation of a fully differential structure

which require a way to set the output common-mode at a fixed voltage. This goal is

normally obtained exploiting a feedback loop which acts on a given node of the opamp in

order to maintain the desired common-mode. Different circuits can be exploited to

implement the common-mode feedback. The considered one is a continuous-time solution,

whose scheme is reported in Fig. 4.21.

Figure 4.21 Common-mode feedback circuit.

The scheme is based on two differential pairs (Mf2-Mf3 and Mf4-Mf5) which modify the

current in Mf1 depending on the changing of the common-mode output voltage. Consider a

raise on the common mode voltage in order to understand how the circuit works (see

Fig. 4.22). As it can be seen, the circuit rejects the differential change on Vout+ and Vout-

nodes, because of

( ) 02

=∆−∆⋅= mgIδ (5)

where:

δI → current variation on Mf1

gm → gain Mf2 = Mf3 = Mf4 = Mf5

∆ → voltage variation on Vout+ and Vout-

It is very important to keep the input differential pairs working in the linear region.

95

Figure 4.22 Signals for a raise of common mode value.

phase (deg)

gain (dB)

Figure 4.23 Gain and bandwidth of the designed Opamp.

Simulations demonstrate that the gain and bandwidth requirements are achieved, as it is

shown in Fig. 4.23.

96

4.7 Simulations on the complete front-end circuit

For the evaluation of the front-end, simulations considering a real input signal have been

performed, in order to test the circuit in a conditions as near as possible to the real one.

Two data are measured during two intervals of a PWM period (dataA and dataB in

Fig. 4.24): in the considered windows a only the current of phase2 crosses the shunt.

Therefore the average value of these data can be directly compared to the drop provided by

the considered phase current on a shunt equal to the one on the DC- bus.

Figure 4.24 Sampling considered to test the front-end.

In the following, figures which show the phase current and the shunt signal for dataA and

dataB are reported, together with the windows that were considered to acquire these values

(indicated as Wi and highlighted in green).

As far as the shunt signal is concerned, Fig. 4.24 and Fig. 4.25 reports the value of the

considered data. During W1, the value of dataA detected directly on the phase is 70.1mV

while the DC- shunt provides 70.12mV (see Fig. 4.24). During W2, the value of dataB

detected directly on the phase varies between 70.51mV and 71.27mV, while the DC- shunt

provides 70.95mV.

97

Figure 4.25 a) Phase currents value during W1; b) shunt signal on W1.

98

Figure 4.26 a) Phase currents value during W2; b) shunt signal on W2.

At first the variable RC network was used as input filter. Considering a PWM period, the

windows used for sampling the data (W1 and W2) can have a different duration in time.

Thus is because two different RC’s values have been used. The provided resistor network

allows to choose a resistance value up to few tens of kohm. In particular, for W1 a

resistance value of R=15 kΩ was chosen, while for W2 R=5kΩ was chosen. The value of

C1 was 800pF obtained using MIM capacitor.

99

(a)

(b)

Figure 4.27 Opamp output. a) Vout for sampleA; b) Vout for sampleB.

100

Tab. I

Vshunt [mV] Vphase2 [mV] Vout single ended [mV] | Errorr| [%]

SampleA 70.12 70.1 69.89 0.3

SampleB 70.51 ÷ 71.37 70.95 71 0.07

The single ended signals obtained as output are 69.89mV and 71mV respectively.

A comparison between this values and the ones observed directly on the shunt resistor

available on the DC- bus and on the motor phases is reported in Tab. I. As it can be seen

the error remains always lower than 1% providing a very good accuracy for the front-end.

The same samples were also used do a preliminary evaluation of the front-end including

the F.I.R.-like input filter instead of the RC one.

Twenty capacitors were used whose value was 40fF, in order to provide 800fF when they

have been put in parallel, while the delay D was set to 1ns, providing a total sampling

windows of 20ns as for the previous simulation. The performances of this solution are

reported in Tab. II.

Tab. II

Vshunt [mV] Vfase2 [mV] V single_ended [mV] | Error| [%]

data 70.12 70.1 69.19 1.3

dataB 70.51 ÷ 71.37 70.95 70.2 1.06

As it can be seen in this case the values provide by the front-end include an error which is

a bit larger than for the RC filter but, in any case, acceptable. It is important to note that the

evaluation of the performance for the F.I.R.-like doesn’t include any optimization.

However this performance, together with the higher area consumption required for the

F.I.R.-like filter, lead us to choose the RC filter for the new test chip of the front-end.

References

[1] H T. C. Green and B. W. Williams, “Derivation of motor line-current waveforms from the dc-link current of an inverter,” Proc. Inst. Electr. Eng. B—Elect. Power Appl., vol. 136, no. 4, pp. 196–204, Jul. 1989.

[2] J. F. Moynihan, R. C. Kavanagh, M. G. Egan, and J. M. D. Murphy, “Indirect phase current detection for field oriented control of a permanent magnet synchronous motor drive,” in Proc. 4th EPE, Firenze, Italy, Sep. 3–6, 1991, pp. 641–646.

101

[3] F. Blaabjerg and J. K. Pedersen, “An ideal PWM-VSI inverter using only one current sensor in the dc-link,” in Proc. 5th Int. Conf. PEVD, London, U.K., Oct. 26–28, 1994, pp. 458–464.

[1] H. Kim, T. M. Jahns, “Phase current reconstruction for AC motor drives using a DC link single current sensor and measurement voltage vectors”, IEEE Trans. Power Electronics, vol. 21, no. 5, pp. 1413-1419, September 2006.

[5] H. Kim, T. M. Jahns, “Current control for AC motor drives using a single DC-link current sensor and measurement voltage vectors,” IEEE Trans. Ind. Applications, vol. 42, pp. 1539-1547, November/December 2006.

[6] B. Saritha, P. A. Janakiraman, “Sinusoidal three-phase current reconstruction and control using a DC-link current sensor and curve-fitting observer,” IEEE Trans. Industrial Electronics, vol. 54, pp. 2657-2664, October 2007.

[7] W.-C. Lee, D.-S. Hyun, and T.-K. Lee, “Novel control method for threephase PWM rectifiers using a single current sensor,” IEEE Trans. Power Electron., vol. 15, no. 5, pp. 861–870, Sep. 2000.

[8] M. Riese, “Phase current reconstruction of a three-phase voltage source inverter fed drive using a sensor in the dc-link,” in Proc. Power Conversion and Intelligent Motion Conf. (PCIM), Nuremberg, Germany, 1996, pp. 95–101.

[9] F. Blaabjerg, J. K. Pedersen, U. Jaeger, and P. Thoegersen, “Single current sensor technique in the dc-link of three-phase PWM-VS inverters: A review and a novel solution,” IEEE Trans. Ind. Appl., vol. 33, no. 5, pp. 1241–1253, Sep.–Oct. 1997.

[10] S. N. Vukosavic and A. M. Stankovic, “Sensorless induction motor drive with a single dc-link current sensor and instantaneous active and reactive power feedback,” IEEE Trans. Ind. Electron., vol. 48, no. 1, pp. 195–204, Feb. 2001.

[11] C. Zhang and F. Lin, “A single current sensor control technique for induction motors,” in Proc. Int. Conf. Power Sys. Technol., 2002, vol. 4, pp. 2290–2293.

[12] E. Persson “Transient effects in application of PWM inverters to induction motors,” IEEE Trans. Ind. Appl., Sept/Oct 1992, pp. 1095-1101.

[13] B. Zhou, W.H. Lau and H. Chung, “A theoretical solution for PWM with non-ideal transient response,” in Proc. IEEE Int. Symposium on Circuits and Systems 2005, pp. 2469-2472.

102

5. Integrated current amplifier with track and hold

function for low side current sensing in three-phase

inverter

This chapter presents an integrated current amplifier for current measurements in the low

side of IGBTs or MOSFETs based three-phase inverters.

This solution of current sensing is widely used to get the current feedback in consumer and

industrial application even if it is expensive with respect to a single shunt solution. The

most common implementation of this sensing approach is the use of an external

large-bandwidth opamp which works in continuous-time mode and provides the data to the

analog to digital converter inside the microcontroller.

This chapter presents an alternative approach, integrating the current amplifier inside a

half-bridge Gate-driver. Various aspects have been taken into account to implement this

solution because of the performances of the opamp that can be obtained in the used

technology compared to a discrete opamp. All considerations are reported together with

the circuit solution and measurements on a test chip.

103

5.1 Introduction

A current measurement method widely used in consumer and appliance applications is

sensing the low side of the three inverter legs. This solution can be implemented using

either a low side switch with a Kelvin terminal dedicated to current measurement or a

shunt resistor in series with the emitter/source terminal of the IGBT/MOSFET switch [1].

Figure 5.1 Three-phase voltage-source PWM inverter with the integrated pilot current sensors in

the three low-side switches.

As far as the former approach is concerned (Fig. 5.1), different works [2-4] have been

reported in literature achieving a closed-loop current regulation for the “brushless dc”

permanent-magnet (PM) machines with trapezoidal (stepped) current excitation. It is

important to note that the Kelvin terminal allows to detect the current only if it crosses the

power switch loosing the information when it crosses the diode [5]. Since in trapezoidal

excitation only two of the three motor phases carry current at any given instant of time (the

third phase current is zero), the measurement of only one phase current is sufficient and

allows to implement an effective current regulator.

On the other hand, current reconstruction problems appear when a sinusoidal excitation is

used instead of the trapezoidal one since all of the phases carry a current at the same time.

Considering the condition with one of the phase current negative and the other two positive

(according with the versus in Fig. 5.1) only the negative one crosses the low side power

switch when it is “on” while the others crosses the diode. This means that no current

reconstruction is possible in this case.

104

For this reason, in most applications, the use of a shunt resistor becomes an effective

solution. In fact, it can transduce the low-side current during all the phase current period.

The ideal shunt signal is reported if Fig. 5.2a. Also in this case the amplitude of the shunt

signal can be up to 250mV while the pulses duration is directly related to the PWM timing.

In this case, with respect to the single shunt application considered in the previous chapter,

the minimum duration for the active vector is not a problem form the microcontroller point

of view: in fact, consider Fig. 5.2b using three shunt resistors (one on each low side), the

current signal can be reconstructed using a single sampling during the PWM period. It

usually happens when all the low side are on (active vector 000). Therefore, also if one of

the low side remained “on” for a limited time (few hundred of microseconds) the other two

shunts could be easily detected and the current reconstruction could be performed.

Vs

D1

D2

LS_shunt

(a)

Vs1

Vs2

Vs3

(b)

Figure 5.2 a) Current waveform available on the low side shunt.

b) Active vector 000 when currents are sampled.

105

It is important to note that the use of three shunts on the low sides allows to obtain

performances which are in line with the ones obtained using three shunts on the motor

phase. Moreover, the data sampling circuits can be referred to ground without the need of a

large common mode rejection as in the phase current sensing.

Due to the use of three shunt resistors, this approach is more expensive than the single

shunt solution, but the control performances are significantly higher.

5.2 Evaluation of the current sensing architecture

Many industrial and consumer applications exploiting this current sensing method use a

discrete Opamp in non-inverting configuration to amplify the shunt voltage signal. A

typical configuration for this system is reported in Fig. 5.3.

An Opamp with high bandwidth and slew rate performances has to be used, in order to be

able to amplify Vin with a continuous-time approach. In fact, the shunt signal can present

pulses of large amplitude and short duration: the opamp output need to moves between

zero and the pulse amplitude for all its working time. Being the shunt signal bipolar while

the analog to digital converter of the microcontroller is unipolar, a voltage shift of the input

signal is normally implemented. The most common solution is to shift the signal to half the

supply voltage of the microcontroller (3.3V in the case of Fig. 5.3)

Figure 5.3 Sensing block using discrete components.

As it can be seen, the use of a large capacitor on the Opamp output, to provide a signal as

stable as possible on the ADC input and not to connect the ADC input sample and hold

106

directly to the opamp output. Unfortunately, this capacitance value, together with the

resistor, give rise to a time constant which largely affects the Opamp output making it very

slow. This could be a real problem when the Vin has a large amplitude and its duration is

very low, because the out node could not set before the pulse’s end. Therefore, this large

capacitor, contrasts the large bandwidth requirements of the opamp

With the considered 15V CMOS devices available in the technology used for the driver,

the bandwidth ad slew rate performances of a discrete standard Opamp are not available.

Thus, a way to workaround these limitations has to be find: in fact, the advantage of the

Opamp integration together with the Gate-driver becomes interesting only if the quality of

the data sample remains competitive with the discrete solution. The adopted solution is

reported in next paragraph.

5.3 Proposed sensing solution

In order to reduce the performances needed by the current amplifier, a discrete-time current

sensing method was adopted. A track and hold (T&H) stage was inserted between the

shunt and the CA+ pin of the IC and the positive input terminal of the amplifier of the

opamp, as shown in Fig. 5.4: this approach allows to track the shunt voltage Vin when the

current crosses it, while this voltage is hold when the shunt’s current droop to zero.

Figure 5.4 Gate-Driver with integrated current amplifier.

107

This solution offers two basic advantages compared with the continuous-time solution:

• The data is sampled without any amplification before the hold phase, and the signal

on the capacitor can set with the RC provided by T&H stage by itself,

independently from the settling time of the current amplifier. Moreover, the output

filter can be reduced.

• Being the current data hold when the low side current goes to zero, the amplifier

slew-rate performances are relaxed. Moreover, the step between two consecutive

data result reduced with respect of the continuous time solution where the amplifier

output always moves from zero to the amplified value.

The waveform on the out pin would be the one reported in Fig. 5.5.

Figure 5.5 Current amplifier output node (out).

Figure 5.6 Track and hold block.

108

The track and hold was implemented with a MOS switch and a capacitor. The switch

design is fundamental in order to limit as much as possible the charge injection when the

switch turns off: this injection could largely affect the value of the sampled data. Being the

Vin that has to be sampled lower than 1V while the supply is Vcc=15V, a simple n channel

MOS based switch was adopted (see Fig. 5.6): two shorted n-channel dummies were added

to the switch and two resistor were also included to provide resistance equalization to both

the input and output nodes of the switch: in this way, the charge injection would split in

equal parts reducing its effect on the stored data. A quite large capacitor value (4.6pF) was

also chosen in order to further reduce the injection effect.

The opamp is supplied exploiting the Vcc=15V which feeds the low side pocket of the

Gate-driver. A p channel input pair is used, being the input voltage to be detected up to 1V

as mentioned before. Since a T&H function has been adopted, the opamp needs to set its

output value (out) quite fast: in fact, there are some working conditions where two

consecutive current pulses can happen very near one to the other and it is fundamental not

to miss them. Thus, a good slew-rate performance is needed and great attention has to be

paid both in the choice of the differential pair current and the sizing of the Miller capacitor

since they are responsible for slew-rate of the opamp. Moreover, as seen in Fig. 5.3, a large

RC filter is required on the CAO node to reduce the effect of the switch charge injection on

the stored data.: therefore, some attention has to be paid in choosing the output stage of the

opamp. Due to the gain requirement, a two stages topology is needed. Furthermore, a low

impedance output stage is needed, in order to drive the resistive load. If a basic class A

output stage was used an asymmetrical rise/fall time of the output node would happen.

Therefore the solution reported in Fig. 5.7 was adopted.

Since no offset compensation was considered, great attention was paid also in the sizing of

the input pair and its active load. The expected input offset considering the technology

parameters would be 1.72mV, which is lower then the desired 3mV. However, the offset of

the current amplifier and the one provided by the charge injection of the switch during its

turn-off will be compensated by the microcontroller before start the system, performing a

sample with zero current on the LS_shunt.

109

Figure 5.7 Schematic of the current amplifier.

5.4 Timing of the track and hold block

The timing of the T&H block is fundamental, both to acquire a data as free as possible

form undesired components and to avoid the return of the amplifier output to zero moving

from one sample to the next one.

To understand how the tracking instant is selected let’s consider the possible working

conditions of the inverter leg (see Fig.5.8).

As far as the phase current flows from the inverter to the motor, consider the case in

Fig. 5.8a: at the beginning, HO is high while LO is low and current Iphase is provided by

the IGBT1, keeping Vs at the DC+ value. When HO goes low turning off IGBT1, after a

small interval current Iphase closes on D2, and Vs goes to zero. Thus, the track phase can

start, also if LO is low. In this way also the dead time (DT) is exploited. The track phase

ends when LO goes back to the low state: in fact, if the going high of Vs was used to stop

this phase a wrong current could be read, due either to the turning-off current of IGBT2 or

the reverse recovery current of D2.

The case with current Iphase which flows from the motor to the inverter is reported in

Fig.5.8b. Considering the same switching sequence seen for the previous case: here, even

if IGBT1 is on, the current flows in D1 keeping Vs at the DC+ value. Voltage of the Vs

110

node goes to the ground only after the going high of LO and the IGBT2 turns-on. It means

that in this case the dead time can’t be exploited for the tracking of the input data. The end

of the tracking phase and the start of the hold one will happen when the LO goes down to

turn-off the IGBT2 as in the previous case.

Figure 5.8a Track and hold timing with the phase current flowing to the motor.

Figure 5.8 Track and hold timing with the phase current flowing from the motor.

111

5.5 Evaluation of the current amplifier prototype

A preliminary evaluation of the proposed circuit was carried out with a simple board,

providing a sinusoidal waveform as input signal, and driving the track and hold using an

external clock.

The frequency of the input waveform was set lower then 100Hz which is a normal

frequency range of the sinusoidal current on the motor phase. In particular, for the

measurements reported in Fig. 5.10a and 5.10b a sinusoidal signal with f=70Hz and

VPP=400mV was used; two clock signal were also tested at fCK1=1kHz.

(a)

(b)

Figure 5.10 Amplifier out waveform and zoom detail with CK1=1kHz.

CK1

CA+

out

CK1

CA+

out

112

A gain of 2 was set in order to compare VCA+ and VCAO directly on the oscilloscope’s

window. As can be seen during the track phase VCAO perfectly tracks the VCA+, while it

keep the tracked value during the hold phase. The same consideration can be done

observing the measurements of Fig. 5.11a and 5.11b where a clock CK2=12kHz was used

(this is the typical PWM frequency used to switch the inverter leg).

(a)

(b)

Figure 11 Amplifier output waveform and zoom detail with CK1=1kHz

CK2

CA+

out

CK2 CA+

CAO

113

An evaluation of the charge injection observing the CAO node was done, setting gain=4.3

for the opamp. A different, fixed input signals was set and the output node was observed

coupling it in AC mode in order to remove the DC value due to the opamp gain. As it can

be seen in Fig. 12, the VCAO presents a voltage step whose amplitude is about 4mV after

each switch turn-off: since a gain=4.3 was set, it means that the injection on the capacitor

of the track and hold stage provides an offset lower than 1mV. This value, remains quite

constant changing both the input signal value and the temperature in the range

(-20÷130 °C).

Figure 12. Effect of the switch injection observed on VCAO.

Finally an evaluation of the amplifier slew-rate was done, using it in buffer configuration

and proving 2V input step an input signal: both positive and negative slew-rate values of

8V/µs were observed.

References

[1] S. Chakrabarti, T. M. Jahns, and R. D. Lorenz, “A current current control technique for induction machines drives using integrated pilot current sensors in the low-side switches,” IEEE Trans. Power Electronics, vol. 22, no. 1, pp. 272–281, Jan. 2007.

[2] T. M. Jahns and E. J. Wildi, “Integrated current sensor configurations for ac motor drives,” U.S. Patent 4 777 579, Oct. 11, 1988.

CK1

CAO

114

[3] T. M. Jahns, R. C. Becerra, and M. Ehsani, “Integrated current regulation for a brushless ECM drive,” IEEE Trans. Power Electronics, vol. 6, no. 1, pp. 118–126, Jan. 1991.

[4] S. R. MacMinn, W. J. Rzesos, P. M. Szczesny, and T. M. Jahns, “Application of sensor integration techniques to switched reluctance motor drives,” IEEE Trans. Industrial. Applications, vol. 28, no. 6, pp. 1339–1344, Nov./Dec. 1992.

[5] S. Chakrabarti, T. M. Jahns, and R. D. Lorenz, “A current reconstruction algorithm for three-phase inverters using integrated current sensor as low side switches,” in Proc. IEEE Ind. Appl. Soc. Annu. Meeting, Salt Lake City, UT, Oct. 2003, pp. 925–932.

115

Conclusions

This work focused on the development of mixed-signal integrated circuits for motor drive

applications; in particular, current sensing for modern electrical drive used in motion

control for both consumer applications (e.g. air conditioning or washing machines) or

industrial applications (e.g. servodrive systems) was considered.

The purpose of the current transduction for these systems is twofold: on one hand the

current data from the motor is the feedback variable used for closing the control loop in

motion control; on the other the detection of the fault conditions which can damage the

electrical drive is usually performed observing over-currents in various point of the

three-phase inverter.

A study of the current signals in a electrical drive and of their representation when

transduced by means of a shunt resistor was performed. The current signals were first

measured in an experimental setup; after that, a Spectre® framework was developed which

allowed to test the various current sensing front-end solutions against realistic signals.

As a first step, the sensing of a shunt resistor directly placed on the motor phase was

considered. The attention was focused on the realization and implementation of a floating

power supply in junction isolated high voltage technology which allowed the use of

advanced CMOS technology inside the floating part of a current sensing IC. In particular,

the circuit is aimed at supplying the signal processing circuits diffused inside the same

floating pocket where the power supply resides. This pocket is biased by the supply output

with a voltage lower than the bootstrap capacitor voltage. Different prototype have been

diffused demonstrating the feasibility of the idea and allowing to continue the development

of a new sensing front-end in the considered IC, and generally the use of large digital

circuitry in the floating part of an high voltage IC.

Another current sensing method which was considered exploits a single shunt resistor

placed on the return wire of the inverter. This approach requires the development of a

dedicated front-end for suitably amplifying and filtering the shunt signal which is

perturbed by stray currents and voltage ringing due to parasitics. A switched capacitor

amplifier was implemented in order to both improve the performances and to reduce the

bandwidth problem shown by a continuous-time solution previously presented. In this way,

the accuracy of the feedback data provided to the control loop could be improved. Two

116

solutions of input filter were considered and tested. The proposed sensing solution would

allow to improve the performances of the control loop, and reduce the acoustical noise

provided by the inverter when the PWM patterns are distorted in order to help the current

transduction.

In a second phase the study of an high voltage IC for faults detection was carried out, first

analyzing the various types of short circuits which can affect the electrical drive and then

developing a prototype. This circuit detects the fault conditions sensing a shunt resistor on

the DC+ bus of the inverter and communicates this condition either to a microcontroller or

a Gate-driver using an open drain output pin. The proposed IC exploits an innovative level

shifting technique to transmit a data over the two sides of the IC which are referred to

different voltage nodes with no additional power consumption with respect to the bias.

Two prototypes have been diffused and characterized showing the effectiveness of the

proposed solution.

Finally, an integrated front-end aimed at sensing a shunt on the low side of the inverter leg

was developed. The proposed solution is an alternative to classical approaches which

exploit discrete components and devices, being integrated in a half-bridge Gate-driver. The

circuit uses a current amplifier, whose gain can be set by the designer. A track and hold

stage was included before the amplifier allowing to reduce both bandwidth and slew-rate

requirements which are critical parameters due to the adopted technology. Two test chip

have been successfully characterized.