design and implementation of a digital image processor for ... · enhancement techniques using...

Design and Implementation of a Digital Image Processor for Image

Enhancement Techniques using Verilog Hardware Description Language

DhirajR. Gawhane, Karri Babu Ravi Teja, AbhilashS. Warrier, AkshayS. Belvadi Visvesvaraya National Institute of Technology, Nagpur, India – 440010

[email protected], [email protected], [email protected], [email protected]

Abstract

The design and implementation of a processor, to

perform basic point operations on an image using

Verilog Hardware Description Language (HDL) has

been investigated. Performing signal processing

operations using HDL have an advantage of

immediate hardware VLSI implementation as against

classical simulation methods. To achieve higher

performance, especially, high speed and efficient

hardware utilization, we suggest a suitable processor

architecture imbibing the concept of pipelining, for

signal processing, along with its implementation and

results. The processor achieves image enhancement

in spatial domain through point processing

operations like: contrast manipulation, brightness manipulation, inversion and threshold operations.

Index Terms - Digital Image Processing, FPGA,

Verilog, Image Enhancement, Point Operations

1. Introduction

he use of HDLs provides designers with the

flexibility of simulating and evaluating the

digital circuit performance with timing

considerations. This flexibility can be extended into

the field of digital signal processing. However, HDLs

provide the main advantage of immediate FPGA

based hardware implementation.

Since, HDLs enable description of circuits

precisely; it provides an opportunity for the designers

to optimize speed of operation from the available

timing information. The only challenge lies in the

mapping of an algorithm into HDL due to its non-

programming background. The only disadvantage of

hardware simulators is that it does not support any

format other than binary. So, all the input output data

files arerequired to be in binary format for HDL

implementation [8].

Digital image processing is widely used in

multimedia services, arts, medicine, space

exploration, surveillance, authentication, automated

industry inspection and many more areas [7].

Use of ASICs or FPGAs for hardware

implementation of signal processing units provides

higher efficiency as compared to its software implementation [1].

An image processor normally comprises of

memory banks, processing unit and a control unit.

For efficient implementation and speed optimization

of any processor architecture, parallelization of

operations is essential. Image processors facilitate the

use of on-chip memory module to achieve

parallelization [2].

2. Image Enhancement Techniques

Image enhancement aims at improving the

interpretability or perception of information in image

for human viewers, or providing „better‟ input for

other automated image processing techniques[3][7].

Image enhancement techniques can be classified into

two categories: spatial domain techniques and

frequency domain techniques. The spatial domain

technique refers to enhancement of image based on

operations performed directly on the pixels of the

image. Frequency domain techniques achieves

enhancement through the use of mathematical

transforms such as Fourier transforms [7].

Image processing operations in spatial domain involves the adjustment of brightness, contrast or

colour of an image. Manipulation of these attributes

results into enhancement of pictorial visual

information, which in turn, reveals enough details to

allow proper interpretation for intended application.

3. Point Operations

T

Dhiraj R Gawhane et al , Int.J.Computer Technology & Applications,Vol 5 (1),87-91

IJCTA | Jan-Feb 2014 Available [email protected]

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Point operationsare nothing but simplest image

filters, where the new value of a pixel is only

determined by the original value of that single pixel

alone. As mentioned [9], point operations perform

modification of pixel values without changing the

size, geometry or local structure of the image. The

pixel value is given by a = I (u, v), which depends

exclusively on the previous value a = I (u, v) at the

same position. This pixel value is independent from

any other pixel value, including any of its

neighbouring pixels. To map the original pixel values

to the new values a function f (a) is used [9],

a’ ← f(a) I’ (u, v) ← f ( I (u, v) )

for each image point with a spatialcoordinate (u, v).

The most commonly used point operations for

image enhancement are: A) Contrast manipulation,

B) Brightness manipulation, C) Inverting image

operation and D) Threshold operation.

3.1 Contrast Manipulation

To enhance the visibility of an image, pixel values

above a given threshold are made more brighter and

values below it are made more darker by a constant

value, given by „valueToAdd‟ and „valueToSubtract‟

respectively. Below shown algorithm is for a single

pixel input. For a colour image of size (m*n*3), this

algorithm will run in parallel for Red, Green and

Blue components (m*n) times.

Fig. 1 Contrast Manipulation Algorithm

3.2 Brightness Manipulation

Brightness Manipulation is categorized into two

parts: A) Brightness addition and B) Brightness

subtraction. Brightness addition involves making a

dark region in an image brighter by adding a constant

value, given by „value‟ to each pixel of an image.

Similarly, brightness subtraction makes entire image

less bright by subtracting a constant value given by

„value‟ from each pixel of an image. This algorithm

runs in a similar fashion as explained in 3.1.

Fig. 2 Brightness Manipulation Algorithm

3.3 Inverting Image Operation

Inverting image operation refers to the technique

of reversing the pixel values of an image, to obtain an

image equivalent to photographic negative of that

image. Its major application is in medical image

processing and astronomy. This operation involves

reversing the ordering of pixel values (by multiplying

with -1) and adding a constant value to map the result

to the admissible range again [9]. It results in the

improvement of visibility of details of an image. For

a pixel value a = I (u, v) in the range of [0,255], the

inverting image operation result is

finvert(a) = - a + amax = amax - a

For an 8-bit imageamax= 255.

To perform the above operation on a colour

image, a common procedure is to take the average of

three colour components of each pixel in order to

equalize the values of the three colour components of

each pixel.



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Req = Geq = Beq = (Rin + Gin + Bin) / 3

Fig. 3 Inverting Image Algorithm

3.4 Threshold Operation

To isolate an object of interest from its

background, threshold operations are used. Threshold

operation is mainly performed on a grayscale image

to convert it into a binary image. Depending upon the

threshold value, any pixel value above the threshold

is assigned the maximum value and any pixel value

less than the threshold is assigned to the lowest value.

Where a0 = 0, a1 = amax and 0<ath<amax.

Fig. 4 Threshold Operation Algorithm

4. Design of the IP Processor

The design of the proposed IP Processor (namely Im-Pro) is accomplished as shown in the fig. 5. The

block diagram is an abstract description of the

processor. Design is split into data-path unit and

control unit. Memory unit has four memory banks,

each having a storage capability of 256 X 256 Bytes.

These banks are intended to save the red, blue, green

and grey matrices of the image under processing.

The control unit is the brain of the processor

which routes the data and executes the instructions in

conjunction with the IP Unit. IP unit is analogues to

the ALU of a general micro-processor. The following

subsections elaborate the design of the three sub-

modules in detail.

Fig. 5 Architectural Block Diagram of Im-Pro

4.1 Processor

The top module has three main inputs clock, reset,

an eight bit bus capable of carrying instructions and

data. An additional signal ILE_bar determines

whether the given data is an Instruction or a Data.

4.2 Memory Block

Similar to the concept of registers used in the

conventional processors, the proposed Im-Pro needs a

memory buffer to save the intermediate results of the

processing as well as the final results. The minimum

size of the buffer needed is four times the size of the

image for the reasons mentioned above. The memory

should be addressable pixel by pixel with read write

capability. The design has been done assuming an

input image of size 256X256X3 with eight bit

resolution, but the concept used here is scalable and

can be comfortably scaled for a given size. A serial

input serial output style of memory is employed

which will use minimum resources, but at the cost of

reduced speed.

4.3 Control unit



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The control unit is the brain of the Im-Pro. Its

major task is to control the dataflow and instruction

execution [1]. It is responsible for accessing the data

from the memory, feeding it to the IPU and writing

the output of the operation back to the location from

where the respective data has been fetched. This is

the only module which communicates with the

external world. The concept of pipelined architecture

is introduced where Fetch,Execute happen in parallel

at any given instant of time [2].

4.4 IP unit

The IPU implemented as of now is capable of

performing the four fundamental image enhancement

operations. The remaining four are reserved for

future. The IPU is capable of performing one

operation at a time. The D_in_ready pin is a level

triggered input, which signals the start of the

operation and D_out_ready will indicate the end of

operation after which the stable output data is

available. The control unit gets this output and then

writes it back to the memory location. The IPU

operates at a lesser clock frequency as it is supposed

to perform the operation on four pixels one at a time.

A divide by four clock divider sub module which is a

part of Control unit, generates this clock.

Table 1Opcodes Used For Operations

Opcode Instruction

000 Contrast manipulation

001 Brightness manipulation

010 Inverting

011 Thresholding

1XX Reserved for future

4.5 Behavioural Simulation

The functional verification of this Design is a real challenge and an uphill task. The conventional VLSI

approach of exhaustive testing is a time consuming

affair, yet it is the only way to guarantee the

exactness of the design. The standard Lena.jpg

(256X256X3) colour image has been converted into

the matrix form using MATLAB 7.10.0. The

resulting text file is converted into binary single

column data format using a C program. This data has

been used for testing the Im-Pro. The data obtained

from the processing is again written back into the text

file and reverse process of the above has been done to

visualize the image.

5. Implementation and Results

The technology independent RTL schematic of the implemented Verilog model of Im-Pro and the

experimental results obtained for an 8-bit RGB

colour image (lena.jpg) are shown below, when point

operations, as described in the previous section are

applied.

Fig. 6 RTL Schematic of an Im-Pro

A. Contrast Manipulation Parameters: Threshold = 150, ValueToAdd = 10,

ValueToSubtract = 20.

Fig. 7 Verilog Result of Contrast Manipulation

(RHS Image)

B. Brightness Manipulation

Parameters: value = 60.

Fig. 8 Verilog Result of (Sign = 1) Brightness

Addition (RHS Image)



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Fig. 9Verilog Result of (Sign = 0) Brightness

Subtraction (RHS Image)

C. Inverting Image Operation

Fig. 10Verilog Result for Invert Operation (RHS

image)

D. Thresholding Operation

Fig. 11Verilog Result of Threshold Operation

using a Threshold = 110 (RHS Image)

6.Conclusions and future scope

Image Processor has been designed and

implemented using Verilog HDL and simulated using

ISim from Xilinx ISE Design Suite 14.6 and

synthesized using Xilinx XST. With lot of image

processing creeping into the PDA and other hand

held equipment, there is an urge for providing a

specialized Image Processor. This work gives an

insight into the most generalized architecture that can

be customized for other image processing

applications too. Though, the most fundamental point operations on the image are discussed, the idea may

be carried forward for designing filtering applications

also. The major challenge in this work is to choose a

proper FPGA for prototyping, since the memory

buffer needs enormous memory, the crucial aspect is

to choose such an FPGA which has enough RAM,

FIFO resources.

Acknowledgement

The Authors would like to thank the Department of

Electronics Engineering, Visvesvaraya National

Institute of Technology, Nagpur for Technology

Support.

References

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[7] Gonzalez, R. C., Woods, R. E., &Eddins, S. L. (2009).”Digital image processing using MATLAB”

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