design and implementation of energy-efficient analog front-end...
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SS LSemiconductor System Lab
Sunyoung Kim 1
Design and Implementation of Energy-Efficient Analog Front-End Circuit
for a Sub-1V Digital Hearing Aid Chip
Sunyoung Kim
June 28, 2005Semiconductor System Laboratory
Korea Advanced Institute of Science and Technology
MS Thesis
SS LSemiconductor System Lab
Sunyoung Kim 2
Outline
• Motivation• Proposed Analog Front-End Circuit• Building Blocks
– Preamplifier with combined gain control– Σ-Δ Modulator with adaptive-SNR
• Implementation Results• Conclusions and Further Works
SS LSemiconductor System Lab
Sunyoung Kim 3
Outline
• Motivation• Proposed Analog Front-End Circuit• Building Blocks
– Preamplifier with combined gain control– Σ-Δ Modulator with adaptive-SNR
• Implementation Results• Conclusions and Further Works
SS LSemiconductor System Lab
Sunyoung Kim 4
Motivation• More and More Needs
on Digital Hearing Aid
• More Design Requirements– Low-power consumption– Small size– Programmability– Low cost CMOS process
[Newsweek. June 6, 2005]“…more than 28 million Americans have some degree of hearing loss,a number that could reach 78 million by 2030…”
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Motivation (Cont’d)
• Americans with hearing trouble*
*Mild to severe hearing loss,2002. Sources:NATL. Health interview survey, CDC
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Overview of the Digital Hearing Aid
*[ISSCC2002. John W. Fattaruso et.al.]
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Outline
• Motivation• Proposed Analog Front-End Circuit• Building Blocks
– Preamplifier with combined gain control– Σ-Δ Modulator with adaptive-SNR
• Implementation Results• Conclusions and Further Works
SS LSemiconductor System Lab
Sunyoung Kim 8
CGC Preamplifier
• Low Power Consumption• Controllability with combined gain control
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Sunyoung Kim 9
Adaptive SNR Σ-Δ Modulator
• Multiple SNR values with adaptive SNR
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Needs of Adaptive-SNR Values
• Normal sound level from 30 to 90-dB SPL– High performance Σ-Δ Modulator
• Sufficiently large sound above 90-dB SPL– Medium performance Σ-Δ Modulator
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Environment-Aware Operationlow-resolution operation with normal SNR
(power-reduction)
high-resolution operation with enhanced SNR
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Proposed Analog Front-End
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Sunyoung Kim 13
Outline
• Motivation• Proposed Analog Front-End Circuit• Building Blocks
– Preamplifier with combined gain control– Σ-Δ Modulator with adaptive-SNR
• Implementation Results• Conclusions and Further Works
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Sunyoung Kim 14
CGC Preamplifier
⎟⎟⎠
⎞⎜⎜⎝
⎛−
−⎟⎟⎠
⎞⎜⎜⎝
⎛−
+==VCdd
x
VCdd
x
VVVLW
VVVLW
INOUTAv 1/1 1221
xVC
xVC
VVVVVV
+=−=
2
1
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How to obtain multiple SNR values• Multiple Clock Frequencies☺ Various SNR values with small power
consumption Difficult to design by analog circuit
• Multiple Orders of the Σ-Δ Modulator☺ Large SNR variations
High power consumption due to additional OTAUnstable @ > 3rd order Σ-Δ modulator
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Adaptive SNR Σ-Δ Modulator• Combine only the strong points of the two
methods☺ Variable clocking : 1.024-MHz or 2.048-MHz☺ Various order : 2nd or 3rd order
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Adaptive SNR
• SW1 determines the number of integrators• SW2 decides the clock frequency
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• The combination of SW1 and SW2 allows the Σ-Δmodulator to obtain four kinds of SNR
Details of Adaptive SNR Σ-Δ Modulator
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2nd order Σ-Δ Modulator
• 2nd order Σ-Δmodulator when the /SW1 is closed
INN
INP
OUTN
OUTP
VREF
'dd
d
'
'
st ndVCM
VREF VCM
rd ff
ff'd
COMP1 COMP2
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3rd order Σ-Δ Modulator
• 3rd order Σ-Δmodulator when the /SW1 is opened
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Low Power OTA
• DC gain : 77.6-dB• Unity gain bandwidth : 7.07-MHz• Phase margin : 55°@ 3-pF load• Power Consumption : 15-μW
Size optimization
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Outline
• Motivation• Proposed Analog Front-End Circuit• Building Blocks
– Preamplifier with combined gain control– Σ-Δ Modulator with adaptive-SNR
• Implementation Results• Conclusions and Further Works
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Sunyoung Kim 23
Chip Microphotograph• 0.25-μm CMOS Process • 0.9-V supply voltage• 0.5-mm2 active area
– Preamplifier : 0.1-mm2
– Σ-Δ Modulator : 0.4-mm2
• Power consumption– < 74.7-μW
• Peak SNR – 72-dB(2nd ), 86-dB(3rd)
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Measured Performance- CGC Preamplifier
• By reducing VTH, the threshold knee point is decreased simultaneously
VTH=0.14VVTH=0.13V
VTH=0.15V
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Attack and Release time- CGC Preamplifier
0.1-V 0.1-V0-V
Measured attack and release response
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Measured SNR - Adaptive SNR Σ-Δ Modulator
Measured output spectrum
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SNR variation - Adaptive SNR Σ-Δ Modulator
Measured SNR/SNDR versus input amplitude
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Performance Summary
38-μW35-μW33-μWVVC=0.85VVC=0.8VVC=0.75Power dissipation
(Preamplifier)
Signal bandwidth
Total power dissipation(Analog front-end)
Power dissipation(Σ-Δ Modulator)
Peak SNR Clock frequency (MHz)
TypeOrder
Supply voltage
26.4-μW
72-dB1.024
12nd order
36.7-μW35.7-μW26.8-μW
86-dB78-dB81-dB
0.9-V
59.4-μW ~ 74.7-μW(According to the parameter value)
2.0481.0242.048
8-kHz
4323rd order
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86-dB
92-dB
77-dB
Peak SNR
0.25-μm59.4-μW0.9-VThis work
0.6-μm190-μW1.1-VJSSC 2002[D. George Gata]
0.8-μm323-μW2.15-VJSSC 1997[Harry Neuteboom]
Process(CMOS)
Power Consumption
Supply Voltage
Performance Comparison
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Power Consumption ComparisonPo
wer
con
sum
ptio
n (u
W)
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Outline
• Motivation• Proposed Analog Front-End Circuit• Building Blocks
– Preamplifier with combined gain control– Σ-Δ Modulator with adaptive-SNR
• Implementation Results• Conclusions and Further Works
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Sunyoung Kim 32
Conclusions• Digital Hearing Aid Preamplifier with
Combined Gain Control– Controllability and Wide dynamic range– Low power consumption
• Σ-Δ Modulator with Adaptive-SNR– Optimized Power consumption wrt input condition
• Average power consumption of the proposedHearing Aid Front End< 74.7-μW @ 0.9-V Supply
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Further Works• Design and Implementation of Digital
Hearing Aid with Combined Gain Control and Adaptive-SNR
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Supplementary
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CGC Preamplifier• Opamp. with MOS Resistive Circuit (MRC)
– Small Area– Ease of Tunability for Future AGC
MRC1
MRC2
vo
VG1 VG2
V'G1 V'G2
vi
1
2
3
4
VG1 VG2
T1
T2
T3
T4
I1
I2
)V(VLWK
RG2G1P
MRC−
=1
RMRC
RMRC
V1 V3
V2 V4
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Details of Adaptive SNR Σ-Δ Modulator
INN
INP
OUTN
OUTP
/SW1
VREF
COMP1 COMP2 DFF
'd 'd
'd'd
d d
dd '
''
'
'
'
'
'
'd
'd
d
d
ff
ff
1st Integrator 2nd Integrator 3rd IntegratorVCM
VREF VCM VREF VCM
VREF VCM
/SW1
SW1
VREF VCM
VREF VCM
SW1
SW1
SW1
/SW1COMP1 COMP2
(b) Timing diagram of the clock
(a) Schematic of the Adaptive SNR Σ-Δ Modulator