design and implementation of flash adc using tiq and...

International Journal of Advanced Computing and Communication Systems (IJACCS)vol.1 Issue.1 March 2014. ISSN: 2347 – 9299 / 2347 – 9280

82 | P a g e www.ijaccs.com Copyright@IJACCS

ABSTRACTThe main design blocks of Flash ADC includes the

design of comparator, decoder and digital to analogconvertor. The design of comparator is the most critical task inthis paper because the performance of ADC depends on thechoice of comparator. This paper describes the design of highspeed FLASH ADC using clocked digital comparator with 4-bitresolution. Analog signal is characterized by the signal whoseamplitude is continuously changing with respect to time. Theclock digital comparator is designed in TSMC 0.18 μm CMOStechnology with supply voltage of 1.8 V. The length oftransistor is fixed and depending upon the width of transistor,internal references voltages are generated in the range of0.653 to 1.02 V. The proposed 4-bit flash ADC using CDC isdesigned using multiplexer based Decoder and simulated withthe help of TANNER-EDA tool in TSMC 0.18 μm CMOStechnology. High speed clocked digital comparator withinverter configuration is used for dynamic offset suppression.The comparison of result are shown in the result part.

Keywords:- Flash ADC, CMOS-Clocked Digital Comparator,Multiplexer Analog to digital convertor, Transistor InverterQuantizer (TIQ).

INTRODUCTIONAnalog to digital convertor circuit converts

continuously changing analog signal into digital signal. Analogsignal is characterized by the signal whose amplitude iscontinuously changing with respect to time while theamplitude and time is discrete in case of digital signal. TheADC is characterized by three-factors namely speed, area, andpower consumption, the cost of ADC is varying fromapplication to application. According to moor’s law as thetechnology shrinks the speed of device increase and thesupply voltage decrease this is the quite challenging in CMOStechnology. Flash ADC with Clocked Digital Convertor (CDC)configuration eliminates the resistive network required forgeneration of internal reference voltage. Flash Analog toDigital Convertor (FADC) consists of two stages. In first stageClocked Digital Comparator (CDC) have back-to-back inverterconfiguration followed by transmission gate. Transmissiongate is used for sampling. Second stage of ADC consists ofmultiplexer based decoder, which requires less hardware andhas short critical path. In multiplexer based decoder, middlebit is used as select line of 2:1 MUX because it consists of twostages (0 and 1) rest of the bits follows the thermometer codehence the MSB of output binary code is exactly same as the

middle bit. The second MSB and LSB’s of output binary bitsare obtained depending on the value of middle bit, if the valueof middle bit is 0 then multiplexer based decoder circuit selectthe upper bits (Right side bits of middle bit) and if value ofmiddle bit is 1 then it selects lower bits (Left side bits ofmiddle bit).

CLOCKED DIGITAL COMPARATORFor conversion of analog signal into digital signal

requires the quantizer, sampler and encoder. In clocked digitalcomparator as shown in fig. 1, the first stage consist of twoinverter, the first inverter is acting as the quantizer by settlingthe comparator voltages for comparison and the secondinverter is acting as the logic level inversion. The need ofsecond inverter arises due to the output of first inverter. InADC and DAC structure, the output should be same as theinput signal but the first inverter inverts the input and lateron, we will get the output out of phase, so for nullifying thephase shift, we have to add the second inverter.

Fig.1 Clocked Digital Comparator

TRANSISTOR INVERTER QUANTIZERComparator structure is most pivotal part in FADC

architecture. The role of comparator is to compare the inputsignal with reference voltage and gives the respective logiclevels (1 and 0) the comparator converts the input signal intoonly two logics (logic1 and logic 0) depending on the values ofinput, if the values of input is greater than threshold valuethen it’ll give logic 1 else it’ll give logic 0. The TIQ shown in fig2 is the first stage of Clocked Digital Comparator, it is use forgenerating the internal reference voltage, which is requiredfor comparison, and the internal reference voltage isgenerated using number of methods namely resistive laddernetwork, systematically varying the size of transistor.

Design and Implementation of Flash ADC using TIQ and TransmissionGate for High Speed Application

Abhishek MadankarDept. of E&TC EngineeringY. C. College of Engineering

Nagpur, [email protected]

Sandeep KakdeDept. of Electronics Engineering

Y. C. College of EngineeringNagpur, India

[email protected]

Abhijit AsatiEEE Group

Birla Institute of TechnologyPilani, India

[email protected]



















[email protected]



[email protected]



















[email protected]



[email protected]


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Fig.2 Transistor Inverter Quantizer (TIQ)

In Transistor Inverter Quantizer (TIQ), systematicvarying the width of NMOS and PMOS transistors generatesthe internal reference voltage. We are keeping the length oftransistor is same because the length of transistor depends onthe technology.

CMOS INVERTER AS PHASE SHIFTERThe inverter provides phase shift, amplification,

quantization stages. Let us consider the signal given to theclocked digital comparator is sine wave then inverter gives theoutput negative of sine wave,

( ) * ( )X t A SIN wt as input inverter gives

1( ) * ( )X t A SIN wt we further solved this equation by

applying some mathematical relationship

( ) ( * ) ( * )SIN A B SINA COSB COSA SINB

1( ) ( * ( )* ( )) ( * ( )* ( ))X t A SIN wt COS A COS wt SIN

1( ) * ( )

[ ( ) 1

( ) 0]

X t A SIN wt

COS

SIN

CMOS INVERTER AS QUANTIZERThe Clocked Digital Comparator compares the input

voltage with reference voltage generated internally by varyingthe width of each comparator. Depending on the value ofreference voltage, each comparator gives its logic level. Thefour-bit comparator requires fifteen comparators since they’llgenerate their respective fifteen levels and act as quantizer.

TRANSMISSION GATEThe second stage consist of transmission gate, the

use of transmission gate is for sampling the signal as we knowthe transmission gate work on clock signal if the transmissiongate is positive edge enabled clocked then it works only forpositive edges that means it only pass the logic for positiveedge and blocked the logic for negative edge that’s why wegenerally called transmission gate as the switch. Thefrequency on which clocked operates called as samplingfrequency and the sampling frequency should be more thantwice of input frequency, so the clocked digital comparator isacting as the quantizer and sampler.

Fig.3 Tanner Implementation of Transmission Gate

MULTIPLEXER BASED DECODERThe multiplexer based decoder consists of 2:1

multiplexer, which requires 11 multiplexer for implementationof 15 inputs. The 2:1 multiplexer requires two input signalswith one select line, depending on the select line input willselected, the M.S.B. bit of binary input equal to middle bit ofthermometer code because it uses the twin logic.

Table.I Conversion of 3-bit thermometer to binary codeThermometer code Binary Code

T3 T2 T1 B2(MSB) B1

0 0 0 0 0

0 0 1 0 1

0 1 1 1 0

1 1 1 1 1

Fig.4 Tanner Implementation of MUX Based Decoder












1( ) * ( )

[ ( ) 1

( ) 0]

X t A SIN wt

COS

SIN









T3 T2 T1 B2(MSB) B1

0 0 0 0 0

0 0 1 0 1

0 1 1 1 0

1 1 1 1 1













1( ) * ( )

[ ( ) 1

( ) 0]

X t A SIN wt

COS

SIN









T3 T2 T1 B2(MSB) B1

0 0 0 0 0

0 0 1 0 1

0 1 1 1 0

1 1 1 1 1




DIGITAL TO ANALOG IMPLEMENTATIONThe DAC configuration shown in figure 5 consist of a

network of resistor alternating in value of R and 2R. Startingfrom bottom of network the 2R resistor is connected to theVref- the digital input decides which resistor is switched toVref- and Vref+.

Fig.5 Digital to Analog Convertor

WORKING WITH ADC-CDCThe comparators are working on their internal

reference voltages. As the input signal, amplitude crosses thethreshold value of reference voltage. Comparator works, andgenerates thermometer code. As the input signal crossesmaximum value of amplitude then all comparator moves tothe saturation region they produces the output equal to logic1. After interfacing ADC and DAC together, they must producethe output same as the input signal which is shown below.The threshold voltages are laying in the range from 0.653 to1.02 volt for this range ADC produces the respective binarybits. Below this range, the output equals to zero and abovethis range, the output equals to one. During positive intervalof clock, it produces output; otherwise zero. The above logic isvalid only when the amplitude of input signal starts from zeroand reaches toward the maximum value as the amplitude fallsfrom the maximum value toward zero value the effect ofmobility arises. As we know, the mobility of electron is equalto the three times the mobility of hole, the output is not sameas the input.

When the input is at logic zero, the pmos producesthe output equal to logic one but if you observe, as the pmosconducts, it will connect to the VDD (positive supply) supply. Itrequires some delay but in case of NMOS transistor, when itconducts it will connect it to ground (negative supply). It willconnect to the ground fast as compare to PMOS that is whythe output is not exactly same as the input.

Fig.6 Tanner Implementation of Analog to Digital Convertor

Fig.7 Tanner implementation of ADC-DAC

SIMULATION RESULT

Fig.8 Tanner implementation of TIQ

The Intersection between input signals with theoutput signal gives the internal reference voltage required forcomparison. The range of reference voltage is 0.653-1.02 volt.The flash ADC produces the binary output according to theAmplitude of Input signal. As the input signal crosses first(0.653) and last (1.02) referance voltage it genrate “ 0000”and “ 1111”.











SIMULATION RESULT













SIMULATION RESULT





Fig.9 DC Sweep Transfer Characteristic of CDC

Fig.10 Output Waveform for 4-bit Flash ADC

Simulation Results of DAC for 180 nm technologyThe Input binary bits generate the output analog

signal. The DAC is based on the binary weighted sum of theinput. It generates amplitude of output signal 0.653 for“0000” Input and 1.02 for “1111” Input.

Fig.11 Output Waveform for 4-bit Flash DAC

Simulation Results of ADC-DAC for 180 nm technologyThe output generated by ADC-DAC look like Input

signal. The ADC-DAC produce the output signal based on thebinary bit generated by ADC, The ADC generate output bitranging from “0000” to “1111” only for the range of Internalreference voltage of comparator.

Fig.12 Transient Result of ADC and DAC for 4-bit Resolution

TABLE.II Comparison with standard design / Standard Result/Expected Result

Parameter Specification Ideal value

Architecture Flash Flash

Resolution 4 bit 4 bit

Power Supply 1.8 v 1.8v

Technology TSMC 0.18 um TSMC 0.18 um

Sampling Frequency 1 GHz 1 GHz

Input Frequency 10 MHz 10 MHz

SNR 25.05 dB 25.84 dB

ENOB 3.86 Bit 4 Bit

DNL +0.059/-0.0325LSB +0.5 LSB/-0.5 LSB

INL +0.0032/-1.5 LSB +0.5 LSB/-0.5 LSB

Reference Voltage 1.02/0.653 1.02/0.653

Fast Fourier Transform (FFT) ResultThe fast Fourier Transform plot is required for

finding out the Dynamic Parameters like Signal to Noise Ratio(SNR) , Spurious Free Dynamic Range (SFDR), Dynamic Range(DR) and Effective Number of Bits (ENOB).



















SNR 25.05 dB 25.84 dB

ENOB 3.86 Bit 4 Bit

DNL +0.059/-0.0325LSB +0.5 LSB/-0.5 LSB

INL +0.0032/-1.5 LSB +0.5 LSB/-0.5 LSB






















SNR 25.05 dB 25.84 dB

ENOB 3.86 Bit 4 Bit

DNL +0.059/-0.0325LSB +0.5 LSB/-0.5 LSB

INL +0.0032/-1.5 LSB +0.5 LSB/-0.5 LSB






Fig.13 Fast Fourier Transform (FFT) Result

CONCLUSIONThe design of Flash ADC includes the design of

comparator, decoder and digital to analog convertor. Thedesign of comparator is the most critical task in this paperbecause the performance of ADC depends on the choice ofcomparator. In this paper, CDC is used which is suitable forincreasing the speed of ADC. Decoder architecture used isMultiplexer Based decoder, which will reduce the complexity.The DAC architecture is implemented with the help ofResistive Ladder Network.The Static characteristics likeDifferential Non Linearity error (DNL) and Integral NonLinearity error (INL) are found in the range of +0.059/-0.00325LSB and +0.0032/-1.5 LSB and Dynamic characteristics likeSNR, SFDR, DR and ENOB are found as 25.05 dB, 22.33 dB,26.66 dB and 3.86 bit. The Flash ADC and DAC is implementedand characterized in the following ways: 1) No externalResistor array is needed for generating the internal referencevoltages. 2) The Multiplexer based Decoder is used due towhich the hardware requirement Reduces. 3) No need ofsample and hold circuit which will cause the increment inspeed.4) Less possibility for the meta-stable output due tohigh switching speed of CDCs.

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