design and implementation of frequency synthesizer and interrogating phase noise in it's parts
DESCRIPTION
In The Name Of God. Design And Implementation Of Frequency Synthesizer And Interrogating Phase Noise In It's Parts. Advisor Professor : Dr.Sadr & Dr.Tayarani Students: Majid Sodagar Mehran Mohammadi Izad. Brief Review. Introduction Block Diagrams Models Oscillator Divider - PowerPoint PPT PresentationTRANSCRIPT
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Design And Implementation Of Frequency Synthesizer And Interrogating Phase NoiseIn It's Parts
Advisor Professor : Dr.Sadr & Dr.TayaraniStudents:
Majid SodagarMehran Mohammadi Izad
In The Name Of God
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Brief Review
• Introduction• Block Diagrams• Models
– Oscillator– Divider– Charge Pump
• Design And Measurements• Conclusions
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Signals Suffer From Noise !
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Introduction & Motivation
• The GSM system needs very narrow channel spacing
• Thus low phase noise levels are required.
• e.g. , At 1 kHz from the carrier, a single sided spectral noise density of -80 dBc/Hz
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Conventional Synthesizer Block Diagram
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PLL Block Diagram And Noise Sources
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Transfer Functions
1 1( )
( ) !1 1
1 ( )
v
Refv
K K z sPNout R SH s LowPassPN K K z s
S N
1( )
( ) !1 1
1 ( )
v
CPv
K z sPNout SH s LowPassPN K K z s
S N
1( ) !
1 11 ( )vco
v
PNoutH s HighPass
PN K K z sS N
1
1( )
( ) !1 1
1 ( )
v
divider vN
K K z sPNout SH s LowPassPN K K z s
S N
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Typical Superposition Of All Sources
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Oscillator Noise Modeling
• LTI Model (Leeson-Cutler)- Ignoring Time Variance Nature of
Oscillator
• LTV Model (Hajimiri-Lee)- Take the Time Variance Nature of
Oscillator into account.
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Typical LC Oscillator
A = Excess noise FactorN = For Active Inductor
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LTI Model
Using Only Z(s) of tank circuit
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Typical Phase Noise Slopes Close to Career
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LTV Model
• Every oscillator is a quasi periodic system
• the noise analysis should take this into account
• Model Benefits:– Design Aspects– Cyclostationary noise
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Impulse Response
The constant qmax = CVpeak issimply a normalization constant, thepeak charge in the oscillator.
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Graphical Interpretation
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Divider Block Model
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Divider Noise Model
2
,
2( ) ( ) ( )
vco
vcof w lf
f MS f S f S f
n
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Filter Noise
• Ignoring Thermal noise of Passive elements And Current Noise
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Typical OpAmp Input Voltage Noise
• Our OpAmp Performance (OP27): 3nv
RMS Voltage noiseHz
2ncf Hz
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Charge Pump PFD Structure
• Lead And Lag Detection• Increasing Lock Range• Reduction of cycle slipping
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Effects Of CP PFD On Phase Noise
• Effect of Leakage On reference Spurs– Charge pump is off majority of the
Time– Leakage causes VCO tuning voltage
to change• Effect of Mismatch On reference Spurs
– The width of correction pulses is related to the mismatch
– causes the AC voltages• undesirable AC voltages Causes FM
modulation
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Experimental Results for FM modulation (Spurs)
Reference Spur example
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CP Phase noise model
• Where
– Fc = Flicker Corner Frequency– Fm = Offset From Carrier– I0 = current noise Floor
0( ) 10log 1 cm
m
fL f I
f
2 /A Hz
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2 RefK
Stability problem In CP PLL
• The charge pump nature is discrete so it is prone to instability
• The following condition should be satisfied to use continuous time analysis !!
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Our Design
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Design Specification
• Design for GSM requirements
– Fref = 10MHz– Fcomp = 200KHz– LoopBandWidth = 15KHz– RFOut = 800 – 1100 MHz– PhaseMargin = 45 deg
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Schematic
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Active Filter
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Simulated Open Loop Response
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Passive Phase Noise Result @1KHz
Phase noise = -53.7-10log(200) = -76.7 dBc/Hz
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Passive Phase Noise Result @10KHz
Phase noise = -51.9-10log(200) = -74.9 dBc/Hz
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Passive Phase Noise Result @100KHz
Phase noise = -70.2-10log(500) = -92.9 dBc/Hz
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Step Response And Lock Time
• Settling time = 150 sec
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Active Phase Noise Result @1KHz
Phase noise =-55.1-10log(200)= -78.1 dBc/Hz
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Active Phase Noise Result @10KHz
Phase noise =-49.7-10log(200)=-72.7 dBc/Hz
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Inappropriate Opamp Bias !!!
Causing excess noise near the career
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1Hz Normalize Phase Noise
• Good way for characterize the phase noise of PLL
• Assumes charge pump phase noise is dominant
• PN=PN1Hz+20logN+10log(Fcomp)
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Experimental Result:
• For our design:
– PN1Hz = -205 dBc/Hz– N = 4500– Fcomp = 200KHz– PN =-205+20log(4500) +10log(200KHz)
= -78.9 dBc/Hz
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Conclusions
• By using better synthesizer, its possible to achieve lower Phase noise
• If the CP noise Dominates in the circuit, then we can not detect the effect of Active filter noise
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• Any Question?
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Thanks