design and implementation of reed solomon code used on smsa in fpga

7/22/2019 Design and Implementation of Reed Solomon Code Used on Smsa in Fpga

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DESIGN AND IMPLEMENTATION OF REED

SOLOMON CODE USED ON SMSA IN FPGA

By

RAMAMOORTHY.S

A PROJECT REPORT-PHASE II

Submitted to the

FACULTY OF INFORMATION& COMMUNICATION

ENGINEERING

In partial fulfillment of the requirements for the award of the degree

Of

MASTER OF ENGINEERING

IN

APPLIED ELECTRONICS

ANNA UNIVERSITY

CHENNAI 600 025

JULY, 2013

ANNA UNIVERSITY: CHENNAI 600 025



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BONAFIDE CERTIFICATE

Certified that this project titled “DESIGN AND IMPLEMENTATION

OF REED SOLOMON CODE USED ON SMSA IN FPGA” is the

bonafide work of “RAMAMOORTHY.S (Reg.NO:411911401016) who

carried out the research under my supervision. Certified further, that to

the best of my knowledge the work reported herein does not from part of

any other project report or dissertation on the basis of which a degree or

award was conferred on an earlier occasion on this or any other

candidate.

SIGNATURE SIGNATURE

Mrs.V.ANITHA M.E., Mr.A.RAJAN M.Tech.,

SUPERVISOR, HEAD OF THE DEPARTMENT,

ASSISTANT PROFESSOR, ASSISTANT PROFESSOR,

DEPT OF ECE, DEPT OF ECE,

ShriAndalAlagar College of Engg, ShriAndalAlagar College of Engg,

Mamandur-603 111, Mamandur-603 111,

Submitted to project and viva examination held on ………………

INTERNAL EXAMINER EXTERNAL EXAMINER



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ABSTRACT

In the present world, communication has got many

applications such as telephonic conversations etc. in which the messages

are encoded into the communication channel and then decoding it at the

receiver end. During the transfer of message, the data might get corrupted

due to lots of disturbances in the communication channel. So it is

necessary for the decoder tool to also have a function of correcting the

error that might occur.

Reed Solomon codes are type of burst error detecting codes which

has got many applications due to its burst error detection and correction

nature. My project Non Binary codes are robust to the simplified min

sum algorithm has been proposed. Based on the SMSA, a high-

throughput RS decoder is designed. Increasing the parallelism and

throughput of decoder are the advantage of the proposed system. The

main idea of the RS decoder is to reduce the computational complexity of

the design. RS decoder can be used to find the exact solution first, the

design increases the parallelism and throughput of the decoder by three to

four times.

The implementation results for the decoder show high throughput

of 64 Mbps at 15 iterations. And design saves memory usage by 38%

to76%. Third, this design shows 2.64 area efficiency improvements.

Key point: SMSA, LDPC-Decoder, RS-Decoder, FPGA



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ACKNOWLEDGEMENT

I submit our sincere heart-felt thanks to our beloved chairperson

Mrs.PRREMALATHAVIJAYAKANT and our secretary cum

correspondent Mr.L.K.SUDHISH for being provided good facilities and

infrastructure to complete our project.

I would like to express our deep sense of gratitude to our respected

principal Dr.R.KARTHIKEYAN for his guidance and motivation.

I immensely thank Mr.A.RAJAN, head of the department,

electronics and communication engineering for constant guidance and

motivate ideas through this project work.

I also thank our project coordinator Mr.T.R.GANESH BABU,

assistant professor, department of ECE for his valuable suggestion which

helped us to complete the project successfully.

And I also express our sincere thanks to our project guide

Mrs.V.ANITHA, assistant professor, department of ECE for guidance.

Last but not least we extend our sincere thanks to all the teaching

and non teaching staff members who have contributed their ideas for the

betterment of the project.



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TABLE OF CONTENTS

CHAPTER NO TITLE PAGE NO

ABSTRACT iii

ACKNOWLEDGEMENT v

LIST OF FIGURES ix

LIST OF TABLES x

LIST OF ABBREVIATIONS xi

1. INTRODUCTION 1

1.1 OVERVIEW 1

1.2 ERRORS AND METHODS 3 1.2.1 AUTOMATIC REPEAT REQUEST 3

1.2.2 FORWARD ERROR CORRECTION 4

1.3 ERROR CONTROL CODING 5

1.4 CLASSIFICATION OF FORWARD ERROR CORRECTION CODES 5

1.5 EFFICIENT IMPLEMENTATION OF APPLICATION PRIMITIVES 6

1.6 ADAPTIVE SYSTEM DESIGN AND SCHEDULING 6

2. LITERATURE SURVEY 7 2.1. LITERATURE SURVEY 7

2.2 EXISTING SYSTEM 9

2.3. DRAWBACKS 10

3. LDPC CODER 11

3.1 INTRODUCTION TO LDPC 11

3.2 TURBO CODES 12

3.3 PERFORMANCE OF ERROR CORRECTING CODES 123.4 FORWARD ERROR CORRECTION 12

3.5 HOW IT WORKS 13

3.5.1 AVERAGING NOISE TO REDUCE ERRORS 14

3.5.2 TYPES OF FEC 14

3.5.3 CONCATENATED FEC CODES FOR IMPROVE

RFORMANCE 15

3.6 LOW-DENSITY PARITY-CHECK 15

3.7 CHANNEL CAPACITY 16



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3.8 BASIC COMMUNICATION MODEL 16

3.9 DECODING LDPC CODES 20

4. REED – SOLOMON CODES 21

4.1OVERVIEW 214.2 PROPERTIES 22

4.3 REED SOLOMON ENCODING 23

4.4 REED SOLOMON DECODING 23

4.5 REED SOLOMON ERROR PROBABILITY 24

4.6 ARCHITECTURES FOR ENCODING AND DECODING

REED-SOLOMON CODES 25

4.6.1FINITE (GALOIS) FIELD ARITHMETIC 25

4.6.2GENERATOR POLYNOMIAL 25

4.7 ENCODER ARCHITECTURE 25

4.8 DECODER ARCHITECTURE 27

4.8.1 SYNDROME CALCULATION 27

4.8.2 FINDING THE SYMBOL ERROR LOCATIONS 28

4.8.3FIND AN ERROR LOCATOR POLYNOMIAL 28

4.9IMPLEMENTATION OF REED-SOLOMON DECODERS 28

4.9.1HARDWARE IMPLEMENTATION 28

4.9.2SOFTWARE IMPLEMENTATION 28

5. MATHEMATICAL THEOREMS 30

5.1 GROUPS 30

5.2 FIELDS 30

5 .2.1 GLAOIS FIELDS 32

5.2.2 PRIMITIVE POLYNOMIAL 33

5.3 SIMPLIFIED MIN-SUM DECODING ALGORITHM 34

5.3.1 THE EXTENDED MIN-SUM DECODING ALGORITHM 35

5.3.2 SIMPLIFIED MIN-SUM -DECODING ALGORITHM 35

5.4 BARREL SHIFTER 36

5.4.1 IMPLEMENTATION 36

6. HARDWARE AND SOFTWARE 38

6.1 HARDWARE DETAILS 386.1.1 FEATURES 38



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6.2 XILINX ISE TOOL FLOW 38

6.2.1 DESIGN ENTRY 39

6.2.2 SYNTHESIS 39

6.2.3 IMPLEMENTATION 39

6.2.4 VERIFICATION 39

6.2.5 DEVICE CONFIGURATION 40

7. RESULTS AND DISCUSSION 42

7.1 SYNTHESIS SUMMARY 41

7.2 INPUT 44

7.3 RTL SCHEMATIC 45

7.4 DEVICE UTILIZATION SUMMARY 46

7.5 SIMULATION RESULT 47

8. CONCLUSION AND FUTURE ENHANCEMENT 48

8.1 CONCLUSION 48

8.2 FUTURE WORK 48

REFERENCES 49



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LIST OF FIGURES

FIGURE NO TITLE PAGE NO

3.1 Basic Communication System 17

3.2 Channel transition diagram for the BSC. 18

4.1 Reed Solomon typical System 21

4.2 Reed Solomon Codeword 22

4.3 Graph between SNR and Bit error rate (BER) 24

4.4 Architecture for a Systematic RS(255,249) Encoder 26

4.4 Architecture for a Systematic RS(255,249) Decoder 27

5.1 Permutation Network 33

6.1 Implementation Flow 40

6.2 ISE Simulation Flow 41

7.1 Test Bench Input Waveform 44

7.2 RTL Schematic View 45

7.3 RTL Internal View 45

7.4 Device Utilization Summary 46

7.5 Simulation Output of RS Decoder 47



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LIST OF TABLES

TABLE NO TITLE PAGE NO

3.1 ERROR CORRECTION 13

4.1 CODE RATE 29

5.1 SOME PRIMITIVE POLYNOMIALS 34



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LIST OF ABBREVIATIONS

ADSL ASYMMETRIC DIGITAL SUBSCRIBER LINE

CD COMPACT DISCS

CER CODEWORD ERROR RATE

CN CHECK NODE

DRAM DYNAMIC RANDOM ACCESS MEMORY

DSP DIGITAL SIGNAL PROCESSING

DVD DIGITAL VIDEO DISCS

ECC ERROR CORRECTION CODING

EMSA EXTENDED MIN-SUM ALGORITHM

FEC FORWARD ERROR CORRECTION

FPGA FIELD PROGRAMMABLE GATE ARRAY

GEC GILBERT-ELLIOT CHANNEL

HDSL HIGH-BIT-RATE DIGITAL SUBSCRIBER LINE

LDPC LOW-DENSITY PARITY-CHECK CODE

MLC MULTI LEVEL CELL

NB LDPC NON BINARY LOW-DENSITY PARITY-CHECK

CODE

QBC QUEUE-BASED CHANNEL

QC-LDPC QUASI-CYCLIC LOW-DENSITY PARITY-HECK

QOS QUALITY OF SERVICE

RS REED SOLOMON CODE

RTL RESISTOR – TRANSISTOR LOGIC

SMSA SIMPLIFIED MIN-SUM DECODING ALGORITHM

SNR SIGNAL-TO-NOISE RATIO

VLSI VERY-LARGE-SCALE INTEGRATION

VN VARIABLE NODE

design and implementation of reed solomon code used on smsa in fpga

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