design and implementation of sdr based qpsk transceiver using fpga
TRANSCRIPT
Design and Implementation of Software-defined Radio (SDR) Based QPSK Transceiver Using FPGA
25/10/2012, Sarajevo
MASTER THESIS
Student: Tarik KazazMentor: Prof. Dr. Mesud Hadžialić
IX International Symposium on Telecommunications – BIHTEL 2012
Introduction Trends in Telecommunications Software-defined radio differences compared to other
radios FPGA as a platform for the implementation of SDR
Software tools and Hardware platform Implementation
Design of QPSK modulator and Costas loop Analysis of simulation results Analysis of results after implementation
Conclusion
PRESENTATION OVERVIEW
2/17
Different areas of research - apparently similar goal: Wired Communications (philosophy of Software Defined Network) Wireless Communications (Cognitive Radio is goal – basis is SDR)
INTRODUCTION
3/17
Trends
Examples of academic research projects: NetFPGA (openFlow) GNU Radio, OSSIE, openBTS, USRP, WARP
Projects
SOFTWARE-DEFINED RADIO DIFFERENCES COMPARED TO OTHER RADIOS
Application Design Upgrade Cycle
4/17
• Multiple variable systems, protocols, interfaces
• Interface with diverse systems
• Wide rage of services with variable QoS
• Fixed number of systems• Reconfigurability decided
at design time• Support multiple services
chosen at design time
• Create waveforms • Negotiate new interfaces• Adjusts operations to
meet QoS required by the application for the signal environment
• Traditional RF Design• Traditional Baseband
Design
• Conventional Radio +• Software Architecture• Reconfigurability• Provisions for easy
upgrades
• SDR +• Intelligence• Awareness• Learning• Observation
• Cannot be made
„future proof“• Typically radios are not
upgradeable
• Ideally software radios could be „future proof“
• Many different external upgrade mechanisms
• Over-the-Air (OTA)
• SDR upgrade
mechanism• Internal upgrades• Collaborative upgrades
Conv
entio
nal
Softw
are
Cogn
itive
5/17
are set by their operators
can adjust themselves to accomodate
anticipated events
can sense their environment and
learn how to adapt
Fixed radios
Adaptive radios
Cognitive radios
SOFTWARE-DEFINED RADIO DIFFERENCES COMPARED TO OTHER RADIOS
5/17
are set by their operators
can adjust themselves to accomodate
anticipated events
can sense their environment and
learn how to adapt
Fixed radios
Adaptive radios
Cognitive radios
Cognitive radios require:
• Sensing• Adaptation• Learning
SOFTWARE-DEFINED RADIO DIFFERENCES COMPARED TO OTHER RADIOS
6/17
FPGA as a platform for the realization of SDR
How to implement the last two concepts?
• Use a reconfigurable platform,• implement multiple standards and protocols for
the management• all implement on a single chip.
ASICFPGA
DSP
energy consumption
prog
ram
mab
ility
Software tools and Hardware platform
Software tools:• Altera DSP Builder• Xilinx System Generator• Synphony Model Compiler• Simulink HDL Coder
Hardware components:• ALTERA DE2-115 development board• HSMC Data Conversion card (AD i DA)
Jampers
Cyclone IV 2C70 FPGALogic elements 114.480
Embedded memory 3.888 Kbit
Embedded multipliers (18x18) 266
PLL 4
I/O pins 528
AD/DA conversion card
Number of AD converters 2
Number of DA converters (2 channels) 1Resolution & sample rate for AD converters 14 bita & 150 MspsResolution & sample rate for DA converters 14 bita & 250 Msps
7/17
Design of QPSK modulator
8/17
1Out1
Uni Bi
Unipolar u Bipolar 1
Uni Bi
Unipolar u Bipolar
In1
In2
Out1
Sum
In1
Ig
Qg
S/P konverzi ja
Ig
Qg
Ig_iz
Qg_iz
RRC fi lteri
soutx10+x3+1
Pseudo slucajni generator
Sin
Cos
Numericki kontrolisani osci lator
In1Out1
Naduzorkovanje1
In1 Out1
Naduzorkovanje
a[1]:[13]
b[1]:[13]r [2]:[26]X
Multiplier1
a[1]:[13]
b[1]:[13]r [2]:[26]X
MultiplierInput Output
Konverzi jaQ13 u B14_
o13:0
DB
BIT
BIT
BIT
SBF_2_13
SBF_2_13 SBF_2_13
SBF_2_13
SBF_2_26
SBF_2_26
UINT_14
SBF_1_13
SBF_1_13
SBF_1_13
SBF_1_13
SBF_1_13 double
Pseudorandom generator
S/P & Unipolar to Bipolar conversion
Upsampling i RRC filtering
Numerically controlled oscillator
Multiplication by a carrier signal and
summation
Scaling and conversion in UINT_ 14
Design of Costas loop
9/17
Conversion to SBF1_13
Multiplication of recieved signal with the recovered carrier signal and scaling
LP filtering and NCO
Phase detector
Loop filter (proportional integrator)
2
Out2
1
Out1
In1Out1
Skaliranje1
In1Out1
Skaliranje
In1
Sin
Cos
Numericki kontrolisani oscilator1
In2
In7
Out1
Out5
Nisko propusni fil teri
a[1]:[13]
b[1]:[13]r [2]:[26]X
Multipl ier3
a[1]:[13]
b[1]:[13]r [2]:[26]X
Multipl ier2
Input Output
Konverzi jaB14 u Q2
In1 Out1
Filter petlje
In1
In2
Fazna greska
Ig
Qg
Detekcija faze
i13:0
ADB_D
1
In1
Analysis of simulation resultsSignals at the output of PN generatora
I channel signal after S/P conversion
I channel signal after unipolar to bipolar conversion
Q channel signal after S/P conversion
Q channel signal after unipolar to bipolar conversion
10/17
Analysis of simulation results
11/17
I channel signal after RRC filtering
I channel signal after multiplication with carrier signal
Q channel signal after RRC filtering
Q channel signal after multiplication with carrier signal
Analysis of simulation results
12/17
Eye diagram Constellation diagram
Analysis of simulation results
13/17
I channel signal after multiplication with carrier signal (receiving side)
I channel signal after LP filtering
Q channel signal after multiplication with carrier signal (receiving side)
Q channel signal after LP filtering
Analysis of results after implementation
14/17
I channel signal waveforms after RRC filtering Spectrum of I channel signal
Eye diagram for I channel Spectrum of carrier signal (output of NCO)
Analysis of results after implementation
15/17
Spectrum of signal after multiplication with carrier
Waveform of signal at the receiving side after multiplication with recovered carrier signal
Spectrum of signal at the receiving side after LP filtering
Waveform of signal after LP filtering
Analysis of results after implementation
16/17
Eye diagram (I channel) at the receiving side after LP filtering
CONCLUSION
17/17
SDR and Cognitive radio are the future of wireless communications
SDR concept extends the capabilities of conventional radio systems
The advent of FPGA integrated circuits has extended the implementation of SDR
Design and implementation of SDR system from higher level of abstraction (model) has its advantages and disadvantages
Simplicity of implementation
Troubleshooting based on results
of simulation
Restricts to existing blocks
Understanding the many blocks
Non universal skills
Thank you for your attention!