design and implementation of vlsi systems (en0160)
DESCRIPTION
Design and Implementation of VLSI Systems (EN0160). Sherief Reda Division of Engineering, Brown University Spring 2007. [sources: Weste/Addison Wesley – Rabaey Pearson]. Last time Gate layouts and stick diagrams This time MOS transistor theory (ideal case). - PowerPoint PPT PresentationTRANSCRIPT
![Page 1: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/1.jpg)
Design and Implementation of VLSI Systems(EN0160)
Sherief RedaDivision of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey Pearson]
![Page 2: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/2.jpg)
Lecture05: MOS transistor theory
• Last time– Gate layouts and stick diagrams
• This time– MOS transistor theory (ideal case)
![Page 3: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/3.jpg)
gate-oxide-body sandwich = capacitor
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
(b)
+-
0 < Vg < Vt
depletion region
(c)
+-
Vg > Vt
depletion regioninversion region
Operating modes• Accumulation • Depletion• Inversion
• The charge accumulated is proportional to the excess gate-channel voltage (Vgc-Vt)
![Page 4: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/4.jpg)
The MOS transistor has three regions of operation
• Cut off
Vgs < Vt
• Linear (resistor):
Vgs > Vt & Vds < Vgs-Vt
Current α Vds
• Saturation:
Vgs > Vt and Vds ≥ Vgs-Vt
Current is independent of Vds
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
![Page 5: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/5.jpg)
How to calculate the current value?
• MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel
• Qchannel = CV
• C = εoxWL/tox = CoxWL (where Cox=εox/tox)
• V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.9)
polysilicongate
![Page 6: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/6.jpg)
Carrier velocity is a factor in determining the current
• Charge is carried by electrons• Carrier velocity v proportional to lateral E-field
between source and drain• v = μE μ called mobility
• E = Vds/L
• Time for carrier to cross channel:
t = L / v
![Page 7: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/7.jpg)
I=Q/t
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
tW VC V V VL
VV V V
![Page 8: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/8.jpg)
In linear mode (Vgs > Vt & Vds < Vgs-Vt)
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
tW VC V V VL
VV V V
Can be ignored for small Vds
For a given Vgs, Ids is proportional (linear) to Vds
![Page 9: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/9.jpg)
In saturation mode (Vgs > Vt and Vds ≥ Vgs-Vt)
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
tW VC V V VL
VV V V
22
2
dsatds gs t dsat
gs t
VI V V V
V V
Now drain voltage no longer increases current
![Page 10: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/10.jpg)
Operation modes summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
0 1 2 3 4 50
0.5
1
1.5
2
2.5
Vds
I ds (m
A)
Vgs = 5
Vgs = 4
Vgs = 3
Vgs = 2
Vgs = 1
– 0.6 micron process
– tox = 100 Å
– = 350 cm2/V*s
– Vt = 0.7 V
– W/L = 4/2
![Page 11: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/11.jpg)
PMOS is similar
![Page 12: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/12.jpg)
What happens when we construct a INV (PMOS+NMOS)?
![Page 13: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/13.jpg)
Inverter voltage transfer function
AB
C
ED
![Page 14: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/14.jpg)
Summary
• This lecture– Ideal transistor modeling
• Next lecture– Non ideal transistor modeling
![Page 15: Design and Implementation of VLSI Systems (EN0160)](https://reader035.vdocument.in/reader035/viewer/2022081506/56813bab550346895da4dd7a/html5/thumbnails/15.jpg)
Inverter current transfer function