design and realization of hf station prototype, james baskaradas #, anna lisa saverino *, amerigo...

Design and Realization of HF Station PrototypeJames Baskaradas#,

Anna Lisa Saverino*,Amerigo Capria*.

#INGV, Roma *RaSS - CNIT, Pisa

Overview of the presentation

2SWING Final Meeting | CNIT - Pisa, Italy13/12/2013

Introduction

Technology Overview

Tx/Rx Antenna System

Transmitter Architecture

Receiver Architecture

Chirp experiment

PSK experiment

Conclusion

Aim


Design and Development of a Robust HF (shortwave) radio link.

Main critical aspects

Full transceiver;

Low power;

Remote controlled;

Modular and Reconfigurable

Analog


DI GITALIZZATORE1_1. DSN 1. 1

ADC BOARD

ISTI TUTO NAZIONALE di GEOFI SI CA e VULCANOLOGIA

C

1 1Tuesday, June 04, 2002

Tit le

Size Document Number Rev

Date: Sheet of

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCCVCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VDD

VDD

VDD

/TXon-of f

DSP_D1DSP_D2DSP_D3DSP_D4DSP_D5DSP_D6

DSP_D8DSP_D9DSP_D10DSP_D11DSP_D12DSP_D13

DSP_D15

DSP_D11DSP_D12

DSP_D15

DSP_BI O

DSP_BI O

400kHz_CK

/TXon-of f

400kHz_CK

DSP_D1DSP_D2DSP_D3DSP_D4DSP_D5DSP_D6DSP_D7

RXon-of f

/RXon-of f

DSP_D14

DSP_D10

DSP_D14DSP_D13

DSP_D9DSP_D8

DSP_A3

DSP_D7DSP_A1

VCA

VCA

VCA

VCA

DSP_D6

DSP_D3

DSP_D5

DSP_D7

DSP_D2

DSP_D4

DSP_D1

DSP_A0

DSP_A2

DSP_D0

U974ALS30

1

2345611

12

8

R6

22

C13

47pF

C15

22nF

C18

22nF

C12

100pF

C16

22nF

U8D74LS125

12 11

13

U8A

74LS125

23

1

U8B

74LS125

5 6

4

R5330

C11100nF

U12

74ALS193

151

109

54

1114

3267

1213

ABCD

UPDNLOADCLR

QAQBQCQD

COBO

U5B

74LS00

45

6

U5C

74LS00

910

8

C10

1uF

J1

FI SCHER

1

2

U10

74ALS193

151

109

54

1114

3267

1213

ABCD

UPDNLOADCLR

QAQBQCQD

COBO

U11A

74LS74A

2

35

6

41

D

CLKQ

Q

PRCL

U8C

74LS125

9 8

10

U7

74ALS138

1 2 3 6 4

5

15 14 13 12 11 10 9 7

A B C G1

G2A

G2B

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

U13A

74LS123

14

15

1

23

13

4

CEXT

REXT/CEXT

A

BCLR

Q

Q

R2

10k

C91nF

C8100nF

C4

22nF

C7

100pF

C1

22nF

U16

TDA 8703

12

13

14

15

23

24

1

2

16 22 8 17

4

5

9

63

10

18 19 20

7

D7

D6

D5

D4

D3

D2

D1

D0

CLK

/CE VI

/CLK

VRB

DEC

VRT

NCAGND

NC

VCCD

VCCO

DGND

VCCA

C3

22nF

R1

22

U1

TDA 870312

13

14

15

23

24

1

2

16 22 8 17

4

5

9

63

10

18 19 20

7

D7

D6

D5

D4

D3

D2

D1

D0

CLK

/CE

VI /CLK

VRB

DEC

VRT

NCAGND

NC

VCCD

VCCO

DGND

VCCA

C27

100nF

C25

100nF

C21100nF

C29100nF

C24100nF

C31100nF

C20100nF

C19100nF

U5A

74LS00

12

3

U2A

74LS112

3

1

2

5

6

415

J

CLK

K

Q

Q

PRCL

R3

100

U2B

74LS112

11

13

12

9

7

1014

J

CLK

K

Q

Q

PRCL

C22100nF

C23100nF

U4C

DI N64_AC

C1C2C3C4C5C6C7C8C9

C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

+C17

22uF

+ C1422uF

+

C2

22uF

U17

74LS245

23456789

191

1817161514131211

A1A2A3A4A5A6A7A8

GDI R

B1B2B3B4B5B6B7B8

U3

74LS245

23456789

191

1817161514131211

A1A2A3A4A5A6A7A8

GDI R

B1B2B3B4B5B6B7B8

C30100nF

U15

CY7C185

21 23 24 25

22

2 3 4 5

27

6 7 8 9 101918171615131211

14

20

26

28

1

A0 A1 A2 A3

/OE

A4 A5 A6 A7

WE

A8 A9

A10

A11

A12

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

I/O

0

GND

/CE1

CE2

VCC

NC

U6

CY7C185

21 23 24 25

22

2 3 4 5

27

6 7 8 9 101918171615131211

14

20

26

28

1

A0 A1 A2 A3

/OE

A4 A5 A6 A7

WE

A8 A9 A10

A11

A12

I/O

7

I/O

6

I/O

5

I/O

4

I/O

3

I/O

2

I/O

1

I/O

0

GND

/CE1

CE2

VCC

NC

U18

74LS245

23456789

191

1817161514131211

A1A2A3A4A5A6A7A8

GDI R

B1B2B3B4B5B6B7B8

U14

74ALS193

15

1

109

54

1114

3267

1213

A

B

CD

UPDNLOADCLR

QAQBQCQD

COBO

R20

R17R16

R18

C53C50C48 C49 C54C51C47 C52

R21 R22 R23 R24 R25 R26 R27

R15

C43C42C41C40

U4A

DI N64_AC

A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

R19 C44

+ C55

10uF

+ C56

10uF

C58100nFC57100nF

+ C522uF

C6

47pF

C46

0. 1pF

C26 100nF

R13

C37 C38

R12R7

C39C35

R11R10 R14

C36C32 C34

R9R8

C33

R29

470

R28

470

U19

LM78051

3

2VI N

GND

VOUT

C45

100nF

C28100nF

R4100

U5D

74LS00

12

1311

R31

470

R32

80

C59

150pF

R30100 D0

D1

D2

D3

D4

D5

D6

D7

D7

D6

D5

D4

D3

D2

D1

D0

I_CK

I_SAMPLE

Q_SAMPLE

200kHz

100kHz

[ 0 ]

[ 1 ]

[ 2 ]

100kHz

[ 3 ]

Q_CK

[ 5 ]

[ 5 ]

IF#3 in

DSP_IS

[ 4 ]

[ 6 ] [ 7 ]

[ 7 ]

[ 8 ]

[ 9 ]

[ 10 ]

TIMING_CODE1_0.DSN (timing_code1.sch) 1.0

TIMING-CODE BOARD

ISTITUTO NAZIONALE DI GEOFISICA e VULCANOLOGIA

B

1 2Thursday, October 25, 2001

Title

Size Document Number Rev

Date: Sheet of

VCC

VCC

VCC

+VDD

-VDD

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC VCC

VCC

VCC

TXON_OFF

TOTAL_CODE

PCD0

PCD2

PCD6

PCD7

PCD4

PCD6

PCD3

PCD0

PCD5

PCD2

/WRRESET

A1

PCD3PCD3PCD3PCD3

PCD6PCD6PCD6PCD6PCD6PCD6PCD6

/RD

PCD2PCD2PCD2

A0

PCD0

PCD5PCD5PCD5PCD5PCD5PCD5PCD4PCD4PCD4PCD4PCD4

PCD3PCD4PCD5

PCD7

CS#1

A1A0/WR

PCD7

PCD6

PCD5

PCD4

PCD3

PCD2

PCD0

CS#1CS#2CS#3

CS#2

CS#3

PCD1

PCD1

PCD1

PCD1PCD1

PCD7PCD7PCD7PCD7PCD7PCD7PCD7PCD7

SYS0SYS1SYS2SYS3

SYS7

SYS4SYS5SYS6

SYS0SYS1SYS2SYS3SYS4SYS5SYS6SYS7

/RD

/RD/WRA0A1RESET

/RD/WRA0A1RESET

TX

C1/C2

/TX

ON_OFF

ON_OFF

U11

74LS165

1011121314

3456

215

1

9

7

SERABCDEFGH

CLKINH

SH/LD

QH

QH

U13

74LS165

1011121314

3456

2

151

9

7

SERABCDEFGH

CLK

INHSH/LD

QH

QH

U5

8255

3433323130292827

536

98

356

432140393837

1819202122232425

1415161713121110

D0D1D2D3D4D5D6D7

RDWRA0A1RESETCS

PA0PA1PA2PA3PA4PA5PA6PA7

PB0PB1PB2PB3PB4PB5PB6PB7

PC0PC1PC2PC3PC4PC5PC6PC7

U2

74LS165

1011121314

3456

215

1

9

7

SERABCDEFGH

CLKINH

SH/LD

QH

QH

U6

74LS165

1011121314

3456

2

151

9

7

SERABCDEFGH

CLK

INHSH/LD

QH

QH

U12

8255

3433323130292827

536

98

356

432140393837

1819202122232425

1415161713121110

D0D1D2D3D4D5D6D7

RDWRA0A1RESETCS

PA0PA1PA2PA3PA4PA5PA6PA7

PB0PB1PB2PB3PB4PB5PB6PB7

PC0PC1PC2PC3PC4PC5PC6PC7

U1A

74LS10

12

1312

R127K

C6

100p

R227K

U7A

74LS123

14

15

1

23

13

4

CEXT

REXT/CEXT

A

BCLR

Q

Q

U9C

74LS04

56

U4B

74LS00

456

U9A

74LS04

12

U3A

74LS74

2

3

5

6

41

D

CLK

Q

Q

PRCL

U10A

DIN64_AC

A1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

A1A2A3A4A5A6A7A8A9

A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32

C8

100p

U7B

74LS123

6

7

910

115

12

CEXT

REXT/CEXT

AB

CLRQ

Q

U15

74LS92

141

67

1211

98

AB

R0(1)R0(2)

QAQBQCQD

U10C

DIN64_AC

C1C2C3C4C5C6C7C8C9

C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

C1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32

U9B

74LS04

3 4

C4100nF

C1100nF

U4D74LS00

12 1311

U1B

74LS10

345

6

C2

100nF

U4A

74LS00

1

23

J2

BNC

1

2

U14

8254

8 7 6 5 4 3 2 1 22 23 19 20 21

9 11 10 15 14 13 18 16 17

D0 D1 D2 D3 D4 D5 D6 D7 RD WR

A0 A1 CS

CLK0 G

0O

UT0

CLK1 G

1O

UT1

CLK2 G

2O

UT2

C9100nF

C12100nF

C7100nF

C13100nF

C5100nF

C14100nF

C11

100nF

U4C

74LS00

9

108

J3BNC

1

2

C10100nF

C15100nF

C3100nF

CODE1

CODE2DATA BUS

CONTROL BUS

STATUS SYSTEM BUS

SYSTEM STATUS BUS

[ 0 ]

[ 0 ]

[ 0 ][ 1 ]

[ 1 ]

[ 1 ]

CODE 1 OUT

CODE 2 OUT

[ 2 ]

[ 3 ]

[ 4 ]

[ 5 ]

[ 5 ]

[ 6 ]

[ 6 ]

[ 6 ]

[ 7 ]

[ 9 ]

[ 9 ]

[ 8 ]

[ 8 ]

[ 10 ]

[ 11 ]

[ 10 ]

[ 12 ]

[ 13 ]

[ 14 ]

[ 2 ]

ATRG out

400kHz_CK

TXon_off

/TXon_off

/ATRG out

[ 10 ]

C1/C2

ASIC/SOC


High resolution TDC25 ps binning~5 man years design~2 man years test and design fixTotal design price: ~1 million $Production cost: 10$/chipProduction volume: ~50k chipsTotal production cost: 500k$

Image from presentation of Dr.,Jorgen Christiansen,CERN

Hybrid


Tx/RX Antenna System


Gain(dBi) Frequency(MHz)

< -13 1-2

-13 2

-6 3

-3 5

1 7.5

0 10

0 20

-1 >20

Transmitter Architecture


Transmitter Architecture:USRP


Dual 100MS/s, 14-bit ADC;Dual 400MS/s, 16-bit DAC;DDC/DUC with 25mHz resolution;Up to 50MS/s Gigabit Ethernet streaming;Gigabit Ethernet interface to host;Fully coherent MIMO capability.

USRP N210 features

Transmitter Architecture:USRP


Transmitter Architecture: HPA


Type Class AB MOSFET

Frequency 100kHz-30MHz

Rated power 500W

Cooling Forced air, front to rear

Mains power110-240V,50-60Hz,single phase,

500VA/750VA/1.5kVA max

Receiver Architecture


Receiver Architecture: BPF


Receiver Architecture:LNA


Gain versus frequency

Model: ZFL-1000LN+Company: Mini-Circuits

Operative Band 0.1 MHz – 1000 MHz

Noise Figure 2.9 dB

Gain 20dB

Output power versus frequency

Low Noise Amplifier (LNA)

Tx/Rx Synchronization


SWING Node locations


Chirp Experiment : why ?


Single reconfigurable hardware for : • probing the ionosphere (including non-reciprocity* of

channel)• HF communication terminal

• wide band of usable frequency from ionospheric prediction• disturbed link channel (ionosphere)

Chirp Experiment : How ?


Fine frequency step (0,001Hz) to avoid unwanted noise in the output spectrum

Chirp Experiment : Transmitter


Transmitter station

Frequency sweep 1 MHz – 30MHz

Frequency step 0,001Hz

scan rate <= 100kHz

Chirp Experiment : Receiver -1


Spectrum monitor receiverChirp receiver

User Interface of the Spectrum monitor Receiver

Receiver station

Chirp Experiment : Receiver -2


User interface of the Chirp Receiver

Chirp Experiment : Results -1/2




Transmitter Power 20W

Received signal power -95,67dBm

PSK Experiment


Aim Design and Development of a demonstrator for data transmission over HF radio links.

Experiment Issues

Extreme space and time-varying propagation channel;

External interference (congestion of the HF band);

High background noise level.

PSK Experiment


Simulated Scenario

Connection type: point-to-point; Carrier frequency : single; Modulation type: PSK.

Simulation equipment

USRP Hardware; LabVIEW programming language.

PSK Experiment


Transmitter functions Convert the message to bits; Rearrange the bit-stream in packets;Apply modulation; Write to USRP for the transmission.

Receiver functions Apply demodulation;

Check for valid packets and organization in the correct order;

Full text reconstruction.

PSK Experiment


Transmitter/Receiver User Interface USRP IP Address

1.I/Q rate:Specifies the sample rate of the baseband I/Q data

for Tx or Rx in samples per second (S/s);

2.Carrier :Carrier frequency in Hz of

the RF signal;

3.Gain:Specifies the gain, in dB, applied to the RF signal

for Rx and Tx;.

4.TX/RX antenna:Refers to the connectors

on the device front panel;

Actual TX/RX ParametersRefers to a Tx/Rx values supported by the device.

Eb/N0

Specifies the desired Eb/N0 of the output complex waveform in dB;

Tx/RX Constellation GraphSpecifies the detected symbol locations and

the transitions between those symbols;

Raw Received SignalReceived Message

PSK Experiment


Transmitter/Receiver Modulation Interface

Modulation Type

Pulse shaping and matched Filters This filter is applied to each symbol to:

1. Reduce the amplitude and phase transition of modulated signal;2. Reduce Inter-Symbol Interference (ISI);

3. Maximize the SNR

Sets the type of modulation and parameters for a pulse shaping filter.

Spectrum with noiseSpectrum of transmitted

base-band complex waveform with noise

PSK Experiment


Transmitter Packet Interface

1.Guard Band:Protects against the filter

effect;

2.Sync Seq:Is the sequence for the

carrier and clock recovery;

3. Packet Number:Is used to reorder the packets and to detect

missing packets;

4. Data :Represents the length of

the useful data;

5. Pad Data:Represents the number of the samples appended at

the end of the signal in order to have a constant

packet size;

Constellation Graph:Shows how the detected

symbol locations and the transitions between

those symbols are modified by the presence

of the noise.

PSK Experiment


Receiver Debug Interface

Sync FoundChecks for valid packet

Error outRepresents error information

Correct Packet RxRepresents the number of the correct received

packets

Conclusion


Design and Development of the SWING demonstrator

Simulation equipment

USRP:1. SDR implementation;2. Low cost and extremely flexible solution;

LabVIEW:1. General purpose software for data processing and

instruments control.

Good candidate for the implementation of HF communication because it can directly sample the entire HF band.

USRP and HF band

Conclusion


Design and Development of a demonstrator for data transmission over HF radio links (PSK experiment):

1. Modulation type: PSK;2. Single carrier;

Main activities

Frequency selection in order to establish the HF link (Chirp experiment):

1. Ionospheric channel;2. External noise level;

The functionality of the system has been experimentally demonstrated in a closed-loop configuration. Moreover the effect of additive white Gaussian noise has been evaluated by using a set of different signal to noise ratios.

Conclusion


PSK and HF link : Experimental validation

Realization of a Fully Automated System:1.Spectral sensing (low noise, HF band occupancy);2.Ionospheric monitoring;3.Optimal frequency selection (chirp system);4.Data transmission over HF link (PSK system)

Future Developments

PSK and Chirp demonstrators : Integration


Thank you for your attention!

THE END

Questions?

design and realization of hf station prototype, james baskaradas #, anna lisa saverino *, amerigo...

Documents

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