design considerations in low power design

8/13/2019 Design Considerations in Low Power Design

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Nanoscale CMOS Technologies

Opportunities and Challenges

Trond Ytterdal

Circuits and Systems Group

Department of Electronics and Telecommunication

Norwegian University of Science and Technology(NTNU)

2006-2007: Sabbatical at UofT

Room: BA5106

[email protected]

1 Trond Ytterdal, Department of Electronics and Telecommunication

October 11, 2006


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Outline

Introduction

How does transistor performance change as*

Analog circuit performance

How does analo circuit erformance chan e as

technology is scaled down

*



3/37

CMOS technology downscaling

3m2m

1.5m

10

[

m]

Data from INTEL

ITRS Roadmap

90nm

0.18m

. m0.5m

0.35m

45nm0.1

rinted

gatelengt

18nm

nm

0.01

1970 1975 1980 1985 1990 1995 2000 2005 2010 2015

Year

10

1

Vdd[V]

0.1

1970 1975 1980 1985 1990 1995 2000 2005 2010 2015

Year


Gate length divided by two approximately every 5 years


4/37

Transistor performance

Transistor performance metrics for analog and RF

Transconductance

Intrinsic ain m s

Capacitances

Maximum o eratin fre uenc

Efficiency (gm/Id)

Linearity

Noise

Mismatch Gate leakage



5/37

Transconductance and intrinsic gain1.E-03

1.E-05

1.E-04

.

65 nm90 nm

0.13 um

0.18 um

Transconductance is, for all practicalpurposes, independent of the

technology node

1.E-07

1.E-06

gm

[S]

seffoxd vVWcI

=

=

or a ve oc y sa ura e c anne :

1.E-09

1.E-08

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

Minimum gate length, same W/L

Vds = 1/2VDD1

; ox

soxm

LcLW

Drain current [A]

60

70

65 nm

90 nm

0.13 um


Vds = 1/2VDD Intrinsic gain is reduced as

sca enotoesm

g

30

40

50

gm/gds

0.18 um .

65nm node the maximum intrinsic

gain is reduced by more than 80%

compared to the gain at the 0.18m

10

20

node.


0

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

Drain current [A]


6/37

Transistor capacitances

1.0

1.1Cgs Minimum gate length, same W/L ; Vds = 0

0.7

0.8

0.9

[fF]

0.4

0.5

0.6

pacitanc

0.1

0.20.3C

a

0.0

90nm 0.13um 0.18um

Capacitances extracted from NMOS having minimum

drain and source areas for the given W/L (~3).



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Maximum operating frequency

The maximum speed of an amplifier is limited by the

of a transistor:

)(2 dbgdgsT

CCC ++=

1.0E+12 2.5E-04

1.0E+10

1.0E+11

[

Hz]

65 nm

90 nm0.13 um

0.18 um

-

2.0E-04


Vds = 1/2VDD

1.0E+07

1.0E+08

1.0E+09

m/(

Cgs

+Cdb

)/2

1.0E-04

.

Id[

A]

1.0E+05

1.0E+06

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03


Vds= 1/2VDD

0.0E+00

5.0E-05

1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

130nm

180nm


ra n curren T


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Potential speed improvement

6.0

potential improvement4.0

5.0

ento

fscaling . .

obtained compared to

realization in a 0.18m3.0edimprove

technology1.0

.

Potential

sp

Minimum gate length, same W/L ; Vds = 1/2VDD

Speed potential normali zed to the 0.18m node.

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

Drain current [A]



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Transistor efficiency (gm/ID)

30

3590nm

0.13um

0.18um

Minimum gate length; W/L = 5; Vds = 1V

20

25

1/V

]

0.25um

10

15

gm

/ID

5

1.0E-12 1.0E-10 1.0E-08 1.0E-06 1.0E-04 1.0E-02

Drain current [A]

the buck) in weak inversion



10/37

Linearity (1)The Taylor expansion of the small signal drain current of a MOS transistorcan be written as:

L+++= vavavgi 32 32

L

L++++ dsgdsgdsds vavavg dsds

mm

32

32

32

L++++ dsgsggdsgsggdsgsgg

sgsgsm

vvavvavvadsmdsmdsm

mbmb

332 222

2

L

L

++++

++++

bsdsggbsdsggbsdsgg

bsgsggbsgsggbsgsgg

vvavvavva

vvavvavva

mbdsmbdsmbds

mbmmbmmbm

332 222

2

22

Here, the coefficients are the higher order derivatives of the total drain

L++ bsdsgsggg vvva mbdsm

.

2

21

2 dgI

am

=


gs


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Linearity (2)

1.0E-05

1.0E-04

1.0E-03

]

90nm

0.13um

0.18um

Second order

nonlinearity in

1.0E-09

1.0E-08

1.0E-07

. -

|a2gds|

[S/

conductance (gds)

increases as

1.0E-12

1.0E-11

1.0E-10

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

ec no ogy s

scaled down.

1.0E-02

90nm Second order

1.0E-04

. -

m[

S/V]

.

0.18umnon near y n

transconductance

almost

1.0E-06

. -

a2 independent of

technology


. -

1.0E-10 1.0E-09 1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03

Id [A]


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Noise

Equivalent noise PSD (power spectral density) referred tothe gate of a transistor connected in a common-source

configuration*:

dependentprocess;42 K

fWLc

K

g

TkV

oxmBng

+

=

Channel noise

Si-SiO2 interface noise

Minimum in weak inversion for given current

= inversionstrongin3/2n

Traditionally [1], the following expression is used for


*Transform valid up to a frequency ~gm/Cgd


13/37

Potential SNR (1)

Thermal noise

mBnd

d

gTkI

I

=

4

1

2 100

120

dB]

65nm

90nm

0.13um0.18um

60

80

10-6Id2/Ind

2)

ecreases a owcurrent 2010log(

Minimum gate length, same W/L ;Vds = 1V

inversion for a given

current

1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

Drain current [A]



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Potential SNR (2)

Flicker noise

22

=

mnd

d

g

WLf

I

I

75

80

[dB

]

65nm

90nm (L = 0.1um)

0.13um0.18um

d65

70

2/(Ind

2Agate

))

ecreases a owcurrent50

5510lo

g(I

Minimum gate length, same W/L ; Vds = VDD/2

inversion for a given

current

1.E-11 1.E-09 1.E-07 1.E-05 1.E-03

Drain current [A]



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Mismatch (1)

Mismatch of two matched transistors identical by design

can be characterized by:

WL

WLAVVVV VTTVTTTT

//with/2/

/)(with21

==+=

===

AVTandA depends on process, layout and more

Based on the quadratic MOS model, one can derive thefollowing well known formulas:

Same gate voltage:

2

Same drain current:

22

+=

VTd

m

d

d

I

g

I( ) 2

+= m

dVTG

gV



16/37

Mismatch (2)

Mismatch per unit area decreases as technologiesare scaled down

minoxVT LtA

Gate area required for any given (VT)

normalized to theLmin = 70nm

1000

From theory and ideal scaling:

100 100earea

n rea y AVT oes no sca e as

fast asLmin

m] 10

Relative

gat

10

AVT[

m

1

0.01 0.1 1 10

Minimum ate len th [m]

1

0.01 0.1 1 10


Experimental Data from [2]

Minimum gate length [m]


17/37

Gate leakage current (1)

Gate current can NOT be neglected in scaled down

technologies.

Dominated by tunneling current => Relatively

insensitive to device temperature.

1.E-06

1.E-05

1.E-04

90nm (simulated)0.13um0.13um (simulated)0.18um

Minimum gate length,

gate width = 100m

IG

VG 1.E-091.E-08

1.E-07

current[A]

1.E-12

1.E-11

1.E-10

Gate

1.E-14

1.E-13

0 0.5 1 1.5 2

Gate voltage [V]


g-flavor technologies


18/37

Gate leakage current (2)G

ig

g

Small signal equivalent

circuit assuming low to

ic itunnel

and strong inversion

ox gtunnel

At a given frequency the impedance of the two branches have the

same ma nitude and the currents i and i will be e ual in

magnitude. This frequency is given by

tunneloxgate gC =

ox

tunnelgate

C

gf

=

2

1


, c

the tradit ional case.


19/37

fgate versus technology

fgate is almost gate area 104

90nmn epen en an an approx ma e

expression is given in [3] as:

)6.13(2 gsox Vt 100101

1020.13m0.18m

gsgga e

Here,tox is the oxide thickness in 16 fgate

[Hz

]

-

10-3

10-2

10-1

g . and 0.51016 for PMOS.

10-7

10-610-5

shown to the right for three

different technologies. Veff[V]0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

10-8



20/37

Analog circuit performance

Analog and RF circuit performance metrics:

Speed



21/37

FOM definition

One commonly used Figure-of-merit (FOM)

fDR

PFOM

=2

Here,P is the power consumption,DR is the

that can be processed by the circuit Small is GOOD.



22/37

Dynamic range (1)

Here, we define the dynamic range (DR) as the ratio

amplitudes.*

If we assume that R is limited b noise on thelower side and the power supply voltage on the

upper side, we can write

rmsn

DDv

rmsn

pp

VV

VVDR

__ 22/ == (2)

where, Vpp is the maximum peak-to-peak value of the

signal, Vn_rms is the RMS noise voltage, v is thevo tage e c ency e ne y Vpp/VDD.


*The ratio of squared amplitudes is also a common definition


23/37

Dynamic range (2)

If we assume that matching limits DR on the lower

,

2

2/DDvpp

V

V

V

V

DR

== (3)

where is a yield parameter and (Vos) is thecircuit.

We observe for both 2 and 3 that DR scales with

VDD and vFor the rest of the talk we assume that DR

is limited by noise on the lower side



24/37

Signal-to-noise ratio (SNR)

SNR is defined as the ratio of the signal power to

. ,

maximum SNR given by

2_

2_ 8

)(

8 rmsn

DDv

rmsn

pp

V

V

V

VSNR

== (4)

If we compare (4) with (2), we see that

SNRR = 2



25/37

SNR versus powerDD

IDD voutVpp

Cv

Gm

v

VSS 1/f

Power: CfVCfVVqfVIVppivppiDDiDDDDDD

=

=

==

Here, i is the current efficiency of the transconductor and q/i is the charge

SNR: SNRTk

VV

SNR B

pp

pp8

8/ 22

==

rans erre rom e power supp y n one per o an . e ave assume a SS=

Only thermal noise is considered.

Combining the two equations we get the power required per pole versus SNR:


vi

=Based on [1] and [4]


26/37

Theoretical FOM

Rewriting (6) in terms of FOM:

vi

B

vi

B

DRfSNRf =

=

2

vi

FOM

=

Ideal world (v = i = 1):(7)TkFOM Bi 4=

Hence, one important question becomes:


v


27/37

FOMs based on measurements

FOMs calculated based on measured performance

obtained using (7) due to one or more of the

following: DR limited by distortion

Additional noise sources (e.g. flicker noise)

Clock power in switched-capacitor circuits Poor current efficiency of MOS transistors (it is even

as epen en

Parasitic capacitances

Smaller mismatch => larger dimensions => larger

parasitic capacitors



28/37

Reported FOMs for ADCs1.0E+14

1997199819992000

diss

sENOB

P

F2FM=

Phili s ISSCC04

1.0E+13

sions/J]

200220032004Selection from Walden

State-of-the-art 2004

Balmell i ISSCC04

Miyazaki ISSCC02

Moyal ISSCC03

1.0E+12

FM[

Conver

nAD12110-18(03)

Kwak (97)

AD9245(03)

Kelly, ISSCC01

,

Philips ISSCC03

Kulhalli ISSCC02

Bjrnsen ESSCIRC05[5]

gureofm

erit

nAD10120-13(03)

Hernes ISSCC04

1.0E+11Fi

Siragusa ISSCC04

1.0E+10

Conversion Rate [Sample/s]1 MHz 10 MHz 100 MHz 1 GHz


From [5]


29/37

Voltage efficiency (v) Assume that

= 0.25

0.30

65nm

90nm

where Vdsat

is the

sapp

0.15

0.20

t[V

]

0.13um

transistors

0.050.10

Vdsa

v when we scale downtechnology, Vdsat must be

0.00

-0.6 -0.4 -0.2 0 0.2 0.4 0.6

Ve [V]

scaled down at the same

rate as VDD.Not possible to scale

Vdsat much lower than75mV

v expected to decrease29 Trond Ytterdal, Department of Electronics and Telecommunication

FOMdegrades


30/37

Current efficiency (i)Assuming CMOS implementation:

The ain bandwidth GBW roduct of a sin le sta e OTA is iven b

C

gGBW m

=2

(8)

Heregm is the transconductance of the input transistor and Cis the load

capacitance.

,2_CTkV Brmsn =

,

2

2

8

)(

DRTk

VgGBW DDvm

= (9)

Hence, ifDR andgm is kept constant, the speed of the circuit decreases

with the square of the supply voltage.



31/37

Scenario 1: Dividing VDD

by 2

while keeping GBWandDR:

To keep it simple, assume that v does not change. From (9)

we note that to keep GBWwhen supply voltage is reduced by

m

It is common to change the W/L ratio and the drain current by

t e same re at ve amount n or er to eep effunc ange

(adding devices in parallel). Hence, to increasegmby a factor

of 4 bias current and W/L are increased b a factor of 4. If we

assume that all stages of the amplifier are scaled in the same

way, the current consumption will be increased by a factor of

our. Power consumption doubles i decreases FOMdegrades

31 Trond Ytterdal, Department of Electronics and TelecommunicationDownscaling will not help


32/37

Scenario 2: Increasing speed (1)

while keeping DR and VDD:25

30

3590nm

0.13um

0.18um

0.25um

Minimum gate length; W/L = 5; Vds = 1V

Assume that the frequency of

the first non-dominant pole is10

15

20

gm

/ID

[1/V]

margin requirements forces a

fixed ratio betweenfTand2.5E-04

0

5

1.0E-12 1.0E-10 1.0E-08 1.0E-06 1.0E-04 1.0E-02

Drain current [A]

.

Assume that the required1.5E-04

2.0E-04


Vds = 1/2VDD

spee s suc a we ave o

push the transistor deep into

strong inversion. 5.0E-05

1.0E-04Id[A]

90nm

130nm

0.0E+00

1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

fT[Hz]

180nm

i decreasesFOMde rades fTmax@90nm

32 Trond Ytterdal, Department of Electronics and TelecommunicationDownscaling will probably help


33/37

Scenario 2: Increasing speed (2)

Watch out for gain70

increasing speed50

60

90 nm

0.13 um

0.18 um

,

Vds = 1/2VDD

If speed increase is

obtained b increasin 2030g

m/gds

Veff, gain will decrease 010

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03

i decreasesFOMdegrades

Downscaling will not help



34/37

Maximizing FOM

Some guidelines for maximizing FOMin nanoscaleCMOS circuits:

Circuit level:

Maximize v by using as low Veffas possible Identify fTmax in your technology. Stay well below this

frequency to maximize i * se as g supp y vo age as poss e may e even

higher than allowed by the foundry)

Avoid high gain requirements (use, for example, gain

calibration Go to interleaved architectures if speed requirements

cause you to move dangerously close to fTmax*


*

or switch to a finer technology


35/37


36/37

List of symbols

Parameter DescriptionAgate Gate area

Parameter Description Mobility

ox

Cgs Gate-source capacitance

Cgd Gate-drain capacitance

T Absolute temperature

tox Oxide thickness

Cdb Drain-bulk capacitance

cox Oxide capacitance per gate area

VDD Supply voltage

Vds Drain-source voltage

ox x e capac ance

f Frequency

gm Transconductance

eff gs T

Vgs Gate-source voltage

vs Saturation velocity

gds Channel conductance

Id Drain current

VT Threshold voltage

W Gate width

B Bo tzmanns constant

L Gate length

L Minimum ate len th



37/37

References

[1] E.A. Vittoz, Low Power Design: Ways to Approach the Limits, Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC,

. - , . .

[2] K. Bult, Analog Design in Deep Sub-Micron CMOS, inProc. ESSCIRC

2000, pp. 11-17.[3] A. Annema et al., Analog Circuits in Ultra-Deep-Submicron CMOS,

IEEE J. of Solid-State Circuits, vol. 40, no. 1, Jan. 2005.

. . , - -

Analog Design, inAnalog Circuit Design, Editors R.S. van de Plaasche,W.M.C. Sansen, and J.H. Huijsing, Kluwer Academic Publishers, 1994.

[5] J. Bjrnsen, . Moldsvor, T. Sther, T. Ytterdal, A 220mW 14b 40MSPS

Gain Calibrated Pipelined ADC, inProc. European Solid-State Circuits

Conference (ESSCIRC) 2005, Grenoble, Sept. 12-14, pp. 165-168, 2005.


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